A A B B C C D D E E 1 1 2 2 3 3 4 4 Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date LA-3981P 0.3 Cover Sheet Custom 142Monday, October 22, 2007 2007/03/26 2006/07/26 Compal Electronics, Inc. REV:0.2 Mobile Merom uFCPGA with Satna Rosa Platform Schematics Document 2007-08-02 Compal confidential A A B B C C D D E E 1 1 2 2 3 3 4 4 Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date LA-3981P 0.3 Block Diagram Custom 242Monday, October 22, 2007 2007/03/26 2006/07/26 Compal Electronics, Inc. Power On/Off CKT. LPC BUS page 22 H_A#(3 31) page 27 BANK 0, 1, 2, 3 USB Conn 533/667/800MHz DMI DC/DC Interface CKT. Mobile Yonah/Merom USB2.0 FSB Clock Generator ICS9LPRS355 Power Circuit DC/DC IDE ODD Connector uFCPGA-478 CPU page 28 DDR2-SO-DIMM X2 page 31 page 4page 4,5,6 RTC CKT. page 15 DDR2 -400/533/667 page 4 page 7,8,9,10,11,12 SB ICH8 Thermal Sensor ADM1032AR page 13,14 page 18,19,20,21 page 19 Fan Control Dual Channel Touch Pad CONN. Int.KBD ENE KB926 page 30 page 30page 28 Page 32,33,34,35,36,37,38 PCI-E BUS page 28 LED SPI 25LF080A SPI ROM page 29 H_D#(0 63) LEON 1.0 (Merom +Crestline+ICH8) AC-LINK/Azalia page 22 SATA HDD Connector PATA Master page 22 Mini-Card WLAN NB Crestline SATA page 24 CX20561-12 Audio Conexant page 25 MODEM AMOM page 26 AMP & Audio Jack TPA6017A2 CX20548 page 16 page 17 LVDS Conn page 23 page 23 RTL8100CL RJ45/11 CONN Realtek CRT/TV-OUT PCI BUS File Name : LA-3981P Compal confidential Socket P USB Card Reader page 27 USB WebCam page 17 ZZZ1 PC B 5 5 4 4 3 3 2 2 1 1 D D C C B B A A Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date LA-3981P 0.3 Notes List 342Monday, October 22, 2007 2007/03/26 2006/07/26 Compal Electronics, Inc. 1 0 1 0 0 1 0 0A4 I2C / SMBUS ADDRESSING 1 0 1 0 0 0 0 0 D2 A0 CLOCK GENERATOR (EXT.) HEX DDR SO-DIMM 1 ADDRESS DDR SO-DIMM 0 1 1 0 1 0 0 1 0 DEVICE Symbol Note : : means Digital Ground : means Analog Ground @ : means just reserve , no build DEBUG@ : means just reserve for debug. SERIAL SENSOR (CPU) SMB_EC_CK2 SOURCE KB925 INVERTER BATT EEPROM THERMAL SODIMM CLK CHIP SMBUS Control Table SMB_CK_CLK1 SMB_CK_DAT1 ICH8 MINI CARD SMB_EC_DA2 SMB_EC_CK1 SMB_EC_DA1 KB925 LCD_CLK LCD_DAT Crestline LCD ADM1032 X X X XX X XX X XX X XX X XX X X X X XX X X VV V External PCI Devices IDSEL # PIRQREQ/GNT #DEVICE LAN AD22 0 A O O X +0.9V Voltage Rails S3 +3VS X X +3VALW +5VS S1 O +1.25VS +CPU_CORE OO OO X XX +VCCP power plane O O O O O X S5 S4/ Battery only XX X +B State +1.5VS +1.8V S5 S4/AC & Battery don't exist S5 S4/AC +5VALW S0 O O Jump-Short: PJP? VVV V BOM: 43151732L01(965GM) & 443151732L02(960GML) with card reader BOM: 43151732L03(965GM) & 43151732L04(960GML) without card reader 5 5 4 4 3 3 2 2 1 1 D D C C B B A A H_PROCHOT# OCP# XDP_TDI XDP_TMS XDP_TRST# XDP_TCK H_REQ#2 H_DBSY# H_ADS#H_A#3 H_A#22 H_A#19 XDP_TRST# H_REQ#4 H_ADSTB#0 H_A#18 H_TRDY#H_REQ#3 H_INTR H_HITM# H_A#6 H_A#26 H_FERR# H_DRDY# CLK_CPU_BCLK CLK_CPU_BCLK# H_A#4 H_A#23 H_A#32 H_BR0# H_A#7 H_A#13 H_THERMDC XDP_TCK H_RS#1 H_LOCK# H_A#5 H_A#25 H_A#21 H_A#10 H_A#34 H_NMI H_DEFER# H_REQ#0 XDP_DBRESET# H_BPRI# H_ADSTB#1 H_A#9 H_A#31 H_A#35 XDP_TMS H_INIT# H_A#30 H_A#24 H_A#16 H_A#11 H_RS#2 H_IGNNE# H_REQ#1 H_A#8 H_A#28 H_STPCLK# H_SMI# XDP_TDI H_A#27 H_A#20 H_A#15 H_THERMTRIP# H_RS#0 H_HIT# H_BNR# H_A20M# H_A#17 H_A#12 H_A#33 H_THERMDA H_A#29 H_A#14 H_IERR# H_THERMDA_R H_THERMDC_R SMB_EC_DA2 SMB_EC_CK2 H_THERMDA H_THERMDC L_THERM# SMB_EC_CK2 SMB_EC_DA2 THERM# FAN H_RESET# H_PROCHOT# DBRESET# THERM#L_THERM# OCP# 20 H_A#[3 16]7 H_ADSTB#07 H_REQ#07 H_REQ#17 H_REQ#27 H_REQ#47 H_A#[17 35]7 H_ADSTB#17 H_A20M#19 H_FERR#19 H_IGNNE#19 H_STPCLK#19 H_INTR19 H_NMI19 H_SMI#19 H_ADS# 7 H_BNR# 7 H_BPRI# 7 H_BR0# 7 H_THERMTRIP# 7,19 CLK_CPU_BCLK 15 CLK_CPU_BCLK# 15 H_RESET# 7 H_RS#0 7 H_RS#1 7 H_RS#2 7 H_TRDY# 7 H_DEFER# 7 H_DRDY# 7 H_DBSY# 7 H_INIT# 19 H_LOCK# 7 H_HIT# 7 H_HITM# 7 XDP_DBRESET# 20 H_REQ#37 SMB_EC_CK230 SMB_EC_DA230 FAN_PWM30 H_PROCHOT# 37 +VCCP +VCCP +VCCP +VCCP +3VS +3VS +5VS +3VS +3VS +3VS Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date LA-3981P 0.3 Merom(1/3)-AGTL+/XDP Custom 442Monday, October 22, 2007 2007/03/26 2006/03/10 Compal Electronics, Inc. H_THERMDA, H_THERMDC routing together, Trace width / Spacing = 10 / 10 mil For Merom, R14 and R15 are 0ohm For Penryn, R14 and R15 are 100ohm. Thermal Sensor ADM1032ARMZ PWM Fan Control circuit Address:100_1100 SP02000D000 S W-CONN ACES 85204-02001 2P P1.25 ACES_85204-02001_2P SP07000FP00 S SOCKET TYCO 2-1871873-2 478P H3 CPU SP07000FD00 S SOCKET FOXCONN PZ4782A-274M-41 478P H3 C5 4.7U_0805_10V4Z 1 2 C3 0.1U_0402_16V4Z 1 2 R414 0_0402_5% 1 2 C6 0.1U_0402_16V4Z 1 2 R2 15_0402_5% 1 2 R17 56_0402_5%@ 12 R13 68_0402_5% 12 R10 56_0402_5% 12 C2 0.1U_0402_16V4Z 1 2 R426 10K_0402_5% @ 12 S G D Q1 SI3456BDV-T1-E3_TSOP6 3 6 2 4 5 1 D26 RLZ5.1B_LL34 @ 12 R8 27_0402_5% 1 2 R15 0_0402_5% 1 2 R416 10K_0402_5% @ 12 C4 2200P_0402_50V7K 1 2 D1 RB751V_SOD323 2 1 R413 0_0402_5% @ 1 2 R427 10K_0402_5% @ 12 R7 560_0402_5% 1 2 R14 0_0402_5% 1 2 R3 39_0402_1% 1 2 U1 ADM1032ARMZ-2REEL_MSOP8 VDD 1 ALERT# 6 THERM# 4 GND 5 D+ 2 D- 3 SCLK 8 SDATA 7 R16 10K_0402_5% 1 2 R405 0_0402_5% 1 2 U2 TC7SH00FU_SSOP5 @ INB 1 INA 2 O 4 G 3 P 5 ADDR GROUP 0 ADDR GROUP 1 CONTROL XDP/ITP SIGNALS H CLK THERMAL RESERVED ICH JP2A Merom Ball-out Rev 1a CONN@ A[10]# N3 A[11]# P5 A[12]# P2 A[13]# L2 A[14]# P4 A[15]# P1 A[16]# R1 A[17]# Y2 A[18]# U5 A[19]# R3 A[20]# W6 A[21]# U4 A[22]# Y5 A[23]# U1 A[24]# R4 A[25]# T5 A[26]# T3 A[27]# W2 A[28]# W5 A[29]# Y4 A[3]# J4 A[30]# U2 A[31]# V4 RSVD[01] M4 RSVD[02] N5 RSVD[03] T2 RSVD[04] V3 RSVD[05] B2 RSVD[06] C3 RSVD[07] D2 RSVD[08] D22 A[4]# L5 A[5]# L4 A[6]# K5 A[7]# M3 A[8]# N2 A[9]# J1 A20M# A6 ADS# H1 ADSTB[0]# M1 ADSTB[1]# V1 RSVD[09] D3 BCLK[0] A22 BCLK[1] A21 BNR# E2 BPM[0]# AD4 BPM[1]# AD3 BPM[2]# AD1 BPM[3]# AC4 BPRI# G5 BR0# F1 DBR# C20 DBSY# E1 DEFER# H5 DRDY# F21 FERR# A5 HIT# G6 HITM# E4 IERR# D20 IGNNE# C4 INIT# B3 LINT0 C6 LINT1 B4 LOCK# H4 PRDY# AC2 PREQ# AC1 PROCHOT# D21 REQ[0]# K3 REQ[1]# H2 REQ[2]# K2 REQ[3]# J3 REQ[4]# L1 RESET# C1 RS[0]# F3 RS[1]# F4 RS[2]# G3 SMI# A3 STPCLK# D5 TCK AC5 TDI AA6 TDO AB3 THERMTRIP# C7 THERMDA A24 THERMDC B25 TMS AB5 TRDY# G2 TRST# AB6 A[32]# W3 A[33]# AA4 A[34]# AB2 A[35]# AA3 RSVD[10] F6 R415 0_0402_5%@ 1 2 JP3 ACES_85204-02001 CONN@ 1 1 2 2 G1 3 G2 4 E B C Q2 MMBT3904_SOT23 @ 2 3 1 5 5 4 4 3 3 2 2 1 1 D D C C B B A A V_CPU_GTLREF H_D#4 H_D#14 H_D#10 H_D#9 H_D#3 H_D#13 H_D#6 H_D#2 H_D#8 H_D#12 H_D#1 H_D#5 H_D#7 H_D#11 H_D#0 H_D#15 H_D#27 H_D#25 H_D#31 H_D#24 H_D#20 H_D#30 H_D#23 H_D#19 H_D#29 H_D#16 H_D#18 H_D#22 H_D#26 H_D#28 H_D#17 H_D#21 H_DINV#0 H_DINV#1 H_DINV#3 H_DINV#2 H_DSTBN#2 H_DSTBP#2 H_DSTBP#1 H_DSTBN#1 H_DSTBP#0 H_DSTBN#0 H_DSTBN#3 H_DSTBP#3 H_D#48 H_D#56 H_D#52 H_D#59 H_D#63 H_D#55 H_D#51 H_D#62 H_D#58 H_D#54 H_D#50 H_D#57 H_D#61 H_D#53 H_D#49 H_D#60 COMP0 COMP2 COMP3 COMP1 CPU_BSEL2 CPU_BSEL1 CPU_BSEL0 H_CPUSLP# H_DPSLP# H_DPRSTP# H_PSI# V_CPU_GTLREF TEST1 TEST2 VSSSENSE VCCSENSE H_DPWR# H_D#47 H_D#43 H_D#42 H_D#37 H_D#34 H_D#33 H_D#39 H_D#38 H_D#41 H_D#40 H_D#35 H_D#36 H_D#45 H_D#44 H_D#32 H_D#46 TEST3 TEST5 TEST6 TEST4 H_PWRGOOD VSSSENSE VCCSENSE VCCSENSE 37 VSSSENSE 37 H_D#[0 15]7 H_DSTBN#07 H_DSTBP#07 H_DINV#07 H_D#[16 31]7 H_DSTBN#17 H_DSTBP#17 H_DINV#17 CPU_BSEL015 CPU_BSEL115 CPU_BSEL215 H_D#[32 47] 7 H_DSTBN#2 7 H_DSTBP#2 7 H_DINV#2 7 H_D#[48 63] 7 H_DSTBN#3 7 H_DSTBP#3 7 H_DINV#3 7 H_DPRSTP# 7,19,37 H_DPSLP# 19 H_CPUSLP# 7 H_DPWR# 7 H_PWRGOOD 19 H_PSI# 37 CPU_VID0 37 CPU_VID1 37 CPU_VID2 37 CPU_VID3 37 CPU_VID4 37 CPU_VID5 37 CPU_VID6 37 +VCCP +VCCP +1.5VS +VCC_CORE +VCC_CORE +VCC_CORE Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date LA-3981P 0.3 Merom(2/3)-AGTL+/PWR Custom 542Monday, October 22, 2007 2007/03/26 2006/03/10 Compal Electronics, Inc. Close to CPU pin AD26 within 500mils. CPU_BSEL CPU_BSEL2 CPU_BSEL1 166 200 01 0 1 CPU_BSEL0 1 0 Resistor placed within 0.5" of CPU pin.Trace should be at least 25 mils away from any other toggling signal. COMP[0,2] trace width is 18 mils. COMP[1,3] trace width is 4 mils. Length match within 25 mils. The trace width/space/other is 20/7/25. Close to CPU pin within 500mils. Near pin B26 layout note: Route TEST3 & TEST5 traces on ground referenced layer to the TPs R20 1K_0402_5%@ 1 2 R19 0_0402_5% 12 R25 27.4_0402_1% 12 R21 1K_0402_5%@ 1 2 R18 0_0402_5% 12 R28 100_0402_1% 1 2 DATA GRP 0 DATA GRP 1 DATA GRP 2DATA GRP 3 MISC JP2B Merom Ball-out Rev 1a CONN@ COMP[0] R26 COMP[1] U26 COMP[2] AA1 COMP[3] Y1 D[0]# E22 D[1]# F24 D[10]# J24 D[11]# J23 D[12]# H22 D[13]# F26 D[14]# K22 D[15]# H23 D[16]# N22 D[17]# K25 D[18]# P26 D[19]# R23 D[2]# E26 D[20]# L23 D[21]# M24 D[22]# L22 D[23]# M23 D[24]# P25 D[25]# P23 D[26]# P22 D[27]# T24 D[28]# R24 D[29]# L25 D[3]# G22 D[30]# T25 D[31]# N25 D[32]# Y22 D[33]# AB24 D[34]# V24 D[35]# V26 D[36]# V23 D[37]# T22 D[38]# U25 D[39]# U23 D[4]# F23 D[40]# Y25 D[41]# W22 D[42]# Y23 D[43]# W24 D[44]# W25 D[45]# AA23 D[46]# AA24 D[47]# AB25 D[48]# AE24 D[49]# AD24 D[5]# G25 D[50]# AA21 D[51]# AB22 D[52]# AB21 D[53]# AC26 D[54]# AD20 D[55]# AE22 D[56]# AF23 D[57]# AC25 D[58]# AE21 D[59]# AD21 D[6]# E25 D[60]# AC22 D[61]# AD23 D[62]# AF22 D[63]# AC23 D[7]# E23 D[8]# K24 D[9]# G24 TEST5 AF1 DINV[0]# H25 DINV[1]# N24 DINV[2]# U22 DINV[3]# AC20 DPRSTP# E5 DPSLP# B5 DPWR# D24 DSTBN[0]# J26 DSTBN[1]# L26 DSTBN[2]# Y26 DSTBN[3]# AE25 DSTBP[0]# H26 DSTBP[1]# M26 DSTBP[2]# AA26 DSTBP[3]# AF24 GTLREF AD26 PSI# AE6 PWRGOOD D6 SLP# D7 TEST3 C24 BSEL[0] B22 BSEL[1] B23 BSEL[2] C21 TEST2 D25 TEST4 AF26 TEST6 A26 TEST1 C23 C9 10U_0805_6.3V6M 1 2 C10 0.01U_0402_16V7K 1 2 T3 R24 54.9_0402_1% 12 R29 2K_0402_1% 12 R27 1K_0402_1% 12 R22 54.9_0402_1% 12 JP2C Merom Ball-out Rev 1a . CONN@ VCC[001] A7 VCC[002] A9 VCC[003] A10 VCC[004] A12 VCC[005] A13 VCC[006] A15 VCC[007] A17 VCC[008] A18 VCC[009] A20 VCC[010] B7 VCC[011] B9 VCC[012] B10 VCC[013] B12 VCC[014] B14 VCC[015] B15 VCC[016] B17 VCC[017] B18 VCC[018] B20 VCC[019] C9 VCC[020] C10 VCC[021] C12 VCC[022] C13 VCC[023] C15 VCC[024] C17 VCC[025] C18 VCC[026] D9 VCC[027] D10 VCC[028] D12 VCC[029] D14 VCC[030] D15 VCC[031] D17 VCC[032] D18 VCC[033] E7 VCC[034] E9 VCC[035] E10 VCC[036] E12 VCC[037] E13 VCC[038] E15 VCC[039] E17 VCC[040] E18 VCC[041] E20 VCC[042] F7 VCC[043] F9 VCC[044] F10 VCC[045] F12 VCC[046] F14 VCC[047] F15 VCC[048] F17 VCC[049] F18 VCC[050] F20 VCC[051] AA7 VCC[052] AA9 VCC[053] AA10 VCC[054] AA12 VCC[055] AA13 VCC[056] AA15 VCC[057] AA17 VCC[058] AA18 VCC[059] AA20 VCC[060] AB9 VCC[061] AC10 VCC[062] AB10 VCC[063] AB12 VCC[064] AB14 VCC[065] AB15 VCC[066] AB17 VCC[067] AB18 VCC[068] AB20 VCC[069] AB7 VCC[070] AC7 VCC[071] AC9 VCC[072] AC12 VCC[073] AC13 VCC[074] AC15 VCC[075] AC17 VCC[076] AC18 VCC[077] AD7 VCC[078] AD9 VCC[079] AD10 VCC[080] AD12 VCC[081] AD14 VCC[082] AD15 VCC[083] AD17 VCC[084] AD18 VCC[085] AE9 VCC[086] AE10 VCC[087] AE12 VCC[088] AE13 VCC[089] AE15 VCC[090] AE17 VCC[091] AE18 VCC[092] AE20 VCC[093] AF9 VCC[094] AF10 VCC[095] AF12 VCC[096] AF14 VCC[097] AF15 VCC[098] AF17 VCC[099] AF18 VCC[100] AF20 VCCA[01] B26 VCCP[03] J6 VCCP[04] K6 VCCP[05] M6 VCCP[06] J21 VCCP[07] K21 VCCP[08] M21 VCCP[09] N21 VCCP[10] N6 VCCP[11] R21 VCCP[12] R6 VCCP[13] T21 VCCP[14] T6 VCCP[15] V21 VCCP[16] W21 VCCSENSE AF7 VID[0] AD6 VID[1] AF5 VID[2] AE5 VID[3] AF4 VID[4] AE3 VID[5] AF3 VID[6] AE2 VSSSENSE AE7 VCCA[02] C26 VCCP[01] G21 VCCP[02] V6 + C7 220U_6.3V_M 1 2 T2 R23 27.4_0402_1% 12 T1 R30 100_0402_1% 1 2 C8 0.1U_0402_16V4Z@ 1 2 5 5 4 4 3 3 2 2 1 1 D D C C B B A A +VCC_CORE +VCC_CORE +VCC_CORE +VCC_CORE +VCC_CORE +VCCP Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date LA-3981P 0.3 Merom(3/3)-GND&Bypass Custom 642Monday, October 22, 2007 2007/03/26 2006/03/10 Compal Electronics, Inc. Place these inside socket cavity on L8 (North side Secondary) ESR <= 1.5m ohm Capacitor > 1980uF Near CPU CORE regulator Mid Frequence Decoupling Place these capacitors on L8 (Sorth side,Secondary Layer) Place these capacitors on L8 (North side,Secondary Layer) Place these capacitors on L8 (Sorth side,Secondary Layer) Place these capacitors on L8 (North side,Secondary Layer) C20 10U_0805_6.3V6M 1 2 C55 0.1U_0402_16V4Z 1 2 C31 10U_0805_6.3V6M 1 2 C29 10U_0805_6.3V6M 1 2 C17 10U_0805_6.3V6M 1 2 C14 10U_0805_6.3V6M 1 2 C21 10U_0805_6.3V6M 1 2 C52 0.1U_0402_16V4Z 1 2 C53 0.1U_0402_16V4Z 1 2 JP2D Merom Ball-out Rev 1a . CONN@ VSS[082] P6 VSS[148] AE11 VSS[002] A8 VSS[003] A11 VSS[004] A14 VSS[005] A16 VSS[006] A19 VSS[007] A23 VSS[008] AF2 VSS[009] B6 VSS[010] B8 VSS[011] B11 VSS[012] B13 VSS[013] B16 VSS[014] B19 VSS[015] B21 VSS[016] B24 VSS[017] C5 VSS[018] C8 VSS[019] C11 VSS[020] C14 VSS[021] C16 VSS[022] C19 VSS[023] C2 VSS[024] C22 VSS[025] C25 VSS[026] D1 VSS[027] D4 VSS[028] D8 VSS[029] D11 VSS[030] D13 VSS[031] D16 VSS[032] D19 VSS[033] D23 VSS[034] D26 VSS[035] E3 VSS[036] E6 VSS[037] E8 VSS[038] E11 VSS[039] E14 VSS[040] E16 VSS[041] E19 VSS[042] E21 VSS[043] E24 VSS[044] F5 VSS[045] F8 VSS[046] F11 VSS[047] F13 VSS[048] F16 VSS[049] F19 VSS[050] F2 VSS[051] F22 VSS[052] F25 VSS[053] G4 VSS[054] G1 VSS[055] G23 VSS[056] G26 VSS[057] H3 VSS[058] H6 VSS[059] H21 VSS[060] H24 VSS[061] J2 VSS[062] J5 VSS[063] J22 VSS[064] J25 VSS[065] K1 VSS[066] K4 VSS[067] K23 VSS[068] K26 VSS[069] L3 VSS[070] L6 VSS[071] L21 VSS[072] L24 VSS[073] M2 VSS[074] M5 VSS[075] M22 VSS[076] M25 VSS[077] N1 VSS[078] N4 VSS[079] N23 VSS[080] N26 VSS[081] P3 VSS[162] A25 VSS[161] AF21 VSS[160] AF19 VSS[159] AF16 VSS[158] AF13 VSS[157] AF11 VSS[156] AF8 VSS[155] AF6 VSS[154] A2 VSS[153] AE26 VSS[152] AE23 VSS[151] AE19 VSS[083] P21 VSS[084] P24 VSS[085] R2 VSS[086] R5 VSS[087] R22 VSS[088] R25 VSS[089] T1 VSS[090] T4 VSS[091] T23 VSS[092] T26 VSS[093] U3 VSS[094] U6 VSS[095] U21 VSS[096] U24 VSS[097] V2 VSS[098] V5 VSS[099] V22 VSS[100] V25 VSS[101] W1 VSS[102] W4 VSS[103] W23 VSS[104] W26 VSS[105] Y3 VSS[107] Y21 VSS[108] Y24 VSS[109] AA2 VSS[110] AA5 VSS[111] AA8 VSS[112] AA11 VSS[113] AA14 VSS[114] AA16 VSS[115] AA19 VSS[116] AA22 VSS[117] AA25 VSS[118] AB1 VSS[119] AB4 VSS[120] AB8 VSS[121] AB11 VSS[122] AB13 VSS[123] AB16 VSS[124] AB19 VSS[125] AB23 VSS[126] AB26 VSS[127] AC3 VSS[128] AC6 VSS[129] AC8 VSS[130] AC11 VSS[131] AC14 VSS[132] AC16 VSS[133] AC19 VSS[134] AC21 VSS[135] AC24 VSS[136] AD2 VSS[137] AD5 VSS[138] AD8 VSS[139] AD11 VSS[140] AD13 VSS[141] AD16 VSS[142] AD19 VSS[143] AD22 VSS[144] AD25 VSS[145] AE1 VSS[146] AE4 VSS[106] Y6 VSS[001] A4 VSS[149] AE14 VSS[150] AE16 VSS[147] AE8 VSS[163] AF25 C15 10U_0805_6.3V6M 1 2 C13 10U_0805_6.3V6M 1 2 C16 10U_0805_6.3V6M 1 2 C30 10U_0805_6.3V6M 1 2 C40 10U_0805_6.3V6M 1 2 C26 10U_0805_6.3V6M 1 2 C39 10U_0805_6.3V6M 1 2 C27 10U_0805_6.3V6M 1 2 C18 10U_0805_6.3V6M 1 2 C22 10U_0805_6.3V6M 1 2 C42 10U_0805_6.3V6M 1 2 C33 10U_0805_6.3V6M 1 2 C51 0.1U_0402_16V4Z 1 2 C38 10U_0805_6.3V6M 1 2 C25 10U_0805_6.3V6M 1 2 C32 10U_0805_6.3V6M 1 2 C37 10U_0805_6.3V6M 1 2 C24 10U_0805_6.3V6M 1 2 C41 10U_0805_6.3V6M 1 2 C36 10U_0805_6.3V6M 1 2 + C48 220U_D2_2V_Y_LESR9M 1 2 + C49 1000U 2.5V M H80 LESR8M @ 1 2 C35 10U_0805_6.3V6M 1 2 + C47 220U_D2_2V_Y_LESR9M 1 2 C11 10U_0805_6.3V6M 1 2 C12 10U_0805_6.3V6M 1 2 C23 10U_0805_6.3V6M 1 2 C34 10U_0805_6.3V6M 1 2 C50 0.1U_0402_16V4Z 1 2 + C45 220U_D2_2V_Y_LESR9M 1 2 + C46 220U_D2_2V_Y_LESR9M 1 2 C54 0.1U_0402_16V4Z 1 2 C19 10U_0805_6.3V6M 1 2 C28 10U_0805_6.3V6M 1 2 5 5 4 4 3 3 2 2 1 1 D D C C B B A A H_SWNGH_VREF PM_EXTTS#0 PM_EXTTS#1 DDR_CKE0_DIMMA DDR_CKE1_DIMMA DDR_CKE3_DIMMB DDR_CS1_DIMMA# DDR_CKE2_DIMMB DDR_CS0_DIMMA# DDR_CS3_DIMMB# DDR_CS2_DIMMB# CLK_MCH_3GPLL# CLK_MCH_3GPLL M_CLK_DDR3 M_CLK_DDR#0 M_CLK_DDR#1 M_CLK_DDR#2 M_CLK_DDR#3 M_CLK_DDR2 M_CLK_DDR0 M_CLK_DDR1 SMRCOMP_VOH SMRCOMP_VOL M_ODT1 SMRCOMP# M_ODT3 M_ODT0 M_ODT2 SMRCOMP V_DDR_MCH_REF SMRCOMP_VOL SMRCOMP_VOH MCH_SSCDREFCLK MCH_SSCDREFCLK# CLK_MCH_DREFCLK CLK_MCH_DREFCLK# CFG10 CFG11 CFG7 CFG5 CFG13 CFG9 CFG16 CFG19 CFG12 CFG6 CFG20 MCH_CLKSEL0 MCH_CLKSEL1 MCH_CLKSEL2 MCH_ICH_SYNC# CLKREQ#_B H_DPRSTP# DPRSLPVR PM_EXTTS#1 PM_BMBUSY# H_THERMTRIP# PM_EXTTS#0 CL_CLK0 CL_DATA0 CL_RST# V_DDR_MCH_REF H_SCOMP# H_DSTBP#0 H_DSTBN#1 H_D#39 H_D#37 H_D#34 H_D#22 H_D#12 H_D#11 H_ADSTB#0 H_A#24 H_A#10 H_RS#0 H_DSTBN#0H_D#58 H_D#54 H_D#4 H_D#13 H_D#20 H_ADSTB#1 H_A#7 H_A#3 H_A#11 H_DSTBP#2 H_D#6 H_D#25 H_D#1 H_A#16 H_REQ#0 H_D#44 H_A#19 H_A#17 H_RCOMP H_A#35 H_DSTBP#1 H_D#43 H_D#35 H_REQ#3 H_BNR# H_A#13 H_CPUSLP# H_SWNG H_HITM# H_DSTBN#3 H_DINV#1 H_D#62 H_D#57 H_D#56 H_D#60 H_A#14 H_RCOMP H_VREF H_HIT# H_D#38 H_D#17 H_A#31 H_DPWR# H_D#32 H_D#50 H_D#10 H_A#20 H_A#12 H_A#33 H_DSTBP#3 H_DINV#3 H_D#59 H_D#5 H_D#33 H_REQ#4 H_DEFER# H_D#55 H_D#47 H_D#45 H_D#28 H_D#27 H_D#19 H_D#16 CLK_MCH_BCLK# H_A#9 H_A#6 H_D#49 H_D#15 H_D#40 H_REQ#2 H_D#0 H_BR0# H_A#27 H_A#22 H_A#15 H_A#34 H_A#32 H_REQ#1 H_LOCK# H_DRDY# H_DINV#0 H_D#61 H_D#26 H_D#23 H_A#8 H_A#25 H_RS#2 H_D#7 H_D#14 H_D#8 H_D#30 CLK_MCH_BCLK H_A#28 H_RS#1 H_TRDY# H_DSTBN#2 H_D#63 H_D#52 H_D#48 H_D#36 H_D#31 H_D#29 H_A#4 H_A#30 H_A#29 H_DINV#2 H_D#41 H_D#24 H_D#21 H_D#18 H_D#9 H_BPRI# H_ADS# H_A#5 H_A#23 H_D#53 H_D#46 H_D#42 H_DBSY# H_A#21 H_A#18 H_SCOMP H_D#51 H_D#3 H_D#2 H_A#26 H_RESET# CLKREQ#_B DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3 DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3 DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3 DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3 CL_VREF CL_VREF M_PWROK CFG8 PLT_RST# PM_PWROK CFG18 V_DDR_MCH_REF13,14,35 H_D#[0 63]5 H_CPUSLP#5 H_DINV#0 5 H_DINV#1 5 H_DINV#2 5 H_DINV#3 5 H_DSTBN#0 5 H_DSTBN#1 5 H_DSTBN#2 5 H_DSTBN#3 5 H_DSTBP#0 5 H_DSTBP#1 5 H_DSTBP#2 5 H_DSTBP#3 5 DDR_CKE0_DIMMA 13 DDR_CKE1_DIMMA 13 DDR_CKE2_DIMMB 14 DDR_CKE3_DIMMB 14 DDR_CS0_DIMMA# 13 DDR_CS1_DIMMA# 13 DDR_CS2_DIMMB# 14 DDR_CS3_DIMMB# 14 CLK_MCH_3GPLL 15 CLK_MCH_3GPLL# 15 H_A#[3 35] 4 H_ADS# 4 H_ADSTB#1 4 H_ADSTB#0 4 H_BPRI# 4 H_BNR# 4 H_DEFER# 4 H_BR0# 4 H_DBSY# 4 CLK_MCH_BCLK 15 CLK_MCH_BCLK# 15 H_DPWR# 5 H_DRDY# 4 H_HIT# 4 H_HITM# 4 H_LOCK# 4 H_TRDY# 4 M_CLK_DDR0 13 M_CLK_DDR1 13 M_CLK_DDR2 14 M_CLK_DDR3 14 M_CLK_DDR#0 13 M_CLK_DDR#1 13 M_CLK_DDR#2 14 M_CLK_DDR#3 14 M_ODT0 13 M_ODT1 13 M_ODT2 14 M_ODT3 14 MCH_SSCDREFCLK 15 MCH_SSCDREFCLK# 15 MCH_CLKSEL015 MCH_CLKSEL115 MCH_CLKSEL215 DMI_TXP0 20 DMI_RXN0 20 DMI_RXP0 20 DMI_TXN0 20 CLKREQ#_B 15 MCH_ICH_SYNC# 20 PM_BMBUSY#20 DPRSLPVR20,37 H_DPRSTP#5,19,37 PM_EXTTS#013 CL_CLK0 20 CL_DATA0 20 CL_RST# 20 M_PWROK 20,30 H_RS#2 4 H_REQ#3 4 H_RS#1 4 H_RESET#4 H_REQ#2 4 H_RS#0 4 H_REQ#1 4 H_REQ#4 4 H_REQ#0 4 DMI_TXN1 20 DMI_TXN2 20 DMI_TXN3 20 DMI_TXP1 20 DMI_TXP2 20 DMI_TXP3 20 DMI_RXN1 20 DMI_RXN2 20 DMI_RXN3 20 DMI_RXP1 20 DMI_RXP2 20 DMI_RXP3 20 PM_EXTTS#114 CLK_MCH_DREFCLK 15 CLK_MCH_DREFCLK# 15 H_THERMTRIP#4,19 DDR_A_MA1413 DDR_B_MA1414 PLT_RST#18,22 PM_PWROK20,30 +VCCP +VCCP +VCCP +3VS +1.8V +1.8V +1.8V +1.25VM_AXD Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date LA-3981P 0.3 CRESTLINE(1/6)-AGTL+/DMI/DDR2 Custom 742Monday, October 22, 2007 2007/03/26 2006/03/10 Compal Electronics, Inc. Layout Note: H_RCOMP / H_VREF / H_SWNG trace width and spacing is 10/20 Layout Note: V_DDR_MCH_REF trace width and spacing is 20/20. NA lead free Near B3 pinwithin 100 mils from NB layout note: Route H_SCOMP and H_SCOMP# with trace width, spacing and impedance (55 ohm) same as FSB data traces For Calero: 80.6ohm For Crestline: 20ohm 0925_Stuff R43 and R46. 0927_Change from 20 ohm to 30 ohm. R51 100_0402_1% 12 R49 2K_0402_1% 12 T19 T10 C60 0.1U_0402_16V4Z 1 2 T11 C57 0.01U_0402_16V7K 1 2 T14 T9 R48 0_0402_5% 12 R44 1K_0402_1% 12 R34 30_0402_1% 12 T4 R35 30_0402_1% 12 R46 1K_0402_1% 12 R40 54.9_0402_1% 12 R39 54.9_0402_1% 12 T12 R36 10K_0402_5% 12 T44 C61 0.1U_0402_16V4Z 1 2 R31 1K_0402_1% 12 C59 0.01U_0402_16V7K 1 2 R37 10K_0402_5% <> 12 T18 HOST U3A CRESTLINE_1p0 H_A#_10 G17 H_A#_11 C14 H_A#_12 K16 H_A#_13 B13 H_A#_14 L16 H_A#_15 J17 H_A#_16 B14 H_A#_17 K19 H_A#_18 P15 H_A#_19 R17 H_A#_20 B16 H_A#_21 H20 H_A#_22 L19 H_A#_23 D17 H_A#_24 M17 H_A#_25 N16 H_A#_26 J19 H_A#_27 B18 H_A#_28 E19 H_A#_29 B17 H_A#_3 J13 H_A#_30 B15 H_A#_31 E17 H_A#_4 B11 H_A#_5 C11 H_A#_6 M11 H_A#_7 C15 H_A#_8 F16 H_A#_9 L13 H_ADS# G12 H_ADSTB#_0 H17 H_ADSTB#_1 G20 H_BNR# C8 H_BPRI# E8 H_BREQ# F12 HPLL_CLK# AM7 H_CPURST# B6 HPLL_CLK AM5 H_D#_0 E2 H_REQ#_2 A11 H_REQ#_3 H13 H_D#_1 G2 H_D#_10 M10 H_D#_20 M3 H_D#_30 W3 H_D#_40 AB2 H_D#_50 AJ14 H_D#_60 AE5 H_D#_8 N8 H_D#_9 H2 H_DBSY# C10 H_D#_11 N12 H_D#_12 N9 H_D#_13 H5 H_D#_14 P13 H_D#_15 K9 H_D#_16 M2 H_D#_17 W10 H_D#_18 Y8 H_D#_19 V4 H_D#_2 G7 H_D#_21 J1 H_D#_22 N5 H_D#_23 N3 H_D#_24 W6 H_D#_25 W9 H_D#_26 N2 H_D#_27 Y7 H_D#_28 Y9 H_D#_29 P4 H_D#_3 M6 H_D#_31 N1 H_D#_32 AD12 H_D#_33 AE3 H_D#_34 AD9 H_D#_35 AC9 H_D#_36 AC7 H_D#_37 AC14 H_D#_38 AD11 H_D#_39 AC11 H_D#_4 H7 H_D#_41 AD7 H_D#_42 AB1 H_D#_43 Y3 H_D#_44 AC6 H_D#_45 AE2 H_D#_46 AC5 H_D#_47 AG3 H_D#_48 AJ9 H_D#_49 AH8 H_D#_5 H3 H_D#_51 AE9 H_D#_52 AE11 H_D#_53 AH12 H_D#_54 AJ5 H_D#_55 AH5 H_D#_56 AJ6 H_D#_57 AE7 H_D#_58 AJ7 H_D#_59 AJ2 H_D#_6 G4 H_D#_61 AJ3 H_D#_62 AH2 H_D#_63 AH13 H_D#_7 F3 H_DEFER# D6 H_DINV#_0 K5 H_DINV#_1 L2 H_DINV#_2 AD13 H_DINV#_3 AE13 H_DPWR# H8 H_DRDY# K7 H_DSTBN#_0 M7 H_DSTBN#_1 K3 H_DSTBN#_2 AD2 H_DSTBN#_3 AH11 H_DSTBP#_0 L7 H_DSTBP#_1 K2 H_DSTBP#_2 AC2 H_DSTBP#_3 AJ10 H_SCOMP W1 H_AVREF B9 H_DVREF A9 H_TRDY# B7 H_HIT# E4 H_HITM# C6 H_LOCK# G10 H_REQ#_0 M14 H_REQ#_1 E13 H_REQ#_4 B12 H_A#_32 C18 H_A#_33 A19 H_A#_34 B19 H_A#_35 N19 H_SWING B3 H_CPUSLP# E5 H_RCOMP C2 H_RS#_0 E12 H_RS#_1 D7 H_RS#_2 D8 H_SCOMP# W2 R47 20K_0402_5% 12 T7 R41 1K_0402_1% 12 T20 C58 2.2U_0805_16V4Z 1 2 T6 C62 0.1U_0402_16V4Z 1 2 R50 24.9_0402_1% 12 R38 10K_0402_5% 12 C63 0.1U_0402_16V4Z 1 2 R42 392_0402_1% 12 T5 R45 221_0603_1% 12 T17 T16 T8 T15 R43 1K_0402_1% 12 R32 3.01K_0402_1% 12 T13 PM MISC NC DDR MUXINGCLK DMI CFGRSVD GRAPHICS VID ME U3B CRESTLINE_1p0 SM_CK_0 AV29 SM_CK_1 BB23 RSVD28 BF23 SM_CK_3 BA25 SM_CK#_0 AW30 SM_CK#_1 BA23 RSVD29 BG23 SM_CK#_3 AW25 SM_CKE_0 BE29 SM_CKE_1 AY32 SM_CKE_3 BD39 SM_CKE_4 BG37 SM_CS#_0 BG20 SM_CS#_1 BK16 SM_CS#_2 BG16 SM_CS#_3 BE13 RSVD34 BH39 SM_ODT_0 BH18 SM_ODT_1 BJ15 SM_ODT_2 BJ14 SM_ODT_3 BE16 SM_RCOMP BL15 SM_RCOMP# BK14 SM_VREF_0 AR49 SM_VREF_1 AW4 CFG_18 L32 CFG_19 N33 CFG_2 N24 CFG_0 P27 CFG_1 N27 CFG_20 L35 CFG_3 C21 CFG_4 C23 CFG_5 F23 CFG_6 N23 CFG_7 G23 CFG_8 J20 CFG_9 C20 CFG_10 R24 CFG_11 L23 CFG_12 J23 CFG_13 E23 CFG_14 E20 CFG_15 K23 CFG_16 M20 CFG_17 M24 PM_BM_BUSY# G41 PM_EXT_TS#_0 L36 PM_EXT_TS#_1 J36 PWROK AW49 RSTIN# AV20 DPLL_REF_CLK B42 DPLL_REF_CLK# C42 DPLL_REF_SSCLK H48 DPLL_REF_SSCLK# H47 DMI_RXN_0 AN47 DMI_RXN_1 AJ38 DMI_RXN_2 AN42 DMI_RXN_3 AN46 DMI_RXP_0 AM47 DMI_RXP_1 AJ39 DMI_RXP_2 AN41 DMI_RXP_3 AN45 DMI_TXN_0 AJ46 DMI_TXN_1 AJ41 DMI_TXN_2 AM40 DMI_TXN_3 AM44 DMI_TXP_0 AJ47 DMI_TXP_1 AJ42 DMI_TXP_2 AM39 DMI_TXP_3 AM43 RSVD10 AR37 RSVD12 AL36 RSVD11 AM36 RSVD13 AM37 RSVD22 BJ20 RSVD23 BK22 RSVD24 BF19 RSVD25 BH20 RSVD26 BK18 PM_DPRSTP# L39 SM_CK_4 AV23 SM_CK#_4 AW23 RSVD30 BC23 RSVD31 BD24 RSVD35 AW20 RSVD36 BK20 RSVD5 AR12 RSVD6 AR13 RSVD7 AM12 RSVD8 AN13 RSVD1 P36 RSVD2 P37 RSVD3 R35 RSVD4 N35 GFX_VID_0 E35 GFX_VID_1 A39 GFX_VID_2 C38 GFX_VID_3 B39 GFX_VR_EN E36 RSVD27 BJ18 SM_RCOMP_VOH BK31 SM_RCOMP_VOL BL31 THERMTRIP# N20 DPRSLPVR G36 RSVD9 J12 CL_CLK AM49 CL_DATA AK50 CL_PWROK AT43 CL_RST# AN49 CL_VREF AM50 RSVD37 C48 RSVD38 D47 RSVD39 B44 RSVD40 C44 RSVD32 BJ29 RSVD33 BE24 RSVD21 B51 NC_1 BJ51 NC_2 BK51 NC_3 BK50 NC_4 BL50 NC_5 BL49 NC_6 BL3 NC_7 BL2 NC_8 BK1 NC_9 BJ1 NC_10 E1 NC_11 A5 NC_12 C51 NC_13 B50 NC_14 A50 NC_15 A49 SDVO_CTRL_CLK H35 SDVO_CTRL_DATA K36 CLK_REQ# G39 RSVD14 D20 ICH_SYNC# G40 RSVD20 H10 RSVD41 A35 RSVD42 B37 RSVD43 B36 RSVD44 B34 RSVD45 C34 PEG_CLK# K45 PEG_CLK K44 TEST_1 A37 NC_16 BK2 TEST_2 R32 C56 2.2U_0805_16V4Z 1 2 R33 1K_0402_1% 12 5 5 4 4 3 3 2 2 1 1 D D C C B B A A DDR_B_DQS#6 DDR_B_D63 DDR_B_D48 DDR_A_MA8 DDR_A_MA5 DDR_A_DQS#1 DDR_A_CAS# DDR_A_BS0 DDR_A_D6 DDR_A_D52 DDR_A_D35 DDR_A_D27 DDR_A_D26 DDR_A_D16 DDR_B_DQS0 DDR_B_DM5 DDR_B_D60 DDR_B_D53 DDR_B_D20 DDR_B_D17 DDR_B_D11 DDR_B_D10 DDR_A_MA12 DDR_A_DQS#5 DDR_A_DM7 DDR_A_D55 DDR_A_D5 DDR_A_D45 DDR_A_D29 DDR_A_D1 DDR_B_DQS7 DDR_B_CAS# DDR_B_D62 DDR_B_D19 DDR_A_MA13 DDR_A_DQS5 DDR_A_DM6 DDR_A_BS1 DDR_A_D48 DDR_A_D44 DDR_A_D20 DDR_A_D14 DDR_B_MA5 DDR_B_DQS#0 DDR_B_BS0 DDR_B_D50 DDR_B_D41 DDR_B_D23 DDR_A_D47 DDR_A_D39 DDR_A_D31 DDR_B_WE# DDR_B_MA1 DDR_B_DM2 DDR_B_DM0 DDR_B_D33 DDR_B_D24 DDR_A_MA4 DDR_A_DQS7 DDR_A_D40 DDR_A_D38 DDR_A_D37 DDR_A_D2 DDR_B_MA7 DDR_B_MA13 DDR_B_D55 DDR_B_D32 DDR_B_D29 DDR_B_D28 DDR_B_D21 DDR_A_MA11 DDR_A_DQS#4 DDR_A_DQS#0 DDR_A_DM5 DDR_A_BS2 DDR_A_D63 DDR_A_D50 DDR_A_D19 DDR_A_D17 DDR_B_D8 DDR_B_D61 DDR_A_DQS4 DDR_A_DM4 DDR_A_D62 DDR_A_D54 DDR_A_D36 DDR_A_D11 DDR_B_DQS#5 DDR_B_DQS#3 DDR_B_DQS4 DDR_B_BS2 DDR_B_D54 DDR_B_D52 DDR_B_D25 DDR_A_MA6 DDR_A_MA2 DDR_A_D9 DDR_A_D4 SB_RCVEN# DDR_B_MA8 DDR_B_DQS6 DDR_B_DQS5 DDR_B_DM4 DDR_B_DM3 DDR_B_D5 DDR_B_D34 DDR_B_D14 DDR_B_D0 DDR_A_MA3 DDR_A_MA0 DDR_A_D34 DDR_A_D18 DDR_B_MA2 DDR_B_MA10DDR_B_D42 DDR_B_D39 DDR_B_D38 DDR_B_D36 DDR_A_RAS# DDR_A_MA10 DDR_A_DQS#3 DDR_A_D60 DDR_A_D46 DDR_A_D42 DDR_A_D28 DDR_B_MA4 DDR_B_D7 DDR_B_D6 DDR_B_D46 DDR_B_D30 DDR_B_D18DDR_A_DQS3 DDR_A_DQS0 DDR_A_DM0 DDR_A_D59 DDR_A_D58 DDR_A_D15 DDR_B_DM6 DDR_B_D57 DDR_B_D4 DDR_B_D35 DDR_B_D27 DDR_B_D2 DDR_B_D1 DDR_A_MA1 DDR_A_D43 DDR_A_D41 DDR_A_D24 DDR_B_MA9 DDR_B_MA12 DDR_B_MA11 DDR_B_DQS3 DDR_B_DQS2 DDR_B_DM1 DDR_B_D56 DDR_B_D37 DDR_B_D16 DDR_B_D12 DDR_A_WE# DDR_A_DQS1 DDR_A_D51 DDR_A_D22 DDR_A_D12 DDR_A_D0 DDR_B_DQS#2 DDR_B_DQS#1 DDR_B_D59 DDR_B_D51 DDR_B_D47 DDR_A_MA9 DDR_A_DQS#2 DDR_A_DQS2 DDR_A_D7 DDR_A_D61 DDR_A_D56 DDR_A_D32 DDR_A_D30 DDR_A_D21 DDR_B_RAS# DDR_B_BS1 DDR_B_D9 DDR_B_D45 DDR_B_D43 DDR_B_D40 DDR_B_D15 DDR_A_DQS#6 DDR_A_DM2 DDR_A_D53 DDR_A_D49 DDR_A_D10 DDR_B_MA0 DDR_B_DQS#7 DDR_B_D58 DDR_B_D44 DDR_B_D3 DDR_B_D13 DDR_A_MA7 DDR_A_DQS#7 DDR_A_DQS6 DDR_A_DM3 DDR_A_DM1 DDR_A_D8 DDR_A_D57 DDR_B_MA6 DDR_B_MA3 DDR_B_DQS#4 DDR_B_DQS1 DDR_B_DM7 DDR_B_D49 DDR_B_D31 DDR_B_D26 DDR_B_D22 SA_RCVEN# DDR_A_D33 DDR_A_D3 DDR_A_D25 DDR_A_D23 DDR_A_D13 DDR_A_BS0 13 DDR_A_BS1 13 DDR_A_BS2 13 DDR_A_DQS[0 7] 13 DDR_A_DQS#[0 7] 13 DDR_A_MA[0 13] 13 DDR_A_RAS# 13 DDR_A_D[0 63]13 DDR_B_BS0 14 DDR_B_BS1 14 DDR_B_BS2 14 DDR_B_DM[0 7] 14 DDR_B_DQS[0 7] 14 DDR_B_DQS#[0 7] 14 DDR_B_MA[0 13] 14 DDR_B_RAS# 14 DDR_B_D[0 63]14 DDR_A_DM[0 7] 13 DDR_A_CAS# 13 DDR_B_CAS# 14 DDR_A_WE# 13 DDR_B_WE# 14 Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date LA-3981P 0.3 CRESTLINE((2/6)-DDR2 A/B CH Custom 842Monday, October 22, 2007 2007/03/26 2006/03/10 Compal Electronics, Inc. DDR SYSTEM MEMORY B U3E CRESTLINE_1p0 SB_DQ_0 AP49 SB_DQ_1 AR51 SB_DQ_10 BA49 SB_DQ_11 BE50 SB_DQ_12 BA51 SB_DQ_13 AY49 SB_DQ_14 BF50 SB_DQ_15 BF49 SB_DQ_16 BJ50 SB_DQ_17 BJ44 SB_DQ_18 BJ43 SB_DQ_19 BL43 SB_DQ_2 AW50 SB_DQ_20 BK47 SB_DQ_21 BK49 SB_DQ_22 BK43 SB_DQ_23 BK42 SB_DQ_24 BJ41 SB_DQ_25 BL41 SB_DQ_26 BJ37 SB_DQ_27 BJ36 SB_DQ_28 BK41 SB_DQ_29 BJ40 SB_DQ_3 AW51 SB_DQ_30 BL35 SB_DQ_31 BK37 SB_DQ_32 BK13 SB_DQ_33 BE11 SB_DQ_34 BK11 SB_DQ_35 BC11 SB_DQ_36 BC13 SB_DQ_37 BE12 SB_DQ_38 BC12 SB_DQ_39 BG12 SB_DQ_4 AN51 SB_DQ_40 BJ10 SB_DQ_41 BL9 SB_DQ_42 BK5 SB_DQ_43 BL5 SB_DQ_44 BK9 SB_DQ_45 BK10 SB_DQ_46 BJ8 SB_DQ_47 BJ6 SB_DQ_48 BF4 SB_DQ_49 BH5 SB_DQ_5 AN50 SB_DQ_50 BG1 SB_DQ_51 BC2 SB_DQ_52 BK3 SB_DQ_53 BE4 SB_DQ_54 BD3 SB_DQ_55 BJ2 SB_DQ_56 BA3 SB_DQ_57 BB3 SB_DQ_58 AR1 SB_DQ_59 AT3 SB_DQ_6 AV50 SB_DQ_60 AY2 SB_DQ_61 AY3 SB_DQ_62 AU2 SB_DQ_63 AT2 SB_DQ_7 AV49 SB_DQ_8 BA50 SB_DQ_9 BB50 SB_BS_0 AY17 SB_BS_1 BG18 SB_BS_2 BG36 SB_CAS# BE17 SB_DM_0 AR50 SB_DM_1 BD49 SB_DM_2 BK45 SB_DM_3 BL39 SB_DM_4 BH12 SB_DM_5 BJ7 SB_DM_6 BF3 SB_DM_7 AW2 SB_DQS_0 AT50 SB_DQS_1 BD50 SB_DQS_2 BK46 SB_DQS_3 BK39 SB_DQS_4 BJ12 SB_DQS_5 BL7 SB_DQS_6 BE2 SB_DQS_7 AV2 SB_DQS#_0 AU50 SB_DQS#_1 BC50 SB_DQS#_2 BL45 SB_DQS#_3 BK38 SB_DQS#_4 BK12 SB_DQS#_5 BK7 SB_DQS#_6 BF2 SB_DQS#_7 AV3 SB_MA_0 BC18 SB_MA_1 BG28 SB_MA_10 BG17 SB_MA_11 BE37 SB_MA_12 BA39 SB_MA_13 BG13 SB_MA_2 BG25 SB_MA_3 AW17 SB_MA_4 BF25 SB_MA_5 BE25 SB_MA_6 BA29 SB_MA_7 BC28 SB_MA_8 AY28 SB_MA_9 BD37 SB_RAS# AV16 SB_RCVEN# AY18 SB_WE# BC17 DDR SYSTEM MEMORY A U3D CRESTLINE_1p0 SA_DQ_0 AR43 SA_DQ_1 AW44 SA_DQ_10 BG47 SA_DQ_11 BJ45 SA_DQ_12 BB47 SA_DQ_13 BG50 SA_DQ_14 BH49 SA_DQ_15 BE45 SA_DQ_16 AW43 SA_DQ_17 BE44 SA_DQ_18 BG42 SA_DQ_19 BE40 SA_DQ_2 BA45 SA_DQ_20 BF44 SA_DQ_21 BH45 SA_DQ_22 BG40 SA_DQ_23 BF40 SA_DQ_24 AR40 SA_DQ_25 AW40 SA_DQ_26 AT39 SA_DQ_27 AW36 SA_DQ_28 AW41 SA_DQ_29 AY41 SA_DQ_3 AY46 SA_DQ_30 AV38 SA_DQ_31 AT38 SA_DQ_32 AV13 SA_DQ_33 AT13 SA_DQ_34 AW11 SA_DQ_35 AV11 SA_DQ_36 AU15 SA_DQ_37 AT11 SA_DQ_38 BA13 SA_DQ_39 BA11 SA_DQ_4 AR41 SA_DQ_40 BE10 SA_DQ_41 BD10 SA_DQ_42 BD8 SA_DQ_43 AY9 SA_DQ_44 BG10 SA_DQ_45 AW9 SA_DQ_46 BD7 SA_DQ_47 BB9 SA_DQ_48 BB5 SA_DQ_49 AY7 SA_DQ_5 AR45 SA_DQ_50 AT5 SA_DQ_51 AT7 SA_DQ_52 AY6 SA_DQ_53 BB7 SA_DQ_54 AR5 SA_DQ_55 AR8 SA_DQ_56 AR9 SA_DQ_57 AN3 SA_DQ_58 AM8 SA_DQ_59 AN10 SA_DQ_6 AT42 SA_DQ_60 AT9 SA_DQ_61 AN9 SA_DQ_62 AM9 SA_DQ_63 AN11 SA_DQ_7 AW47 SA_DQ_8 BB45 SA_DQ_9 BF48 SA_BS_0 BB19 SA_BS_1 BK19 SA_BS_2 BF29 SA_CAS# BL17 SA_DM_0 AT45 SA_DM_1 BD44 SA_DM_2 BD42 SA_DM_3 AW38 SA_DM_4 AW13 SA_DM_5 BG8 SA_DM_6 AY5 SA_DQS_0 AT46 SA_DQS_1 BE48 SA_DQS_2 BB43 SA_DQS_3 BC37 SA_DQS_4 BB16 SA_DQS_5 BH6 SA_DQS_6 BB2 SA_DQS_7 AP3 SA_DM_7 AN6 SA_DQS#_0 AT47 SA_DQS#_1 BD47 SA_DQS#_2 BC41 SA_DQS#_3 BA37 SA_DQS#_4 BA16 SA_DQS#_5 BH7 SA_DQS#_6 BC1 SA_DQS#_7 AP2 SA_MA_0 BJ19 SA_MA_1 BD20 SA_MA_10 BC19 SA_MA_11 BE28 SA_MA_12 BG30 SA_MA_13 BJ16 SA_MA_2 BK27 SA_MA_3 BH28 SA_MA_4 BL24 SA_MA_5 BK28 SA_MA_6 BJ27 SA_MA_7 BJ25 SA_MA_8 BL28 SA_MA_9 BA28 SA_RAS# BE18 SA_RCVEN# AY20 SA_WE# BA19 T22 T21 5 5 4 4 3 3 2 2 1 1 D D C C B B A A ENABLT ENAVDD LCD_CLK LCD_DATA PEGCOMP CRT_R TV_CRMA TV_COMPS TV_LUMA CRT_G CRT_B 3VDDCDA 3VDDCCL CRT_HSYNC CRT_VSYNC LVDSA0+ LVDSA2+ LVDSA1+ LVDSA0- LVDSA2- LVDSA1- LVDSB1+ LVDSB2+ LVDSB0+ LVDSB1- LVDSB2- LVDSB0- LVDSAC+ LVDSAC- LVDSBC+ LVDSBC- BKLT_CTRL LCD_CLK17 LCD_DATA17 ENABLT17 ENAVDD17 CRT_R16 CRT_G16 CRT_B16 TV_COMPS16 TV_LUMA16 TV_CRMA16 3VDDCDA16 3VDDCCL16 CRT_HSYNC16 CRT_VSYNC16 LVDSA0+17 LVDSA2+17 LVDSA1+17 LVDSA0-17 LVDSA2-17 LVDSA1-17 LVDSB1+17 LVDSB2+17 LVDSB0+17 LVDSB1-17 LVDSB2-17 LVDSB0-17 LVDSAC+17 LVDSAC-17 LVDSBC+17 LVDSBC-17 +VCCP +3VS +3VS Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date LA-3981P 0.3 CRESTLINE((3/6)-VGA/LVDS/TV Custom 942Monday, October 22, 2007 2007/03/26 2006/03/10 Compal Electronics, Inc. CFG9 0 = Normal mode 1 = Low Power mode (PCIE Graphics Lane Reversal) CFG[2:0] FSB Freq select Reserved Reserved ReservedCFG[15:14] Strap Pin Table ReservedCFG[18:17] (Lane number in Order) Others = Reserved 011 = FSB 667MHz 010 = FSB 800MHz 11 = Normal Operation 10 = All Z Mode Enabled 01 = XOR Mode Enabled * 1 = Reverse Lane 0 = Reverse Lane SDVO_CTRLDATA 1 = Enabled 1 = SDVO Device Present 0 = Normal Operation 0 = No SDVO Device Present (Default) * 0 = Disabled * 0 = DMI x 2 00 = Reserved * * * * 1 = PCIE/SDVO are operating simu. 0 = Only PCIE or SDVO is operational. * 1 = Normal Operation 1 = DMI x 4 0 = Reserved 1 = Mobile CPU CFG5 (DMI select) CFG19 (DMI Lane Reversal) CFG16 (FSB Dynamic ODT) CFG6 CFG7 (CPU Strap) CFG20 (PCIE/SDVO concurrent) CFG[11:10] CFG[13:12] (XOR/ALLZ) CFG8 (Low power PCIE) * For Calero: 255ohm For Crestline:1.3kohm For Calero: 1.5Kohm For Crestline:2.4kohm PEGCOMP trace width and spacing is 20/25 mils. CFG[19:18] have internal pull down CFG[17:3] have internal pull up R52 24.9_0402_1% 1 2 R55 2.4K_0402_1% 12 R53 10K_0402_5% 1 2 R57 1.3K_0402_1% 12 R56 2.2K_0402_5% 1 2 LVDS PCI-EXPRESS GRAPHICS TV VGA U3C CRESTLINE_1p0 PEG_COMPI N43 PEG_COMPO M43 PEG_RX#_0 J51 PEG_RX#_1 L51 PEG_RX#_2 N47 PEG_RX#_3 T45 PEG_RX#_4 T50 PEG_RX#_5 U40 PEG_RX#_6 Y44 PEG_RX#_7 Y40 PEG_RX#_8 AB51 PEG_RX#_9 W49 PEG_RX#_10 AD44 PEG_RX#_11 AD40 PEG_RX#_12 AG46 PEG_RX#_13 AH49 PEG_RX#_14 AG45 PEG_RX#_15 AG41 PEG_RX_0 J50 PEG_RX_1 L50 PEG_RX_2 M47 PEG_RX_3 U44 PEG_RX_4 T49 PEG_RX_5 T41 PEG_RX_6 W45 PEG_RX_7 W41 PEG_RX_8 AB50 PEG_RX_9 Y48 PEG_RX_10 AC45 PEG_RX_11 AC41 PEG_RX_12 AH47 PEG_RX_13 AG49 PEG_RX_14 AH45 PEG_RX_15 AG42 PEG_TX#_0 N45 PEG_TX#_10 AC46 PEG_TX#_3 N51 PEG_TX#_4 R50 PEG_TX#_5 T42 PEG_TX#_6 Y43 PEG_TX#_7 W46 PEG_TX#_8 W38 PEG_TX#_9 AD39 PEG_TX#_1 U39 PEG_TX#_11 AC49 PEG_TX#_12 AC42 PEG_TX#_13 AH39 PEG_TX#_14 AE49 PEG_TX#_15 AH44 PEG_TX#_2 U47 PEG_TX_0 M45 PEG_TX_1 T38 PEG_TX_2 T46 PEG_TX_3 N50 PEG_TX_4 R51 PEG_TX_5 U43 PEG_TX_6 W42 PEG_TX_7 Y47 PEG_TX_8 Y39 PEG_TX_9 AC38 PEG_TX_10 AD47 PEG_TX_11 AC50 PEG_TX_12 AD43 PEG_TX_13 AG39 PEG_TX_14 AE50 PEG_TX_15 AH43 L_CTRL_CLK E39 L_CTRL_DATA E40 L_DDC_CLK C37 L_DDC_DATA D35 L_VDD_EN K40 LVDS_IBG L41 LVDS_VBG L43 LVDS_VREFH N41 LVDS_VREFL N40 LVDSA_CLK# D46 LVDSA_CLK C45 LVDSA_DATA#_0 G51 LVDSA_DATA#_1 E51 LVDSA_DATA#_2 F49 LVDSA_DATA_1 E50 LVDSA_DATA_2 F48 LVDSB_CLK# D44 LVDSB_CLK E42 LVDSB_DATA#_0 G44 LVDSB_DATA#_1 B47 LVDSB_DATA#_2 B45 LVDSB_DATA_1 A47 LVDSB_DATA_2 A45 L_BKLT_EN H39 TVA_DAC E27 TVB_DAC G27 TVC_DAC K27 TVA_RTN F27 TVB_RTN J27 TVC_RTN L27 CRT_BLUE H32 CRT_BLUE# G32 CRT_DDC_CLK K33 CRT_DDC_DATA G35 CRT_GREEN K29 CRT_GREEN# J29 CRT_HSYNC F33 CRT_TVO_IREF C32 CRT_RED F29 CRT_RED# E29 CRT_VSYNC E33 LVDSA_DATA_0 G50 LVDSB_DATA_0 E44 L_BKLT_CTRL J40 TV_DCONSEL_0 M35 TV_DCONSEL_1 P33 R54 10K_0402_5% 1 2 5 5 4 4 3 3 2 2 1 1 D D C C B B A A +1.25VM_A_SM +VCCP +V1.25VS_AXF +1.25VS +1.25VS_DMI +1.8V_SM_CK +3VS_HV +VCC_PEG +1.25VS_PEGPLL +1.25VS +1.25VM_AXD +1.25VM_A_SM_CK +3VS_PEG_BG +3VS +1.8V_TXLVDS +3VS +3VS_DAC_BG +3VS +3VS_DAC_CRT +3VS +3VS_TVDACA +3VS +3VS_TVDACB +3VS +3VS_TVDACC +1.8V +1.8V_LVDS +1.5VS +1.5VS_QDAC +3VS_TVDACA +3VS_TVDACB +3VS_TVDACC +1.25VS_PEGPLL +1.25VM_HPLL +1.5VS_TVDAC +1.8V_LVDS +1.5VS_QDAC +1.8V_TXLVDS +1.25VM_MPLL +1.25VS_DPLLB +1.25VM_HPLL +1.25VS_DPLLA +3VS_DAC_BG VCCSYNC +3VS +3VS_DAC_CRT +1.8V_TXLVDS +1.8V +1.25VM_HPLL +1.25VS +1.25VM_MPLL +1.25VS +VCCP +1.25VS_PEGPLL +1.25VS +1.25VS +V1.25VS_AXF +1.25VS +1.25VS_DMI +1.8V +1.8V_SM_CK +1.25VS_DPLLA +1.25VS_DPLLB +1.25VS +1.25VS +1.5VS +1.5VS_TVDAC +VCCP +3VS +VCCP_D +3VS_HV +VCC_PEG Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date LA-3981P 0.3 CRESTLINE(4/6)-PWR Custom 10 42Monday, October 22, 2007 2007/03/26 2006/03/10 Compal Electronics, Inc. 20 mils 20mils 10mA 80mA 5mA 80mA 80mA 50mA 150mA 10mA 5mA 950mA 100mA 40mA 40mA 40mA 75mA 5mA 250mA 100mA 150mA 850mA 200mA 350mA 100mA 120mA 100mA 100mA 1200mA 250mA 1450mA 50mA 25mA 0925_Change C439 from 0.47uF to 4.7uF. 1022_Change R64, R79 from 0 ohm to 1uH/400mA inductor. C81 0.1U_0402_16V4Z 1 2 R70 MBK2012121YZF_0805 12 + C71 220U_6.3V_M 1 2 C115 0.022U_0402_16V7K 1 2 C65 0.022U_0402_16V7K 1 2 R74 BLM18PG181SN1D_0603 12 C88 0.022U_0402_16V7K 1 2 C73 0.022U_0402_16V7K 1 2 R69 10U_FLC-453232-100K_0.25A_10% 1 2 + C104 220U_6.3V_M 1 2 C103 0.1U_0402_16V4Z 1 2 C121 0.022U_0402_16V7K 1 2 C93 1U_0603_10V4Z 1 2 C92 4.7U_0805_10V4Z 1 2 C100 10U_0805_10V4Z 1 2 C86 0.1U_0402_16V4Z 1 2 C97 0.1U_0402_16V4Z 1 2 C101 1U_0603_10V4Z 1 2 R66 0_0603_5% 12 C96 10U_0805_10V4Z 1 2 R73 MBK2012121YZF_0805 12 C108 0.47U_0603_10V7K 1 2 POWER CRTPLLA PEGA SMTV D TV/CRTLVDS VTTLF PEG SM CK AXD AXF VTT DMI HV A CK A LVDS U3H CRESTLINE_1p0 VTT_19 T2 VTT_20 R3 VTT_21 R2 VTT_22 R1 VCCD_CRT M32 VCCA_PEG_BG K50 VCCA_PEG_PLL U51 VCCA_CRT_DAC_1 A33 VCCA_CRT_DAC_2 B33 VCCA_DPLLA B49 VCCA_DPLLB H49 VCCA_HPLL AL2 VCCA_LVDS A41 VCCA_MPLL AM2 VCCA_TVA_DAC_1 C25 VCCA_TVA_DAC_2 B25 VCCA_TVB_DAC_1 C27 VCCA_TVB_DAC_2 B27 VCCA_TVC_DAC_1 B28 VCCA_TVC_DAC_2 A28 VCCD_PEG_PLL U48 VTT_15 T7 VTT_16 T6 VTT_17 T5 VTT_18 T3 VTT_12 T11 VTT_13 T10 VTT_14 T9 VCCSYNC J32 VCCD_HPLL AN2 VTT_1 U13 VTT_2 U12 VTT_4 U9 VTT_5 U8 VTT_6 U7 VTT_7 U5 VTT_8 U3 VTT_9 U2 VTT_10 U1 VTT_11 T13 VTT_3 U11 VCCA_SM_CK_1 BC29 VCCA_SM_CK_2 BB29 VCCA_DAC_BG A30 VCCD_TVDAC L29 VTTLF1 A7 VTTLF2 F2 VTTLF3 AH1 VCC_RXR_DMI_1 AH50 VCC_RXR_DMI_2 AH51 VCC_SM_CK_1 BK24 VCC_SM_CK_2 BK23 VCC_SM_CK_3 BJ24 VCC_SM_CK_4 BJ23 VCCD_LVDS_1 J41 VCCD_QDAC N28 VCC_AXD_2 AU28 VCC_AXD_3 AU24 VCC_AXD_5 AT25 VCC_AXF_1 B23 VCC_AXF_2 B21 VCC_AXF_3 A21 VCCA_SM_1 AW18 VCCA_SM_2 AV19 VCCA_SM_3 AU19 VCCA_SM_4 AU18 VCCA_SM_5 AU17 VCCA_SM_7 AT22 VCCA_SM_8 AT21 VCCA_SM_9 AT19 VCC_DMI AJ50 VCC_TX_LVDS A43 VSSA_DAC_BG B32 VSSA_LVDS B41 VSSA_PEG_BG K49 VCC_HV_1 C40 VCC_HV_2 B40 VCC_PEG_1 AD51 VCCA_SM_10 AT18 VCCA_SM_11 AT17 VCCA_SM_NCTF_1 AR17 VCCA_SM_NCTF_2 AR16 VCCD_LVDS_2 H42 VCC_PEG_2 W50 VCC_PEG_3 W51 VCC_PEG_4 V49 VCC_PEG_5 V50 VCC_AXD_NCTF AR29 VCC_AXD_4 AT29 VCC_AXD_6 AT30 VCC_AXD_1 AT23 C87 10U_0805_10V4Z 1 2 C112 0.1U_0402_16V4Z 1 2 C67 0.1U_0402_16V4Z 1 2 R72 0_0805_5% 12 R68 0_0805_5% 1 2 C78 10U_0805_10V4Z 1 2 C91 10U_0805_10V4Z 1 2 C83 1U_0603_10V4Z 1 2 C75 0.47U_0603_10V7K 1 2 R60 10U_FLC-453232-100K_0.25A_10% 1 2 C105 10U_0805_10V4Z 1 2 R75 10_0402_5% 12 L1 BLM18PG121SN1D_0603 12 C82 1000P_0402_50V7K 1 2 C110 0.47U_0603_10V7K 1 2 C76 4.7U_0805_10V4Z 1 2 C79 10U_0805_10V4Z 1 2 C84 10U_0805_10V4Z 1 2 C114 0.1U_0402_16V4Z 1 2 C98 10U_0805_10V4Z 1 2 C85 0.1U_0402_16V4Z 1 2 C89 0.1U_0402_16V4Z 1 2 C111 0.022U_0402_16V7K 1 2 C64 0.1U_0402_16V4Z 1 2 R71 0_0603_5% 12 R63 0_0603_5% 1 2 R59 BLM18PG181SN1D_0603 12 R62 BLM18PG181SN1D_0603 12 R77 100_0603_1% 12 C116 0.1U_0402_16V4Z 1 2 R58 0_0603_5% 12 C72 4.7U_0805_10V4Z 1 2 R61 0_0603_5% 1 2 R67 0_0805_5% 1 2 C99 1U_0603_10V4Z 1 2 C118 1000P_0402_50V7K 1 2 R64 1U_WIM32251R0KZF_10% 1 2 R65 0_0805_5% 1 2 C102 0.1U_0402_16V4Z 1 2 C95 0.1U_0402_16V4Z 1 2 C107 10U_0805_10V4Z 1 2 R76 0_0402_5% 12 R78 BLM18PG181SN1D_0603 12 C119 10U_0805_10V4Z 1 2 C109 0.47U_0603_10V7K 1 2 C120 1U_0603_10V4Z 1 2 C117 10U_0805_10V4Z 1 2 C106 0.1U_0402_16V4Z 1 2 C80 0.1U_0402_16V4Z 1 2 C69 10U_0805_10V4Z 1 2 C113 0.022U_0402_16V7K 1 2 D2 CH751H-40PT_SOD323-2 2 1 R79 1U_WIM32251R0KZF_10% 12 R81 0_0603_5% 12 C66 0.1U_0402_16V4Z 1 2 + C90 220U_6.3V_M 1 2 C122 0.1U_0402_16V4Z 1 2 C77 2.2U_0805_16V4Z 1 2 C68 10U_0805_10V4Z 1 2 C74 0.1U_0402_16V4Z 1 2 C439 4.7U_0603_6.3V6K 1 2 C70 1U_0603_10V4Z 1 2 R80 BLM18PG181SN1D_0603 12 [...]... LVDSB 0- LVDSB0+ LVDSB 0- 9 9 LVDSB1+ LVDSB 1- 9 9 680P_0402_50V7K 2 1 680P_0402_50V7K 1 680P_0402_50V7K 2 1 C252 9 9 C LVDSBC+ LVDSBC- LVDSBC+ LVDSBC- LVDSB1+ LVDSB1LVDSB2+ LVDSB 2- LVDSB2+ LVDSB 2- 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 LVDSA2+ LVDSA 2- LVDSA2+ 9 LVDSA 2- 9 LVDSA1+ LVDSA 1- LVDSA1+ 9 LVDSA 1- 9 LVDSA0+ LVDSA 0- +3VS LVDSA0+ 9 LVDSA 0- 9 LVDSAC+ LVDSAC- LVDSAC+ 9 LVDSAC- 9... +5VS 2 R142 75_0402_5% 1 2 CRT_B C236 10P_0402_50V8J CRT_B CRT_G C233 10P_0402_50V8J 9 CRT_R CRT_R CRT_G R141 75_0402_5% 1 2 9 9 L2 FBMA-L1 0-2 0120 9-1 21LMT_0805 1 2 L3 FBMA-L1 0-2 0120 9-1 21LMT_0805 1 2 L4 FBMA-L1 0-2 0120 9-1 21LMT_0805 1 2 2.2K_0402_5% 3 3 TV-Out Connector S-Video L7 MBC1608121YZF_0603 1 2 1 R153 9 2 0_0402_5% TVCRMA R154 4 2 1 2 C246 270P_0402_50V7K 1 C245 270P_0402_50V7K TVCOMPS C244 270P_0402_50V7K... 53 15 MINI_CLKREQ# +1.5VS L12 FBMA-L1 1-2 0120 9-1 02LMA10T 1 2 2 L13 FBMA-L1 1-2 0120 9-1 02LMA10T 1 2 DEBUG@ 0_0402_5% 1 2 DEBUG@ 0_0402_5% 1 2 DEBUG@ 0_0402_5% 1 2 DEBUG@ 0_0402_5% 1 2 DEBUG@ 0_0402_5% WL_LED# R411 100K_0402_5% WL_LED# 28 2 ICH_PCIE_WAKE# 20 ICH_PCIE_WAKE# +3VS WL_LED# 4 FOX_AS0B226-S40N-7F~D Mini Card STANDOFF H19 HOLEA SP01000P700 S H-CONN ACES 8891 4-5 204 52P P0.8 H20 HOLEA 1 1 Issued... +5VALW +3VS 2 S 1 SI2301BDS-T1-E3_SOT2 3-3 3 D 1 R162 2 R161 30 1 BKOFF# D9 3 S C259 1 Q9 2N7002_SOT2 3-3 3 1 100K_0402_5% C260 0.22U_0402_10V4Z S 0.047U_0402_16V7K 2 C258 C257 4.7U_0805_10V4Z 1 ENABLT 1 2 1 D 2 G 2 CH751H-40PT_SOD32 3-2 R164 4.7U_0805_10V4Z 100K_0402_5% 2 2 2 R308 100K_0402_5% 2 1 1 9 1 ENAVDD DI SPLAYOFF# 2 CH751H-40PT_SOD32 3-2 2 G R298 9 1 D8 1 2 1 D Q8 2N7002_SOT2 3-3 4.7K_0402_5% 2 G R163... PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C D Title Compal Electronics, Inc CRT & TVout Connector Size Document Number Rev 0.3 LA-3981P Date: Monday, October 22, 2007 Sheet E 16 of 42 5 4 3 2 1 +5VALW J2 1 +5VS @ JOPEN 2 J3 1 JOPEN 2 LVDS CONN Q35 SI2301BDS-T1-E3_SOT2 3-3 D D D S 3 1 B+ +LCDVDD INVPWR_B+ 2 G @ L10 30 WEBCAM_ON/OFF# 2 0_0805_5% 1 1 C250 L11 1 2 FBMA-L1 1-2 0120 9-2 21LMA30T_0805... 8520 4-0 2001 2P P1.25 ACES_8520 4-0 2001_2P B D21, D25, D23 Footprint can not match part number 1 3 SN100000F00 S TACT SW SMT 1-0 5-A SPST HCH H1.5 4P SW_SMT 1-0 5-A_4P 30 1 2 SYSON 30,31,35 SYSON 2 D S Q34 2N7002_SOT2 3-3 2 G 1 2 1 2 TP_DATA 30 TP_CLK 30 ACES_8520 1-0 405N CONN@ @C413 100P_0402_50V8J 1 A TP_LED# 0.1U_0402_16V4Z 1 2 3 4 5 6 1 1 2 3 4 G1 G2 On (TP_LED#=L )-> Blue Off (TP_LED#=H )-> Amber 2 JP22 3 2 D Q22... Off (TP_LED#=H )-> Amber 2 JP22 3 2 D Q22 TP_LED# 2 G 2N7002_SOT2 3-3 1 1 TP_BTN# 30 D S 2 2 4 R384 10K_0402_5% 1 @ C412 TP_BTN# 5 6 Orange Blue 3 1 LTST-C195TBKFKT_BLUE/ORG 1 1 2 2 4 2 1 2 SW1 SMT 1-0 5-A_4P 3 D 3 G AMBER +5V Q33 SI2301BDS-T1-E3_SOT2 3-3 S TP_LED#_LIGHT +5VALW D24 PACDN042Y3R_SOT2 3-3 R340 10K_0402_5% D23 Q21 2N7002_SOT2 3-3 2 G 3 +5V R339 330_0402_5% BLUE R341 10K_0402_5% TP_DATA TP_CLK... 6 CM129 3-0 4SO_SOT2 3-6 CH3 U23 CH2 1 2 3 4 5 6 7 8 9 10 11 12 ON/OFFBTN# 1 +3VALW +3VS WL_BTN# ON/OFFBTN_LED# WL_LED# LID_SW# LID_SW# 2 1 2 LTST-C191TBKT-5A_BLUE_0603 27_0402_5% +3VS 3 Battery Charge LED(Left 2) 1 2 3 4 5 6 7 8 9 10 GND GND R331 D18 30 1 BAT_LED# D +3VALW BLUE 2 1 2 LTST-C191TBKT-5A_BLUE_0603 27_0402_5% HDD LED(Left 3) +3VS ACES_8520 1-1 005N CONN@ BLUE R333 D20 SP01000H400 S H-CONN ACES... PCI_STOP# 46 AT93C4 6-1 0SU-2.7_SO8 ACTIVITY#_R 1 2 R278 0_0603_5% LINK_100#_R 1 2 R279 0_0603_5% 76 61 63 67 68 69 PAR FRAME# IRDY# TRDY# DEVSEL# STOP# PCI_PERR# PCI_SERR# 70 75 PERR# SERR# PCI_REQ0# PCI_GNT0# 30 29 REQ# GNT# 25 CLK_PCI_LAN 1 2 R289 10K_0402_5% 28 65 2 1K_0402_5% 2 15K_0402_5% 2 5.6K_0603_1% 1 1 1 NC/AVDDH NC/HV RJ11 CONN@ JM34F2-M512 5-7 F JM34F2*-N512 5-7 F JM34F2A-M512 5-7 F C +3VS @ D28... C335 680P_0402_50V7K IDSEL PCI_RST# 0.1U_0402_16V4Z 2 ACTIVITY# TXD+/MDI0+ TXD-/MDI0RXIN+/MDI1+ RXIN-/MDI 1- 1 2 5 6 X1 X2 C/BE#0 C/BE#1 C/BE#2 C/BE#3 PCI_PME# TX 1- R_MDO0+ R277 300_0603_5% 1 2 LINK# 3 DO DI SK CS 1 NC/MDI2+ NC/MDI2NC/MDI3+ NC/MDI 3- 4 17 128 CLK_PCI_LAN 4 3 2 1 2 TXD+/MDI0+ TXD-/MDI0RXIN+/MDI1+ RXIN-/MDI 1- 92 77 60 44 PCI_PIRQ# RX1+ 2 3 18 PCI_PAR 18 PCI_FRAME# 18 PCI_IRDY# 18 PCI_TRDY# . Electronics, Inc. REV:0.2 Mobile Merom uFCPGA with Satna Rosa Platform Schematics Document 200 7-0 8-0 2 Compal confidential A A B B C C D D E E 1 1 2 2 3 3 4 4 Title Size Document Number Rev Date:. A ENABLT ENAVDD LCD_CLK LCD_DATA PEGCOMP CRT_R TV_CRMA TV_COMPS TV_LUMA CRT_G CRT_B 3VDDCDA 3VDDCCL CRT_HSYNC CRT_VSYNC LVDSA0+ LVDSA2+ LVDSA1+ LVDSA 0- LVDSA 2- LVDSA 1- LVDSB1+ LVDSB2+ LVDSB0+ LVDSB 1- LVDSB 2- LVDSB 0- LVDSAC+ LVDSAC- LVDSBC+ LVDSBC- BKLT_CTRL LCD_CLK17 LCD_DATA17 ENABLT17 ENAVDD17 CRT_R16 CRT_G16 CRT_B16 TV_COMPS16 TV_LUMA16 TV_CRMA16 3VDDCDA16 3VDDCCL16 CRT_HSYNC16 CRT_VSYNC16 LVDSA0+17 LVDSA2+17 LVDSA1+17 LVDSA 0-1 7 LVDSA 2-1 7 LVDSA 1-1 7 LVDSB1+17 LVDSB2+17 LVDSB0+17 LVDSB 1-1 7 LVDSB 2-1 7 LVDSB 0-1 7 LVDSAC+17 LVDSAC-17 LVDSBC+17 LVDSBC-17 +VCCP +3VS +3VS Title Size Document Number Rev Date:. A ENABLT ENAVDD LCD_CLK LCD_DATA PEGCOMP CRT_R TV_CRMA TV_COMPS TV_LUMA CRT_G CRT_B 3VDDCDA 3VDDCCL CRT_HSYNC CRT_VSYNC LVDSA0+ LVDSA2+ LVDSA1+ LVDSA 0- LVDSA 2- LVDSA 1- LVDSB1+ LVDSB2+ LVDSB0+ LVDSB 1- LVDSB 2- LVDSB 0- LVDSAC+ LVDSAC- LVDSBC+ LVDSBC- BKLT_CTRL LCD_CLK17 LCD_DATA17 ENABLT17 ENAVDD17 CRT_R16 CRT_G16 CRT_B16 TV_COMPS16 TV_LUMA16 TV_CRMA16 3VDDCDA16 3VDDCCL16 CRT_HSYNC16 CRT_VSYNC16 LVDSA0+17 LVDSA2+17 LVDSA1+17 LVDSA 0-1 7 LVDSA 2-1 7 LVDSA 1-1 7 LVDSB1+17 LVDSB2+17 LVDSB0+17 LVDSB 1-1 7 LVDSB 2-1 7 LVDSB 0-1 7 LVDSAC+17 LVDSAC-17 LVDSBC+17 LVDSBC-17 +VCCP +3VS +3VS Title Size