A A B B C C D D E E 1 1 2 2 3 3 4 4 Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date LA-3491P 0.5 Cover Sheet Custom 147Tuesday, March 20, 2007 2006/10/26 2006/07/26 Compal Electronics, Inc. REV:0.5 Mobile Yonah uFCPGA with Intel Calistoga_GM+ ICH7-M core logic Schematics Document 2007-03-20 Compal confidential A A B B C C D D E E 1 1 2 2 3 3 4 4 Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date LA-3491P 0.5 Block Diagram Custom 247Tuesday, March 20, 2007 2006/10/26 2006/07/26 Compal Electronics, Inc. Power On/Off CKT. File Name : LA-3491P LPC BUS Compal confidential PCBGA 1466 page 22 H_A#(3 31) page 29 BANK 0, 1, 2, 3 USB Conn x2 533/667MHz DMI DC/DC Interface CKT. Mobile Yonah/Merom USB2.0 FSB Clock Generator ICS9LP306BGLFT Power Circuit DC/DC IDE ODD Connector PCI BUS uFCPGA-478 CPU page 31 DDR2-SO-DIMM X2 page 33 Intel Calistoga MCH page 4page 4,5,6 RTC CKT. page 15 DDR2 -400/533/667 mBGA-652 page 34 page 4 page 7,8,9,10,11,12 Intel ICH7-M Thermal Sensor ADM1032AR page 13,14 page 18,19,20,21 Power OK CKT. page 19 Fan Control Dual Channel Touch Pad CONN. Int.KBD SMSC KBC 1070 page 30 page 30page 32 Page 37 3 、 83940 、、 PCI-E BUS page 31 LED SPI 25LF080A SPI ROM page 31 H_D#(0 63) Volga 2.0 AC-LINK/Azalia page 22 SATA HDD Connector PATA Slave page 25 Mini-Card WLAN 945GM SATA page 26 CX20549-12 Audio Conexant page 27 MODEM AMOM page 28 AMP & Audio Jack TPA6017A2 CX20548 page 16 CRT page 17 LVDS Conn CardBus Controller CB-1410 page 24 Slot 0 page 24 page 23 page 23 82562V 10 /100 RJ45/11 CONN INTEL LAN 5 5 4 4 3 3 2 2 1 1 D D C C B B A A Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date LA-3491P 0.5 Notes List 347Tuesday, March 20, 2007 2006/10/26 2006/07/26 Compal Electronics, Inc. IDSEL # 2 1 0 1 0 0 1 0 0A4 I2C / SMBUS ADDRESSING C 1 0 1 0 0 0 0 0 D2 CARD BUS A0 CLOCK GENERATOR (EXT.) HEX DDR SO-DIMM 1 D6 ADDRESS PCI Device ID DDR SO-DIMM 0 DEVICE 1 1 0 1 0 0 1 0 External PCI Devices REQ/GNT # DEVICE AD22 PIRQ Voltage Rails Symbol Note : : means Digital Ground : means Analog Ground XDP@ : means just build when XDP function enable. When this time, docking PCI express will not work. CONN@ : means ME parts LP@ : means just build when Low power clock gen. install NOXDP@ : means just build when XDP function disable. BATT@ : means need be mounted when 45 level assy or rework stage. 45@ : means need be mounted when 45 level assy or rework stage. Debug@ : means Mini debug card use ICH7 R1 SA00000V1F0 ICH7 R3 SA00000V1A0 Calistoga 940GML R3 SA000011C10 Calistoga 945GM R3 SA0000059L0 Calistoga 945GM R1 SA0000059A0 Calistoga 940GML R1 SA000011C00 14@ : means need be mounted when 14.1" IAT50 945GM FF 46147932L01 IAT50 940GML DF 46147932L02 IAT60 945GM FF 46147932L21 IAT60 940GML DF 46147932L22 VIN OF F Power Plane N/AN/A ON AC or battery power rail for power circuit +CPU_CORE +0.9V S3 +1.5VS OF F +VCCP N/A ON 0.9V switched power rail for DDRII Vtt S0-S1 ON OFF ON N/A N/A OF F Description 1.05V power rail for Processor I/O and MCH/ICH core power Adapter power supply (18.5V) N/A OF F OF F Core voltage for CPU OF FOF F S5 1.5V switched power rail for PCI-E interface B+ OF F2.5V switched power rail for MCH video PLL 5V always on power rail ON 3.3V always on power rail 3.3V switched power rail+3VS ON* RTC power ONON Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF. +1.8V OF F OF F ON ON +3VALW OF F ON 5V switched power rail ON +2.5VS +RTC_VCC +5VS ON ON ON OFF +5VALW ON 1.8V power rail for DDRII ON* ON OFF OFF IAT50 940GML DF 46147932L03 (No WLAN) IAT60 940GML DF 46147932L23 (No WLAN) WLAN@ : means need be mounted when have wireless LED Function WLAN14@ : means need be mounted when have wireless LED Function and 14" 5 5 4 4 3 3 2 2 1 1 D D C C B B A A H_A#28 H_THERMDA H_FERR# H_ADSTB#0 H_A#23 H_REQ#2 H_A#31 H_REQ#0 H_A#17 H_BNR# H_A#29 H_DSTBP#0 H_A#8 H_DEFER# H_REQ#1 H_A#3 H_RS#0 H_DSTBN#1 H_A#6 XDP_BPM#2 H_BPRI# H_ADS# H_A#25 XDP_BPM#3 H_RS#1 H_DSTBP#1 H_A#4 H_IERR# H_HITM# H_DSTBN#0 H_INTR H_DSTBN#2 H_A#22 H_A#7 H_REQ#4 XDP_DBRESET# H_DRDY# H_A#15 H_A#14 H_A20M# H_DINV#0 H_DSTBP#2 H_DINV#2 H_DINV#3 H_DINV#1 H_DSTBN#3 H_DSTBP#3 H_NMI H_A#30 H_A#27 H_A#18 H_A#10 H_BR0# H_LOCK# H_A#11 H_A#21 H_A#26 H_A#13 H_A#9 XDP_BPM#0 H_DPSLP# H_A#20 H_A#16 H_A#12 H_HIT# H_ADSTB#1 H_THERMTRIP# H_DBSY# H_A#19 H_A#24 H_A#5 H_RS#2 H_RESET# XDP_BPM#1 H_REQ#3 H_SMI# H_STPCLK# XDP_TCK XDP_TRST# XDP_TMS H_CPUSLP# XDP_TDO XDP_TDI H_PWRGOOD XDP_BPM#5 H_DPRSTP# H_TRDY# CLK_CPU_BCLK CLK_CPU_BCLK# ICH_SMBCLK ICH_SMBDATA H_THERMDA H_THERMDC THERM# ICH_SMBDATA ICH_SMBCLK THERM# H_THERMDC XDP_BPM#4 H_DPWR# TEST1 TEST2 H_D#0 H_D#1 H_D#2 H_D#3 H_D#7 H_D#6 H_D#4 H_D#5 H_D#11 H_D#10 H_D#8 H_D#9 H_D#15 H_D#14 H_D#12 H_D#13 H_D#19 H_D#18 H_D#16 H_D#17 H_D#23 H_D#22 H_D#20 H_D#21 H_D#27 H_D#26 H_D#24 H_D#25 H_D#31 H_D#30 H_D#28 H_D#29 H_D#35 H_D#34 H_D#32 H_D#33 H_D#39 H_D#38 H_D#36 H_D#37 H_D#43 H_D#42 H_D#40 H_D#41 H_D#47 H_D#46 H_D#44 H_D#45 H_D#51 H_D#50 H_D#48 H_D#49 H_D#55 H_D#54 H_D#52 H_D#53 H_D#59 H_D#58 H_D#56 H_D#57 H_D#63 H_D#62 H_D#60 H_D#61 H_INIT# H_IGNNE# H_PROCHOT# H_PROCHOT# OCP# H_DPSLP# H_DPRSTP# XDP_HOOK1 XDP_HOOK1 XDP_BPM#3 XDP_DBRESET#_R XDP_BPM#0 XDP_BPM#1 XDP_BPM#2 XDP_PRE XDP_DBRESET#XDP_DBRESET#_R XDP_TDI XDP_TMS XDP_TCK XDP_TRST# XDP_TCK XDP_TDO H_RESET# XDP_TRST# XDP_TMS XDP_TDO XDP_TDI H_PWRGOOD_R H_RESET#_R XDP_BPM#5 CLK_CPU_XDP# CLK_CPU_XDP XDP_BPM#4 XDP_BPM#5 FAN THERM_SCI# H_PWRGOOD ICH_SMBDATA<13,14,15,20,25> ICH_SMBCLK<13,14,15,20,25> THERM_SCI# <20> FAN_PWM<30> H_D#[0 63] <7> H_A#[3 31]<7> H_REQ#[0 4]<7> H_ADSTB#0<7> H_ADSTB#1<7> CLK_CPU_BCLK#<15> CLK_CPU_BCLK<15> H_ADS#<7> H_BNR#<7> H_BR0#<7> H_DRDY#<7> H_HIT#<7> H_HITM#<7> H_BPRI#<7> H_DEFER#<7> H_LOCK#<7> H_RESET#<7> H_RS#[0 2]<7> H_TRDY#<7> H_DBSY#<7> H_DPSLP#<19> H_DPRSTP#<19,40> H_DPWR#<7> H_CPUSLP#<7> H_THERMTRIP#<7,19> H_DINV#0 <7> H_DINV#1 <7> H_DINV#2 <7> H_DINV#3 <7> H_DSTBN#[0 3] <7> H_DSTBP#[0 3] <7> H_A20M# <19> H_FERR# <19> H_IGNNE# <19> H_INIT# <19> H_INTR <19> H_NMI <19> H_STPCLK# <19> H_SMI# <19> XDP_DBRESET#<20> H_PROCHOT#<40> OCP# <20,30,42> H_PWRGOOD<19> CLK_CPU_XDP <15> CLK_CPU_XDP# <15> +VCCP +3VS +3VS +5VS +3VS +VCCP +VCCP +3VS +VCCP+VCCP +VCCP Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date LA-3491P 0.5 Yonah CPU in mFCPGA479 447Tuesday, March 20, 2007 2006/10/26 2006/07/26 Compal Electronics, Inc. H_THERMDA, H_THERMDC routing together. Trace width / Spacing = 10 / 10 mil Thermal Sensor ADM1032AR-2 Address:1001_101 PWM Fan Control circuit Place R2203 within 200ps (~1") to CPU Change to same as Chimay 4/6 This shall place near CPU ITP-XDP Connector Change value in 5/02 Removed at 5/30.(Follow Chimay) Follow datasheet 12/05 S G D Q1 AO6402_TSOP6 3 6 2 4 5 1 R2201 1K_0402_1% XDP@ 1 2 JP3 ACES_85205-0200 CONN@ 1 2 U1 ADM1032AR-2_MSOP8 VDD 1 ALERT# 6 THERM# 4 GND 5 D+ 2 D- 3 SCLK 8 SDATA 7 R2199 54.9_0402_1%@ 1 2 C1455 0.1U_0402_16V7K XDP@ 12 ZD1 RLZ5.1B_LL34 @ 12 R12 56_0402_5% 1 2 R2202 200_0402_1% XDP@ 12 R2203 0_0402_5% XDP@ 1 2 R15 56_0402_5% 1 2 ADDR GROUP CONTROL HOST CLK MISC DATA GROUP THERMAL DIODE LEGACY CPU YONAH JP1A FOX_PZ47903-2741-42_YONAH CONN@ A3# J4 A4# L4 A5# M3 A6# K5 A7# M1 A8# N2 A9# J1 A10# N3 A11# P5 A12# P2 A13# L1 A14# P4 A15# P1 A16# R1 A17# Y2 A18# U5 A19# R3 A20# W6 A21# U4 A22# Y5 A23# U2 A24# R4 A25# T5 A26# T3 A27# W3 A28# W5 A29# Y4 A30# W2 A31# Y1 REQ0# K3 REQ1# H2 REQ2# K2 REQ3# J3 REQ4# L5 ADSTB0# L2 ADSTB1# V4 BCLK0 A22 BCLK1 A21 ADS# H1 BNR# E2 BPRI# G5 BR0# F1 DEFER# H5 DRDY# F21 HIT# G6 HITM# E4 IERR# D20 LOCK# H4 RESET# B1 RS0# F3 RS1# F4 RS2# G3 TRDY# G2 BPM0# AD4 BPM1# AD3 BPM2# AD1 BPM3# AC4 DBR# C20 DBSY# E1 DPSLP# B5 DPWR# D24 PRDY# AC2 PREQ# AC1 PROCHOT# D21 PWRGOOD D6 SLP# D7 TCK AC5 TDI AA6 TDO AB3 TEST1 C26 TEST2 D25 TMS AB5 TRST# AB6 THERMDA A24 THERMDC A25 THERMTRIP# C7 D0# E22 D1# F24 D2# E26 D3# H22 D4# F23 D5# G25 D6# E25 D7# E23 D8# K24 D9# G24 D10# J24 D11# J23 D12# H26 D13# F26 D14# K22 D15# H25 D16# N22 D17# K25 D18# P26 D19# R23 D20# L25 D21# L22 D22# L23 D23# M23 D24# P25 D25# P22 D26# P23 D27# T24 D28# R24 D29# L26 D30# T25 D31# N24 D32# AA23 D33# AB24 D34# V24 D35# V26 D36# W25 D37# U23 D38# U25 D39# U22 D40# AB25 D41# W22 D42# Y23 D43# AA26 D44# Y26 D45# Y22 D46# AC26 D47# AA24 D48# AC22 D49# AC23 D50# AB22 D51# AA21 D52# AB21 D53# AC25 D54# AD20 D55# AE22 D56# AF23 D57# AD24 D58# AE21 D59# AD21 D60# AE25 D61# AF25 D62# AF22 D63# AF26 DINV0# J26 DINV1# M26 DINV2# V23 DINV3# AC20 DSTBN0# H23 DSTBN1# M24 DSTBN2# W24 DSTBN3# AD23 DSTBP0# G22 DSTBP1# N25 DSTBP2# Y25 DSTBP3# AE24 A20M# A6 FERR# A5 IGNNE# C4 INIT# B3 LINT0 C6 LINT1 B4 STPCLK# D5 SMI# A3 DPRSTP# E5 R16 1K_0402_5%@ 1 2 R20 56_0402_5%@ 1 2 R5 54.9_0402_1% 1 2 D1 CH751H-40_SC76 2 1 U2 TC7SH00FU_SSOP5 INB 1 INA 2 O 4 G 3 P 5 C5 0.1U_0402_16V4Z 1 2 R18 56_0402_5%@ 12 E B C Q2 MMBT3904_SOT23@ 2 3 1 R13 10K_0402_5% 12 C2 0.1U_0402_16V4Z 1 2 R6 51_0402_1% 1 2 R3 54.9_0402_1% 1 2 R2 54.9_0402_1% 1 2 R10 1K_0402_5%@ 1 2 C4 4.7U_0805_10V4Z 1 2 R14 10K_0402_5% 1 2 R4 54.9_0402_1% 1 2 R19 56_0402_5%@ 1 2 R7 54.9_0402_1% 1 2 C3 2200P_0402_50V7K 1 2 R17 51_0402_5% 12 JP29 SAMTE_BSH-030-01-L-D-ACONN@ GND0 1 OBSFN_A0 3 OBSFN_A1 5 GND2 7 OBSDATA_A0 9 OBSDATA_A1 11 GND4 13 OBSDATA_A2 15 OBSDATA_A3 17 GND6 19 OBSFN_B0 21 OBSFN_B1 23 GND8 25 OBSDATA_B0 27 OBSDATA_B1 29 GND10 31 OBSDATA_B2 33 OBSDATA_B3 35 GND12 37 PWRGOOD/HOOK0 39 HOOK1 41 VCC_OBS_AB 43 HOOK2 45 HOOK3 47 GND14 49 SDA 51 SCL 53 TCK1 55 TCK0 57 GND16 59 GND1 2 OBSFN_C0 4 OBSFN_C1 6 GND3 8 OBSDATA_C0 10 OBSDATA_C1 12 GND5 14 OBSDATA_C2 16 OBSDATA_C3 18 GND7 20 OBSFN_D0 22 OBSFN_D1 24 GND9 26 OBSDATA_D0 28 OBSDATA_D1 30 GND11 32 OBSDATA_D2 34 OBSDATA_D3 36 GND13 38 ITPCLK/HOOK4 40 ITPCLK#/HOOK5 42 VCC_OBS_CD 44 RESET#/HOOK6 46 DBR#/HOOK7 48 GND15 50 TD0 52 TRST# 54 TDI 56 TMS 58 GND17 60 R2200 1K_0402_5% XDP@ 1 2 5 5 4 4 3 3 2 2 1 1 D D C C B B A A COMP3 COMP2 H_PSI# COMP1 COMP0 CPU_VID1 CPU_VID0 CPU_VID3 CPU_VID4 CPU_VID2 CPU_VID5 CPU_VID6 CPU_BSEL1 CPU_BSEL2 CPU_BSEL0 VSSSENSE VCCSENSE VSSSENSE VCCSENSE H_PSI#<40> CPU_VID0<40> CPU_VID1<40> CPU_VID2<40> CPU_VID3<40> CPU_VID4<40> CPU_VID5<40> CPU_VID6<40> CPU_BSEL0<15> CPU_BSEL1<15> CPU_BSEL2<15> VCCSENSE<40> VSSSENSE<40> +VCCP +VCC_CORE +VCCP V_CPU_GTLREF V_CPU_GTLREF +1.5VS +VCC_CORE +VCC_CORE Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date LA-3491P 0.5 Yonah CPU in mFCPGA479 547Tuesday, March 20, 2007 2006/10/26 2006/07/26 Compal Electronics, Inc. Resistor placed within 0.5" of CPU pin.Trace should be at least 25 mils away from any other toggling signal. Close to CPU pin AD26 within 500mils. CPU_BSEL CPU_BSEL2 CPU_BSEL1 133 166 00 0 1 CPU_BSEL0 1 1 Length match within 25 mils The trace width 18 mils space 7 mils Close to CPU pin within 500mils. POWER, GROUNG, RESERVED SIGNALS AND NC YONAH JP1B FOX_PZ47903-2741-42_YONAH CONN@ PSI# AE6 GTLREF AD26 VCCSENSE AF7 VCCA B26 VCC AB20 VCC AA20 VCC AF20 VCC AE20 VCC AB18 VCC AB17 VCC AA18 VCC AA17 VCC AD18 VCC AD17 VCC AC18 VCC AC17 VCC AF18 VCC AF17 RSVD T22 RSVD V3 RSVD B2 RSVD C3 VSS AB26 VSS AA25 VSS AD25 VSS AE26 VSS AB23 VSS AC24 VSS AF24 VSS AE23 VSS AA22 VSS AD22 VSS AC21 VSS AF21 VSS AB19 VSS AA19 VSS AD19 VSS AC19 VSS AF19 VSS AE19 VSS AB16 VSS AA16 VSS AD16 VSS AC16 VSS AF16 VSS AE16 VSS AB13 VSS AA14 VSS AD13 VSS AC14 VSS AF13 VSS AE14 VSS AB11 VSS AA11 VSS AD11 VSS AC11 VSS AF11 VSS AE11 VSS AB8 VSS AA8 VSS AD8 VSS AC8 VSS AF8 VSS AE8 VSS AA5 VSS AD5 VSS AC6 VSS AF6 VSS AB4 VSS AC3 VSS AF3 VSS AE4 VSS AB1 VSS AA2 VSS AD2 VSS AE1 VSS B6 VSS C5 VSS F5 VSS E6 VSS H6 VSS J5 VSS M5 VSS L6 VSS P6 VSS R5 VSS V5 VSS U6 VSS Y6 VSS A4 VSS D4 VSS E3 VSS H3 VSS G4 VSS K4 VSS L3 VSS P3 VSS N4 VSS T4 VSS U3 VSS Y3 VSS W4 VSS D1 VSS C2 VSS F2 VSS G1 RSVD B25 VSSSENSE AE7 VCCP K6 VCCP J6 VCCP M6 VCCP N6 VCCP T6 VCCP R6 VCCP K21 VCCP J21 VCCP M21 VCCP N21 VCCP T21 VCCP R21 VCCP V21 VCCP W21 VCCP V6 VCCP G21 VID0 AD6 VID1 AF5 VID2 AE5 VID3 AF4 VID4 AE3 VID5 AF2 VID6 AE2 BSEL0 B22 BSEL1 B23 BSEL2 C21 COMP0 R26 COMP1 U26 COMP2 U1 COMP3 V1 RSVD C23 RSVD C24 RSVD AA1 RSVD AA4 RSVD AB2 RSVD AA3 RSVD M4 RSVD N5 RSVD T2 RSVD D2 RSVD F6 RSVD D3 RSVD C1 RSVD AF1 RSVD D22 VCC E7 R24 2K_0402_1% 12 R28 54.9_0402_1% 12 C6 0.01U_0402_16V7K 1 2 R25 27.4_0402_1% 12 R21 1K_0402_1% 12 POWER, GROUND YONAH JP1C FOX_PZ47903-2741-42_YONAH CONN@ VCC AE18 VCC AE17 VCC AB15 VCC AA15 VCC AD15 VCC AC15 VCC AF15 VCC AE15 VCC AB14 VCC AA13 VCC AD14 VCC AC13 VCC AF14 VCC AE13 VCC AB12 VCC AA12 VCC AD12 VCC AC12 VCC AF12 VCC AE12 VCC AB10 VCC AB9 VCC AA10 VCC AA9 VCC AD10 VCC AD9 VCC AC10 VCC AC9 VCC AF10 VCC AF9 VCC AE10 VCC AE9 VCC AB7 VCC AA7 VCC AD7 VCC AC7 VCC B20 VCC A20 VCC F20 VCC E20 VCC B18 VCC B17 VCC A18 VCC A17 VCC D18 VCC D17 VCC C18 VCC C17 VCC F18 VCC F17 VCC E18 VCC E17 VCC B15 VCC A15 VCC D15 VCC C15 VCC F15 VCC E15 VSS K1 VSS J2 VSS M2 VSS N1 VSS T1 VSS R2 VSS V2 VSS W1 VSS A26 VSS D26 VSS C25 VSS F25 VSS B24 VSS A23 VSS D23 VSS E24 VSS B21 VSS C22 VSS F22 VSS E21 VSS B19 VSS A19 VSS D19 VSS C19 VSS F19 VSS E19 VSS B16 VSS A16 VSS D16 VSS C16 VSS F16 VSS E16 VSS B13 VSS A14 VSS D13 VSS C14 VSS F13 VSS E14 VSS B11 VSS A11 VSS D11 VSS C11 VSS F11 VSS E11 VSS B8 VSS A8 VSS D8 VSS C8 VSS F8 VSS E8 VSS G26 VSS K26 VSS J25 VSS M25 VSS N26 VSS T26 VSS R25 VSS V25 VSS W26 VSS H24 VSS G23 VSS K23 VSS L24 VSS P24 VSS N23 VSS T23 VSS U24 VSS Y24 VSS W23 VSS H21 VSS J22 VSS M22 VSS L21 VSS P21 VSS R22 VSS V22 VSS U21 VSS Y21 VCC B14 VCC A13 VCC D14 VCC C13 VCC F14 VCC E13 VCC B12 VCC A12 VCC D12 VCC C12 VCC F12 VCC E12 VCC B10 VCC B9 VCC A10 VCC A9 VCC D10 VCC D9 VCC C10 VCC C9 VCC F10 VCC F9 VCC E10 VCC E9 VCC B7 VCC F7 VCC A7 R27 27.4_0402_1% 12 R23 100_0402_1% 1 2 R26 54.9_0402_1% 12 C7 10U_0805_10V4Z 1 2 R22 100_0402_1% 1 2 5 5 4 4 3 3 2 2 1 1 D D C C B B A A +VCCP +VCC_CORE +VCC_CORE +VCC_CORE +VCC_CORE +VCC_CORE Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date LA-3491P 0.5 CPU Bypass capacitors 647Tuesday, March 20, 2007 2006/10/26 2006/07/26 Compal Electronics, Inc. Mid Frequence Decoupling ESR <= 1.5m ohm Capacitor > 1980uF Place these capacitors on L8 (North side,Secondary Layer) Place these capacitors on L8 (Sorth side,Secondary Layer) Place these capacitors on L8 (Sorth side,Secondary Layer) Place these capacitors on L8 (North side,Secondary Layer) 02/26 Change C43 C44 C45 to 、、 1.9mm height for PV build short term solution C19 10U_0805_6.3V6M 1 2 + C42 330U_D2E_2.5VM_R7 1 2 C32 10U_0805_6.3V6M 1 2 C24 10U_0805_6.3V6M 1 2 C27 10U_0805_6.3V6M 1 2 C8 10U_0805_6.3V6M 1 2 C22 10U_0805_6.3V6M 1 2 C26 10U_0805_6.3V6M 1 2 C16 10U_0805_6.3V6M 1 2 + C40 330U_D2E_2.5VM_R7 1 2 C52 0.1U_0402_10V6K 1 2 C11 10U_0805_6.3V6M 1 2 C49 0.1U_0402_10V6K 1 2 C35 10U_0805_6.3V6M 1 2 C9 10U_0805_6.3V6M 1 2 + C47 330U_D2E_2.5VM_R9 1 2 C18 10U_0805_6.3V6M 1 2 C36 10U_0805_6.3V6M 1 2 C10 10U_0805_6.3V6M 1 2 C30 10U_0805_6.3V6M 1 2 C51 0.1U_0402_10V6K 1 2 C17 10U_0805_6.3V6M 1 2 C23 10U_0805_6.3V6M 1 2 C14 10U_0805_6.3V6M 1 2 C53 0.1U_0402_10V6K 1 2 C39 10U_0805_6.3V6M 1 2 C33 10U_0805_6.3V6M 1 2 C20 10U_0805_6.3V6M 1 2 + C45 330U_D2E_2.5VM_R7 1 2 C50 0.1U_0402_10V6K 1 2 + C41 330U_D2E_2.5VM_R7@ 1 2 C29 10U_0805_6.3V6M 1 2 C15 10U_0805_6.3V6M 1 2 C38 10U_0805_6.3V6M 1 2 C34 10U_0805_6.3V6M 1 2 C13 10U_0805_6.3V6M 1 2 + C44 330U_D2E_2.5VM_R7 1 2 + C43 330U_D2E_2.5VM_R7 1 2 C31 10U_0805_6.3V6M 1 2 C12 10U_0805_6.3V6M 1 2 C37 10U_0805_6.3V6M 1 2 C25 10U_0805_6.3V6M 1 2 C28 10U_0805_6.3V6M 1 2 C21 10U_0805_6.3V6M 1 2 C48 0.1U_0402_10V6K 1 2 5 5 4 4 3 3 2 2 1 1 D D C C B B A A H_SWNG0 H_VREF DDR_THERM# V_DDR_MCH_REF M_OCDOCMP1 PM_EXTTS#1 H_RS#0 H_ADSTB#1 H_SWNG1 H_XRCOMP CFG3 DMI_TXP1 H_REQ#0 CFG7 CFG5 DDR_CKE0_DIMMA M_CLK_DDR3 DMI_RXN2 H_HIT# H_DSTBP#0 H_REQ#4 H_SWNG0 CFG15 DDR_CKE1_DIMMA M_OCDOCMP0 DMI_TXN1 DMI_TXN0 H_BNR# H_REQ#2 M_ODT1 DMI_TXP2 H_DSTBP#2 CLK_MCH_3GPLL CFG13 M_CLK_DDR#0 DMI_RXP2 H_REQ#3 CFG9 H_DINV#2 CLK_MCH_BCLK# H_REQ#1 H_YSCOMP MCH_CLKSEL0 DDR_CKE3_DIMMB H_BPRI# H_DINV#0 CFG18 CFG4 M_CLK_DDR#1 DMI_RXP1 DMI_RXP0 DMI_TXP0 H_CPUSLP# H_DPWR# H_ADS# H_DSTBP#3 H_DSTBN#3 CFG16 DMI_RXN1 M_OCDOCMP0 CLK_MCH_BCLK PLTRST_R# CFG19 CFG12 DDR_CS1_DIMMA# SMRCOMPN H_DSTBP#1 H_DINV#3 H_RS#2 H_ADSTB#0 CFG17 CFG8 CFG6 DDR_CKE2_DIMMB DMI_RXN0 H_LOCK# H_RESET# M_ODT3 M_OCDOCMP1 M_CLK_DDR#2 DMI_TXP3 DMI_TXN3 H_DBSY# H_BR0# H_DSTBN#1 H_DSTBN#0 CFG20 V_DDR_MCH_REF H_DSTBN#2 H_RS#1 H_XSCOMP CFG10 MCH_CLKSEL2 DDR_CS0_DIMMA# SMRCOMPP M_CLK_DDR#3 CFG11 DDR_CS3_DIMMB# DMI_RXN3 H_HITM# H_DRDY# DDR_CS2_DIMMB# M_ODT2 M_ODT0 H_DEFER# H_TRDY# H_DINV#1 H_THERMTRIP# CFG14 M_CLK_DDR2 M_CLK_DDR1 M_CLK_DDR0 H_VREF H_YRCOMP DMI_TXN2 DMI_RXP3 PM_EXTTS#1 MCH_CLKSEL1 H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#11 H_D#13 H_D#9 H_D#14 H_D#8 H_D#15 H_D#12 H_D#10 H_D#19 H_D#21 H_D#17 H_D#22 H_D#16 H_D#23 H_D#20 H_D#18 H_D#27 H_D#29 H_D#25 H_D#30 H_D#24 H_D#31 H_D#28 H_D#26 H_D#35 H_D#37 H_D#33 H_D#38 H_D#32 H_D#39 H_D#36 H_D#34 H_D#43 H_D#45 H_D#41 H_D#46 H_D#40 H_D#47 H_D#44 H_D#42 H_D#51 H_D#53 H_D#49 H_D#54 H_D#48 H_D#52 H_D#50 H_D#55 H_D#59 H_D#61 H_D#57 H_D#62 H_D#56 H_D#63 H_D#60 H_D#58 H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#11 H_A#8 H_A#10 H_A#12 H_A#9 H_A#13 H_A#15 H_A#17 H_A#14 H_A#21 H_A#18 H_A#20 H_A#22 H_A#19 H_A#26 H_A#23 H_A#25 H_A#27 H_A#24 H_A#31 H_A#28 H_A#30 H_A#29 H_A#16 CLK_MCH_REF# CLK_MCH_REF MCH_SSCDREFCLK# MCH_SSCDREFCLK GMCH_H32 PWROK PWROK CLKREQC#GMCH_H32 PM_BMBUSY# DDR_THERM# H_SWNG1 CLK_MCH_3GPLL# H_D#[0 63]<4> H_A#[3 31] <4> H_REQ#[0 4] <4> H_ADSTB#1 <4> H_ADSTB#0 <4> CLK_MCH_BCLK# <15> CLK_MCH_BCLK <15> H_DSTBN#[0 3] <4> H_DSTBP#[0 3] <4> H_DINV#0 <4> H_DINV#1 <4> H_DINV#2 <4> H_DINV#3 <4> H_RESET# <4> H_ADS# <4> H_TRDY# <4> H_DPWR# <4> H_DRDY# <4> H_DEFER# <4> H_BR0# <4> H_BNR# <4> H_BPRI# <4> H_DBSY# <4> H_CPUSLP# <4> H_HITM# <4> H_HIT# <4> H_LOCK# <4> H_RS#[0 2] <4> DMI_TXN0<20> DMI_TXN1<20> DMI_TXN2<20> DMI_TXN3<20> DMI_TXP0<20> DMI_TXP1<20> DMI_TXP2<20> DMI_TXP3<20> DMI_RXN0<20> DMI_RXN1<20> DMI_RXN2<20> DMI_RXN3<20> DMI_RXP0<20> DMI_RXP1<20> DMI_RXP2<20> DMI_RXP3<20> M_CLK_DDR0<13> M_CLK_DDR1<13> M_CLK_DDR2<14> M_CLK_DDR3<14> M_CLK_DDR#0<13> M_CLK_DDR#1<13> M_CLK_DDR#2<14> M_CLK_DDR#3<14> DDR_CS0_DIMMA#<13> DDR_CS1_DIMMA#<13> DDR_CS2_DIMMB#<14> DDR_CS3_DIMMB#<14> DDR_CKE0_DIMMA<13> DDR_CKE1_DIMMA<13> DDR_CKE2_DIMMB<14> DDR_CKE3_DIMMB<14> M_ODT0<13> M_ODT1<13> M_ODT2<14> M_ODT3<14> PM_BMBUSY#<20> H_THERMTRIP#<4,19> PLT_RST#<18,20,22,24,25,30,31> MCH_ICH_SYNC#<18> V_DDR_MCH_REF<13,14> MCH_CLKSEL0 <15> CFG5 <11> CFG7 <11> CFG9 <11> CFG11 <11> CFG12 <11> CFG13 <11> MCH_CLKSEL2 <15> MCH_CLKSEL1 <15> CFG16 <11> CFG18 <11> CFG19 <11> CFG20 <11> CLK_MCH_3GPLL <15> VGATE_INTEL<20,40> PM_POK<20,30> DPRSLPVR<20,40> CLKREQC# <15> CLK_MCH_REF# <15> CLK_MCH_REF <15> MCH_SSCDREFCLK# <15> MCH_SSCDREFCLK <15> DDR_THERM#<13,14> CLK_MCH_3GPLL# <15> +VCCP +VCCP+VCCP +VCCP +3VS +1.8V +1.8V Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date LA-3491P 0.5 Calistoga (1/6) 747Tuesday, March 20, 2007 2006/10/26 2006/07/26 Compal Electronics, Inc. Layout Note: H_XRCOMP / H_YRCOMP / H_VREF / H_SWNG0 / H_SWNG1 trace width and spacing is 18/20. Layout Note: Route as short as possible Description at page11. Stuff R42 & R43 for A1 Calistoga Layout Note: V_DDR_MCH_REF trace width and spacing is 20/20. H_XSCOMP/H_YSCOMP trace width and spacing is 5/20. T5 PAD R33 0_0402_5% 1 2 R32 54.9_0402_1% 12 R48 100_0402_1% 12 R39 10K_0402_5% 12 R42 40.2_0402_1% @ 12 C54 0.1U_0402_16V4Z 1 2 R51 200_0402_1% 12 R41 100_0402_1% 12 R34 100_0402_1% 12 DMI DDR MUXING CFG PM CLKNC RESERVED U3B CALISTOGA_FCBGA1466~D DMIRXN0 AE35 DMIRXN1 AF39 DMIRXN2 AG35 DMIRXN3 AH39 DMIRXP0 AC35 DMIRXP1 AE39 DMIRXP2 AF35 DMIRXP3 AG39 DMITXN0 AE37 DMITXN1 AF41 DMITXN2 AG37 DMITXN3 AH41 DMITXP0 AC37 DMITXP1 AE41 DMITXP2 AF37 DMITXP3 AG41 SM_CK0 AY35 SM_CK1 AR1 SM_CK2 AW7 SM_CK3 AW40 SM_CK0# AW35 SM_CK1# AT1 SM_CK2# AY7 SM_CK3# AY40 SM_OCDCOMP0 AL20 SM_OCDCOMP1 AF10 SM_ODT0 BA13 SM_ODT1 BA12 SM_ODT2 AY20 SM_ODT3 AU21 SM_RCOMPN AV9 SM_RCOMPP AT9 SM_VREF0 AK1 SM_VREF1 AK41 SM_CKE0 AU20 SM_CKE1 AT20 SM_CKE2 BA29 SM_CKE3 AY29 SM_CS0# AW13 SM_CS1# AW12 SM_CS2# AY21 SM_CS3# AW21 CFG16 G18 CFG1 K18 CFG2 J18 CFG3 F18 CFG4 E15 CFG5 F15 CFG6 E18 CFG7 D19 CFG8 D16 CFG9 G16 CFG10 E16 CFG11 D15 CFG12 G15 CFG13 K15 CFG14 C15 CFG15 H16 CFG0 K16 CFG17 H15 CFG18 J25 CFG19 K27 CFG20 J26 G_CLKP AG33 G_CLKN AF33 D_REF_CLKN A27 D_REF_CLKP A26 D_REF_SSCLKN C40 D_REF_SSCLKP D41 NC0 A3 NC1 A39 NC2 A4 NC3 A40 NC4 AW1 NC5 AW41 NC6 AY1 NC7 BA1 NC8 BA2 NC9 BA3 NC10 BA39 NC11 BA40 NC12 BA41 NC13 C1 NC14 AY41 NC15 B2 NC16 B41 NC17 C41 NC18 D1 PM_BMBUSY# G28 PM_EXTTS0# F25 PM_EXTTS1# H26 PM_THERMTRIP# G6 PWROK AH33 RSTIN# AH34 RESERVED1 T32 RESERVED2 R32 RESERVED3 F3 RESERVED4 F7 RESERVED5 AG11 RESERVED6 AF11 RESERVED7 H7 RESERVED8 J19 RESERVED9 A41 RESERVED10 A34 RESERVED11 D28 RESERVED12 D27 RESERVED13 A35 ICH_SYNC# K28 CLK_REQ# H32 C55 0.1U_0402_16V4Z 1 2 R31 54.9_0402_1% 12 R40 10K_0402_5%@ 12 R37 24.9_0402_1% 12 T4 PAD T3 PAD R49 100_0402_1% 12 R50 100_0402_1% 12 R36 0_0402_5% 1 2 R46 221_0603_1% 12 C57 0.1U_0402_16V4Z 1 2 R45 100_0402_1% 12 T7 PAD C56 0.1U_0402_16V4Z 1 2 R43 40.2_0402_1% @ 12 T1 PAD R29 80.6_0402_1% 1 2 R30 80.6_0402_1% 1 2 R38 24.9_0402_1% 12 T2 PAD R35 0_0402_5%@ 1 2 R47 221_0603_1% 12 T8 PAD R44 0_0402_5% 1 2 HOST U3A CALISTOGA_FCBGA1466~D HD0# F1 HD1# J1 HD2# H1 HD3# J6 HD4# H3 HD5# K2 HD6# G1 HD7# G2 HD8# K9 HD9# K1 HD10# K7 HD11# J8 HD12# H4 HD13# J3 HD14# K11 HD15# G4 HD16# T10 HD17# W11 HD18# T3 HD19# U7 HD20# U9 HD21# U11 HD22# T11 HD23# W9 HD24# T1 HD25# T8 HD26# T4 HD27# W7 HD28# U5 HD29# T9 HD30# W6 HD31# T5 HD32# AB7 HD33# AA9 HD34# W4 HD35# W3 HD36# Y3 HD37# Y7 HD38# W5 HD39# Y10 HD40# AB8 HD41# W2 HD42# AA4 HD43# AA7 HD44# AA2 HD45# AA6 HD46# AA10 HD47# Y8 HD48# AA1 HD49# AB4 HD50# AC9 HD51# AB11 HD52# AC11 HD53# AB3 HD54# AC2 HD55# AD1 HD56# AD9 HD57# AC1 HD58# AD7 HD59# AC6 HD60# AB5 HD61# AD10 HD62# AD4 HD63# AC8 HVREF1 K13 HXRCOMP E1 HXSCOMP E2 HYRCOMP Y1 HYSCOMP U1 HXSWING E4 HYSWING W1 HA3# H9 HA4# C9 HA5# E11 HA6# G11 HA7# F11 HA8# G12 HA9# F9 HA10# H11 HA11# J12 HA12# G14 HA13# D9 HA14# J14 HA15# H13 HA16# J15 HA17# F14 HA18# D12 HA19# A11 HA20# C11 HA21# A12 HA22# A13 HA23# E13 HA24# G13 HA25# F12 HA26# B12 HA27# B14 HA28# C12 HA29# A14 HA30# C14 HA31# D14 HREQ#0 D8 HREQ#1 G8 HREQ#2 B8 HREQ#3 F8 HREQ#4 A8 HADSTB#0 B9 HADSTB#1 C13 HRS0# B4 HRS1# E6 HRS2# D6 HCLKN AG1 HCLKP AG2 HDINV#0 J7 HDINV#1 W8 HDINV#2 U3 HDINV#3 AB10 HDSTBN#0 K4 HDSTBN#1 T7 HDSTBN#2 Y5 HDSTBN#3 AC4 HDSTBP#0 K3 HDSTBP#1 T6 HDSTBP#2 AA5 HDSTBP#3 AC5 HCPURST# B7 HADS# E8 HTRDY# E7 HDPWR# J9 HDRDY# H8 HDEFER# C3 HHITM# D4 HHIT# D3 HLOCK# B3 HBREQ0# C7 HBNR# C6 HBPRI# F6 HDBSY# A7 HCPUSLP# E3 HVREF0 J13 T6 PAD 5 5 4 4 3 3 2 2 1 1 D D C C B B A A DDR_B_D11 DDR_B_D57 DDR_B_D46 DDR_B_D7 DDR_B_D0 DDR_B_D44 DDR_B_D40 DDR_B_D30 DDR_B_D27 DDR_B_D15 DDR_B_D3 DDR_B_D35 DDR_B_D25 DDR_B_D23 DDR_B_D49 DDR_B_D37 DDR_B_D19 DDR_B_D48 DDR_B_D47 DDR_B_D36 DDR_B_D18 DDR_B_D8 DDR_B_D62 DDR_B_D60 DDR_B_D9 DDR_B_D2 DDR_B_D52 DDR_B_D50 DDR_B_D22 DDR_B_D56 DDR_B_D51 DDR_B_D39 DDR_B_D28 DDR_B_D17 DDR_B_D45 DDR_B_D6 DDR_B_D61 DDR_B_D58 DDR_B_D1 DDR_B_D54 DDR_B_D41 DDR_B_D31 DDR_B_D12 DDR_B_D5 DDR_B_D38 DDR_B_D32 DDR_B_D20 DDR_B_D16 DDR_B_D14 DDR_B_D33 DDR_B_D63 DDR_B_D59 DDR_B_D42 DDR_B_D55 DDR_B_D53 DDR_B_D43 DDR_B_D29 DDR_B_D26 DDR_B_D13 DDR_B_D4 DDR_B_BS#2 DDR_B_D34 DDR_B_D24 DDR_B_D21 DDR_B_D10 DDR_B_WE# DDR_B_RAS# DDR_A_D35 DDR_A_D15 DDR_A_D14 DDR_A_D21 DDR_A_BS#2 DDR_A_D28 DDR_A_D11 DDR_A_D7 DDR_A_WE# DDR_A_D31 DDR_A_D16 DDR_A_D59 DDR_A_D56 DDR_A_D42 DDR_A_D25 DDR_A_D9 DDR_A_D60 DDR_A_D55 DDR_A_D13 DDR_A_D0 DDR_A_D62 DDR_A_D3 DDR_A_D1 DDR_A_D41 DDR_A_D20 DDR_A_D43 DDR_A_D24 DDR_A_CAS# DDR_A_D54 DDR_A_D52 DDR_A_D33 DDR_A_D12 DDR_A_D19 DDR_A_D46 DDR_A_D23 DDR_A_D18 DDR_A_D63 DDR_A_D34 DDR_A_D26 DDR_A_D22 SA_RCVENIN# SA_RCVENOUT# SB_RCVENIN# SB_RCVENOUT# DDR_A_D27 DDR_A_D2 DDR_A_D32 DDR_A_D6 DDR_A_D49 DDR_A_D47 DDR_A_D58 DDR_A_D40 DDR_A_D36 DDR_A_D5 DDR_A_D48 DDR_A_D10 DDR_A_D8 DDR_A_D57 DDR_A_D39 DDR_A_D37 DDR_A_D30 DDR_A_D4 DDR_A_D45 DDR_A_D53 DDR_A_D51 DDR_A_D17 DDR_A_D38 DDR_A_D29 DDR_A_D44 DDR_A_D50 DDR_A_D61 DDR_A_DQS6 DDR_B_DQS7 DDR_B_MA9 DDR_A_MA13 DDR_A_MA7 DDR_A_DM1 DDR_A_MA5 DDR_A_DM7 DDR_B_MA0 DDR_A_DQS7 DDR_A_DM5 DDR_B_MA7 DDR_B_DQS#1 DDR_B_DQS0 DDR_B_DM3 DDR_B_DQS1 DDR_B_DM1 DDR_A_BS#0 DDR_A_DQS#6 DDR_B_DQS5 DDR_B_DM0 DDR_A_MA4 DDR_A_MA8 DDR_A_DQS#7 DDR_A_MA10 DDR_A_DQS5 DDR_A_DM2 DDR_A_DQS0 DDR_B_MA2 DDR_B_MA13 DDR_B_DM5 DDR_B_DQS#5 DDR_B_DQS#7 DDR_B_BS#1 DDR_A_DQS#1 DDR_A_MA2 DDR_B_MA4 DDR_A_DQS#5 DDR_B_DM6 DDR_B_DQS4 DDR_A_DQS1 DDR_A_MA9 DDR_A_DQS4 DDR_A_DM0 DDR_A_MA0 DDR_B_MA5 DDR_A_DM4 DDR_A_DQS#2 DDR_A_DQS3 DDR_B_MA3 DDR_A_MA11 DDR_B_MA11 DDR_B_BS#0 DDR_A_DM6 DDR_B_MA6DDR_A_MA6 DDR_B_DQS#4 DDR_B_DQS3 DDR_B_DQS#3 DDR_A_DQS#0 DDR_A_DM3 DDR_A_MA3 DDR_A_MA12 DDR_B_MA8 DDR_A_DQS2 DDR_B_DQS#0 DDR_B_MA10 DDR_B_DM7 DDR_A_MA1 DDR_B_MA12 DDR_B_DQS#2 DDR_B_DM4 DDR_B_DQS#6 DDR_B_MA1 DDR_B_DQS2 DDR_B_DQS6 DDR_B_DM2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_RAS# DDR_B_CAS# DDR_A_BS#1 DDR_A_BS#0<13> DDR_A_BS#1<13> DDR_A_BS#2<13> DDR_A_DM[0 7]<13> DDR_A_DQS[0 7]<13> DDR_A_DQS#[0 7]<13> DDR_A_MA[0 13]<13> DDR_A_CAS#<13> DDR_A_RAS#<13> DDR_A_WE#<13> DDR_B_BS#0<14> DDR_B_BS#1<14> DDR_B_BS#2<14> DDR_B_DM[0 7]<14> DDR_B_DQS[0 7]<14> DDR_B_DQS#[0 7]<14> DDR_B_MA[0 13]<14> DDR_B_CAS#<14> DDR_B_RAS#<14> DDR_B_WE#<14> DDR_A_D[0 63] <13> DDR_B_D[0 63] <14> Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date LA-3491P 0.5 Calistoga (2/6) 847Tuesday, March 20, 2007 2006/10/26 2006/07/26 Compal Electronics, Inc. DDR SYS MEMORY A U3D CALISTOGA_FCBGA1466~D SA_DQ0 AJ35 SA_DQ1 AJ34 SA_DQ2 AM31 SA_DQ3 AM33 SA_DQ4 AJ36 SA_DQ5 AK35 SA_DQ6 AJ32 SA_DQ7 AH31 SA_DQ8 AN35 SA_DQ9 AP33 SA_DQ10 AR31 SA_DQ11 AP31 SA_DQ12 AN38 SA_DQ13 AM36 SA_DQ14 AM34 SA_DQ15 AN33 SA_DQ16 AK26 SA_DQ17 AL27 SA_DQ18 AM26 SA_DQ19 AN24 SA_DQ20 AK28 SA_DQ21 AL28 SA_DQ22 AM24 SA_DQ23 AP26 SA_DQ24 AP23 SA_DQ25 AL22 SA_DQ26 AP21 SA_DQ27 AN20 SA_DQ28 AL23 SA_DQ29 AP24 SA_DQ30 AP20 SA_DQ31 AT21 SA_DQ32 AR12 SA_DQ33 AR14 SA_DQ34 AP13 SA_DQ35 AP12 SA_DQ36 AT13 SA_DQ37 AT12 SA_DQ38 AL14 SA_DQ39 AL12 SA_DQ40 AK9 SA_DQ41 AN7 SA_DQ42 AK8 SA_DQ43 AK7 SA_DQ44 AP9 SA_DQ45 AN9 SA_DQ46 AT5 SA_DQ47 AL5 SA_DQ48 AY2 SA_DQ49 AW2 SA_DQ50 AP1 SA_DQ51 AN2 SA_DQ52 AV2 SA_DQ53 AT3 SA_DQ54 AN1 SA_DQ55 AL2 SA_DQ56 AG7 SA_DQ57 AF9 SA_DQ58 AG4 SA_DQ59 AF6 SA_DQ60 AG9 SA_DQ61 AH6 SA_DQ62 AF4 SA_DQ63 AF8 SA_BS0 AU12 SA_BS1 AV14 SA_BS2 BA20 SA_CAS# AY13 SA_RAS# AW14 SA_WE# AY14 SA_RCVENIN# AK23 SA_RCVENOUT# AK24 SA_DM0 AJ33 SA_DM1 AM35 SA_DM2 AL26 SA_DM3 AN22 SA_DM4 AM14 SA_DM5 AL9 SA_DM6 AR3 SA_DM7 AH4 SA_DQS0 AK33 SA_DQS1 AT33 SA_DQS2 AN28 SA_DQS3 AM22 SA_DQS4 AN12 SA_DQS5 AN8 SA_DQS6 AP3 SA_DQS7 AG5 SA_DQS0# AK32 SA_DQS1# AU33 SA_DQS2# AN27 SA_DQS3# AM21 SA_DQS4# AM12 SA_DQS5# AL8 SA_DQS6# AN3 SA_DQS7# AH5 SA_MA0 AY16 SA_MA1 AU14 SA_MA2 AW16 SA_MA3 BA16 SA_MA4 BA17 SA_MA5 AU16 SA_MA6 AV17 SA_MA7 AU17 SA_MA8 AW17 SA_MA9 AT16 SA_MA10 AU13 SA_MA11 AT17 SA_MA12 AV20 SA_MA13 AV12 T10 PAD T12 PADT11 PAD T9 PAD DDR SYS MEMORY B U3E CALISTOGA_FCBGA1466~D SB_DQ0 AK39 SB_DQ1 AJ37 SB_DQ2 AP39 SB_DQ3 AR41 SB_DQ4 AJ38 SB_DQ5 AK38 SB_DQ6 AN41 SB_DQ7 AP41 SB_DQ8 AT40 SB_DQ9 AV41 SB_DQ10 AU38 SB_DQ11 AV38 SB_DQ12 AP38 SB_DQ13 AR40 SB_DQ14 AW38 SB_DQ15 AY38 SB_DQ16 BA38 SB_DQ17 AV36 SB_DQ18 AR36 SB_DQ19 AP36 SB_DQ20 BA36 SB_DQ21 AU36 SB_DQ22 AP35 SB_DQ23 AP34 SB_DQ24 AY33 SB_DQ25 BA33 SB_DQ26 AT31 SB_DQ27 AU29 SB_DQ28 AU31 SB_DQ29 AW31 SB_DQ30 AV29 SB_DQ31 AW29 SB_DQ32 AM19 SB_DQ33 AL19 SB_DQ34 AP14 SB_DQ35 AN14 SB_DQ36 AN17 SB_DQ37 AM16 SB_DQ38 AP15 SB_DQ39 AL15 SB_DQ40 AJ11 SB_DQ41 AH10 SB_DQ42 AJ9 SB_DQ43 AN10 SB_DQ44 AK13 SB_DQ45 AH11 SB_DQ46 AK10 SB_DQ47 AJ8 SB_DQ48 BA10 SB_DQ49 AW10 SB_DQ50 BA4 SB_DQ51 AW4 SB_DQ52 AY10 SB_DQ53 AY9 SB_DQ54 AW5 SB_DQ55 AY5 SB_DQ56 AV4 SB_DQ57 AR5 SB_DQ58 AK4 SB_DQ59 AK3 SB_DQ60 AT4 SB_DQ61 AK5 SB_DQ62 AJ5 SB_DQ63 AJ3 SB_BS0 AT24 SB_BS1 AV23 SB_BS2 AY28 SB_CAS# AR24 SB_RAS# AU23 SB_WE# AR27 SB_RCVENIN# AK16 SB_RCVENOUT# AK18 SB_DM0 AK36 SB_DM1 AR38 SB_DM2 AT36 SB_DM3 BA31 SB_DM4 AL17 SB_DM5 AH8 SB_DM6 BA5 SB_DM7 AN4 SB_DQS0 AM39 SB_DQS1 AT39 SB_DQS2 AU35 SB_DQS3 AR29 SB_DQS4 AR16 SB_DQS5 AR10 SB_DQS6 AR7 SB_DQS7 AN5 SB_DQS0# AM40 SB_DQS1# AU39 SB_DQS2# AT35 SB_DQS3# AP29 SB_DQS4# AP16 SB_DQS5# AT10 SB_DQS6# AT7 SB_DQS7# AP5 SB_MA0 AY23 SB_MA1 AW24 SB_MA2 AY24 SB_MA3 AR28 SB_MA4 AT27 SB_MA5 AT28 SB_MA6 AU27 SB_MA7 AV28 SB_MA8 AV27 SB_MA9 AW27 SB_MA10 AV24 SB_MA11 BA27 SB_MA12 AY27 SB_MA13 AR23 5 5 4 4 3 3 2 2 1 1 D D C C B B A A PEGCOMP VSYNC HSYNC CRT_IREF LIBG ENAVDD LCD_CLK LCD_DAT BKLT_CTL ENABLT LCD_CLK LCD_DAT VSYNCHSYNC LVDSB1+ LVDSB1- LVDSBC+ LVDSBC- LVDSA0+ LVDSA0- LVDSAC- LVDSAC+ LVDSA2- LVDSA2+ LVDSB2+ LVDSB2- LVDSA1- LVDSA1+ LVDSB0+ LVDSB0- ENABLT COMPS LUMA CRMA CRT_SMBCLK<16> CRT_SMBDAT<16> VSYNC<16> HSYNC<16> LCD_CLK<17> LCD_DAT<17> BKLT_CTL<17> ENABLT<17,30> ENAVDD<17> LVDSB1+<17> LVDSB1-<17> LVDSBC-<17> LVDSBC+<17> LVDSA0+<17> LVDSA0-<17> LVDSAC+<17> LVDSAC-<17> LVDSA2-<17> LVDSA2+<17> LVDSB2-<17> LVDSB2+<17> LVDSA1-<17> LVDSA1+<17> LVDSB0-<17> LVDSB0+<17> CRT_GRN<16> CRT_BLU<16> CRT_RED<16> +1.5VS_PCIE +3VS +3VS +1.5VS +1.5VS +1.5VS +1.5VS +1.5VS Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date LA-3491P 0.5 Calistoga (3/6) 947Tuesday, March 20, 2007 2006/10/26 2006/07/26 Compal Electronics, Inc. PEGCOMP trace width and spacing is 18/25 mils. R54 1.5K_0402_1% 12 R53 100K_0402_5% 1 2 D2 PACDN042_SOT23~D@ 2 3 1 R2212 10K_0402_5% 1 2 R2173 0_0402_5% 1 2 R52 24.9_0402_1% 1 2 LVDS TV CRT PCI-EXPRESS GRAPHICS U3C CALISTOGA_FCBGA1466~D SDVOCTRL_CLK H28 SDVOCTRL_DATA H27 LA_DATA0 B37 LA_DATA1 B34 LA_DATA2 A36 LVREFH C33 LVREFL C32 TVDAC_A A16 TVDAC_B C18 TVDAC_C A19 TV_IREF J20 TV_IRTNA B16 TV_IRTNB B18 TV_IRTNC B19 DDCCLK C26 DDCDATA C25 LA_DATA#0 C37 LA_DATA#1 B35 LA_DATA#2 A37 LB_DATA0 F30 LB_DATA1 D29 LB_DATA2 F28 LB_DATA#0 G30 LB_DATA#1 D30 LB_DATA#2 F29 LA_CLK A32 LA_CLK# A33 LB_CLK E26 LB_CLK# E27 LBKLT_CTL D32 LBKLT_EN J30 LCTLA_CLK H30 LCTLB_DATA H29 LDDC_CLK G26 LDDC_DATA G25 LVDD_EN F32 LIBG B38 LVBG C35 VSYNC H23 HSYNC G23 BLUE E23 BLUE# D23 GREEN C22 GREEN# B22 RED A21 RED# B21 CRT_IREF J22 EXP_COMPI D40 EXP_COMPO D38 EXP_RXN0 F34 EXP_RXN1 G38 EXP_RXN2 H34 EXP_RXN3 J38 EXP_RXN4 L34 EXP_RXN5 M38 EXP_RXN6 N34 EXP_RXN7 P38 EXP_RXN8 R34 EXP_RXN9 T38 EXP_RXN10 V34 EXP_RXN11 W38 EXP_RXN12 Y34 EXP_RXN13 AA38 EXP_RXN14 AB34 EXP_RXN15 AC38 EXP_RXP0 D34 EXP_RXP1 F38 EXP_RXP2 G34 EXP_RXP3 H38 EXP_RXP4 J34 EXP_RXP5 L38 EXP_RXP6 M34 EXP_RXP7 N38 EXP_RXP8 P34 EXP_RXP9 R38 EXP_RXP10 T34 EXP_RXP11 V38 EXP_RXP12 W34 EXP_RXP13 Y38 EXP_RXP14 AA34 EXP_RXP15 AB38 EXP_TXN0 F36 EXP_TXN1 G40 EXP_TXN2 H36 EXP_TXN3 J40 EXP_TXN4 L36 EXP_TXN5 M40 EXP_TXN6 N36 EXP_TXN7 P40 EXP_TXN8 R36 EXP_TXN9 T40 EXP_TXN10 V36 EXP_TXN11 W40 EXP_TXN12 Y36 EXP_TXN13 AA40 EXP_TXN14 AB36 EXP_TXN15 AC40 EXP_TXP0 D36 EXP_TXP1 F40 EXP_TXP2 G36 EXP_TXP3 H40 EXP_TXP4 J36 EXP_TXP5 L40 EXP_TXP6 M36 EXP_TXP7 N40 EXP_TXP8 P36 EXP_TXP9 R40 EXP_TXP10 T36 EXP_TXP11 V40 EXP_TXP12 W36 EXP_TXP13 Y40 EXP_TXP14 AA36 EXP_TXP15 AB40 TV_DCONSEL1 J29 TV_DCONSEL0 K30 R2172 0_0402_5% 1 2 R2211 10K_0402_5% 1 2 R58 255_0402_1% 12 R55 10K_0402_5% 12 R57 0_0603_5% 1 2 R2174 0_0402_5% 1 2 R2251 0_0402_5% 1 2 R56 10K_0402_5% 12 5 5 4 4 3 3 2 2 1 1 D D C C B B A A MCH_D2 MCH_A6 MCH_AB1 3GPLL MCH_CRTDAC +1.5VS +1.5VS_PCIE +1.5VS +1.5VS+1.5VS_3GPLL +3VS +1.5VS_MPLL +1.5VS +1.5VS_3GPLL +1.5VS +VCCP +1.5VS_MPLL +1.5VS_HPLL +1.5VS+1.5VS +2.5VS +2.5VS +2.5VS +2.5VS +2.5VS +1.5VS_DPLLB +1.5VS_DPLLA +1.5VS_HPLL +1.5VS_DPLLA +1.5VS_DPLLB +1.5VS+1.5VS +1.5VS_DPLLA +1.5VS_DPLLB +VCCP +2.5VS +3VS +1.5VS +2.5VS +1.5VS +1.5VS +1.5VS Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date LA-3491P 0.5 Calistoga (4/6) 10 47Tuesday, March 20, 2007 2006/10/26 2006/07/26 Compal Electronics, Inc. W=40 mils 45mA Max. 45mA Max. PCI-E/MEM/PSB PLL decoupling Place close to Pin G41 12/28 + C64 220U_D2_2VM_R9 1 2 C66 10U_0805_6.3V6M 1 2 R70 10_0402_5%@ 12 R68 0_0805_5% 12 R65 0_0805_5% 12 R2224 0_0402_5% 12 C85 0.1U_0402_16V4Z 1 2 D4 CH751H-40_SOD323 @ 1 2 C79 10U_0805_6.3V6M 1 2 C93 0.22U_0603_10V7K 1 2 C87 0.1U_0402_16V4Z 1 2 C63 0.1U_0402_16V4Z 1 2 L1 CHB1608U301_0603 12 R60 0_0805_5% 12 C74 2200P_0402_50V7K 1 2 R64 0.5_0805_1% 1 2 C91 0.22U_0603_10V7K 1 2 R2221 0_0402_5% 12 L2 CHB1608U301_0603@ 12 C90 10U_0805_6.3V6M 1 2 R71 10_0402_5%@ 12 C75 0.1U_0402_16V4Z 1 2 + C67 220U_D2_2VM_R9 1 2 + C61 330U_D2E_2.5VM @ 1 2 C80 0.1U_0402_16V4Z @ 1 2 L3 BLM11A601S_0603 1 2 C88 10U_0805_6.3V6M 1 2 R2222 0_0402_5% 12 C59 0.1U_0402_16V4Z 1 2 C84 0.47U_0603_10V7K 1 2 C86 10U_0805_6.3V6M 1 2 C76 4.7U_0805_10V4Z 1 2 C92 0.1U_0402_16V4Z 1 2 + C60 330U_D2E_2.5VM 1 2 R2225 0_0402_5% 12 C94 0.47U_0603_10V7K 1 2 R2223 0_0402_5% 12 C78 0.1U_0402_16V4Z 1 2 C89 0.1U_0402_16V4Z 1 2 C58 0.1U_0402_16V4Z 1 2 R59 0_1206_5% 1 2 C62 0.1U_0402_16V4Z 1 2 C65 10U_0805_6.3V6M 1 2 C77 2.2U_0805_16V4Z 1 2 P O W E R U3H CALISTOGA_FCBGA1466~D VCC_SYNC H22 VCCTX_LVDS0 B30 VCCTX_LVDS1 C30 VCC3G0 AB41 VCC3G1 AJ41 VCC3G2 L41 VCC3G3 N41 VCC3G4 R41 VCC3G5 V41 VCC3G6 Y41 VCCA_3GBG G41 VSSA_3GBG H41 VCCA_3GPLL AC33 VCCTX_LVDS2 A30 VCCA_LVDS A38 VSSA_LVDS B39 VCCA_MPLL AF2 VCCA_TVBG H20 VSSA_TVBG G20 VCCA_TVDACA0 E19 VCCA_TVDACA1 F19 VCCA_TVDACB0 C20 VCCA_TVDACB1 D20 VCCA_TVDACC0 E20 VCCA_TVDACC1 F20 VCCAUX1 AF31 VCCAUX2 AE31 VCCAUX3 AC31 VCCAUX4 AL30 VCCAUX5 AK30 VCCAUX6 AJ30 VCCAUX7 AH30 VCCAUX8 AG30 VCCAUX9 AF30 VCCAUX10 AE30 VCCAUX11 AD30 VCCAUX12 AC30 VCCAUX13 AG29 VCCAUX14 AF29 VCCAUX15 AE29 VCCAUX16 AD29 VCCAUX17 AC29 VCCAUX18 AG28 VCCAUX19 AF28 VCCAUX20 AE28 VTT0 AC14 VTT1 AB14 VTT2 W14 VTT3 V14 VTT4 T14 VTT5 R14 VTT6 P14 VTT7 N14 VTT8 M14 VTT9 L14 VTT10 AD13 VTT11 AC13 VTT12 AB13 VTT13 AA13 VTT14 Y13 VTT15 W13 VTT16 V13 VTT17 U13 VTT18 T13 VTT19 R13 VTT20 N13 VTT21 M13 VTT22 L13 VTT23 AB12 VTT24 AA12 VTT25 Y12 VTT26 W12 VTT27 V12 VTT28 U12 VTT29 T12 VTT30 R12 VTT31 P12 VTT32 N12 VTT33 M12 VTT34 L12 VTT35 R11 VTT36 P11 VTT37 N11 VTT38 M11 VTT39 R10 VTT40 P10 VTT41 N10 VTT42 M10 VTT43 P9 VTT44 N9 VTT45 M9 VTT46 R8 VTT47 P8 VTT48 N8 VTT49 M8 VTT50 P7 VTT51 N7 VTT52 M7 VTT53 R6 VTT54 P6 VTT55 M6 VTT56 A6 VTT57 R5 VTT59 N5 VTT60 M5 VTT61 P4 VTT62 N4 VTT63 M4 VTT64 R3 VTT65 P3 VTT66 N3 VTT67 M3 VTT68 R2 VTT69 P2 VTT70 M2 VTT71 D2 VTT72 AB1 VTT73 R1 VTT74 P1 VTT75 N1 VTT76 M1 VCCA_CRTDAC0 E21 VCCA_CRTDAC1 F21 VSSA_CRTDAC2 G21 VCCA_DPLLA B26 VCCA_DPLLB C39 VCCA_HPLL AF1 VCCD_HMPLL0 AH1 VCCD_HMPLL1 AH2 VCCD_LVDS0 A28 VCCD_LVDS1 B28 VCCD_LVDS2 C28 VCCD_TVDAC D21 VCCDQ_TVDAC H19 VCCHV0 A23 VCCHV1 B23 VCCHV2 B25 VCCAUX21 AH22 VCCAUX22 AJ21 VCCAUX23 AH21 VCCAUX24 AJ20 VCCAUX25 AH20 VCCAUX26 AH19 VCCAUX27 P19 VCCAUX28 P16 VCCAUX29 AH15 VCCAUX30 P15 VCCAUX31 AH14 VCCAUX32 AG14 VCCAUX33 AF14 VCCAUX34 AE14 VCCAUX35 Y14 VCCAUX36 AF13 VCCAUX37 AE13 VCCAUX38 AF12 VCCAUX39 AE12 VCCAUX40 AD12 VCCAUX0 AK31 VTT58 P5 D3 CH751H-40_SOD323 @ 1 2 R67 0_0805_5% 12 [...]... VCCSM_LF5 011 001 1 2 = 667MT/s FSB = 533MT/s FSB CFG5 C98 0.47U_0603_10V7K C97 0.47U_0603_10V7K CFG[2:0] 0 = Reserved 1 = Mobile Yonah CPU*(Default) CFG9 2 0 = DMI x 2 1 = DMI x 4 *(Default) CFG7 1 0 = Lane Reversal Enable * 1 = Normal Operation (Default) 0 = Calistoga D * (Acc ording to Intel Napa Schematic Checklist & CRB Rev1.301 document 2.2Kohm pull-down resistor r e q u e s tReserved 1 = ) CFG11 Place... SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C D Title Compal Electronics, Inc HDD & ODD Size Document Number Rev 0.5 LA-3491P Date: Tuesday, March 20, 2007 Sheet E 22 of 47 4 3 close to U12chip (Intel rule) close to U12chip (Intel rule) 2 2 TDN 2 R260 110_0402_1% 1 R262 110_0402_1% 1 RDN RDN JP11 2 R267 300_0603_5%... THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC 5 4 3 2 Title Compal Electronics, Inc Calistoga (6/6) Size Document Number Rev 0.5 LA-3491P Date: Sheet Tuesday, March 20, 2007 1 12 of 47 5 4 3... THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC 5 V_DDR_MCH_REF R83 10K_0402_5% 2 1 DDR_A_D8 DDR_A_D14 DDR_A_D7 DDR_A_D1 R82 10K_0402_5% 2 1 DDR_A_D2 DDR_A_D3 D 2 4 6 8 10 12 14 16 18 20... THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC 5 M_CLK_DDR3 M_CLK_DDR#3 DDR_B_D14 DDR_B_D15 R85 RP22 56_0404_4P2R_5% RP23 56_0404_4P2R_5% DDR_B_MA4 1 4 4 1 DDR_B_MA2 2 3 3 2 RP24 56_0404_4P2R_5%... 1 T32 C 21 6 1 CPU_BSEL2 1 CLK_MCH_BCLK# 20 SATA1/SRCCLKC4 1 1K_0402_5% CLK_MCH_BCLK *REQ_SEL/PCICLK2 R125 R129 8.2K_0402_5% CLKREF1 2 1 Place near U4 Place these components near each pin within 40 mils CLK_CPU_BCLK# 23 **SEL_LCDCLK#/PCICLK_F1 2 ICH_SMBCLK CLK_MCH_BCLK 2 24_0402_5% CLK_MCH_BCLK# 2 24_0402_5% 2 Vtt_PwrGd#/PD 7 ICH_SMBDATA ICH_SMBDATA 1... C1469 41 0.1U_0402_16V4Z CLK_14M_ICH 1 2 U4 R105 FSB 0.1U_0402_16V4Z 2 Place close to U4 VDDSATA R100 1K_0402_5% CLK_Ra C184 33 1 CLK_Rd 2 2 FSB 2 CPU_BSEL0 0.1U_0402_16V4Z 2 C1457 Place crystal within 500 mils of CK410 2 C185 55 1 C190 @ 0.1U_0402_16V4Z 1 C183 1 VDD48 24 2 C189 @ R97 56_0402_5% 1 2 1 2 C180 2 CK_VDD_48 R89 2.2_0805_1% 1 0.1U_0402_16V4Z 2 C176 CK_VDD_REF 1 CLK_48M_ICH @ 5P_0402_50V8C... THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC 3 2 Title Compal Electronics, Inc Clock generator Size Document Number Rev 0.5 LA-3491P Date: Sheet Tuesday, March 20, 2007 1 15 of 47 A B C D CRT... THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C D Title Compal Electronics, Inc CRT Connector Size Document Number Rev 0.5 LA-3491P Date: Sheet Tuesday, March 20, 2007 E 16 of 47 5 4 LVDS... THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC 5 4 3 2 Title Compal Electronics, Inc LCD CONN Size Document Number Rev 0.5 LA-3491P Date: Sheet Tuesday, March 20, 2007 1 17 of 47 5 4 3 2 1 D . Sheet Custom 147Tuesday, March 20, 2007 2006/10/26 2006/07/26 Compal Electronics, Inc. REV:0.5 Mobile Yonah uFCPGA with Intel Calistoga_GM+ ICH7-M core logic Schematics Document 2007-03-20 Compal confidential A A B B C C D D E E 1. x2 533/667MHz DMI DC/DC Interface CKT. Mobile Yonah/ Merom USB2.0 FSB Clock Generator ICS9LP306BGLFT Power Circuit DC/DC IDE ODD Connector PCI BUS uFCPGA- 478 CPU page 31 DDR2-SO-DIMM X2 page 33 Intel Calistoga MCH page. CPU_BSEL1 133 166 00 0 1 CPU_BSEL0 1 1 Length match within 25 mils The trace width 18 mils space 7 mils Close to CPU pin within 500mils. POWER, GROUNG, RESERVED SIGNALS AND NC YONAH JP1B FOX_PZ47903-2741-42 _YONAH CONN@ PSI# AE6 GTLREF AD26 VCCSENSE AF7 VCCA B26 VCC AB20 VCC AA20 VCC AF20 VCC AE20 VCC AB18 VCC AB17 VCC AA18 VCC AA17 VCC AD18 VCC AD17 VCC AC18 VCC AC17 VCC AF18 VCC AF17 RSVD T22 RSVD V3 RSVD B2 RSVD C3 VSS AB26 VSS AA25 VSS AD25 VSS AE26 VSS AB23 VSS AC24 VSS AF24 VSS AE23 VSS AA22 VSS AD22 VSS AC21 VSS AF21 VSS AB19 VSS AA19 VSS AD19 VSS AC19 VSS AF19 VSS AE19 VSS AB16 VSS AA16 VSS AD16 VSS AC16 VSS AF16 VSS AE16 VSS AB13 VSS AA14 VSS AD13 VSS AC14 VSS AF13 VSS AE14 VSS AB11 VSS AA11 VSS AD11 VSS AC11 VSS AF11 VSS AE11 VSS AB8 VSS AA8 VSS AD8 VSS AC8 VSS AF8 VSS AE8 VSS AA5 VSS AD5 VSS AC6 VSS AF6 VSS AB4 VSS AC3 VSS AF3 VSS AE4 VSS AB1 VSS AA2 VSS AD2 VSS AE1 VSS B6 VSS C5 VSS F5 VSS E6 VSS H6 VSS J5 VSS M5 VSS L6 VSS P6 VSS R5 VSS V5 VSS U6 VSS Y6 VSS A4 VSS D4 VSS E3 VSS H3 VSS G4 VSS K4 VSS L3 VSS P3 VSS N4 VSS T4 VSS U3 VSS Y3 VSS W4 VSS D1 VSS C2 VSS F2 VSS G1 RSVD B25 VSSSENSE AE7 VCCP K6 VCCP J6 VCCP M6 VCCP N6 VCCP T6 VCCP R6 VCCP K21 VCCP J21 VCCP M21 VCCP N21 VCCP T21 VCCP R21 VCCP V21 VCCP W21 VCCP V6 VCCP G21 VID0 AD6 VID1 AF5 VID2 AE5 VID3 AF4 VID4 AE3 VID5 AF2 VID6 AE2 BSEL0 B22 BSEL1 B23 BSEL2 C21 COMP0 R26 COMP1 U26 COMP2 U1 COMP3 V1 RSVD C23 RSVD C24 RSVD AA1 RSVD AA4 RSVD AB2 RSVD AA3 RSVD M4 RSVD N5 RSVD T2 RSVD D2 RSVD F6 RSVD D3 RSVD C1 RSVD AF1 RSVD D22 VCC E7 R24 2K_0402_1%