5 SNIPE Block Diagram Xtal 14.318Mhz 300~400mA 100/133Mhz 100Mhz 100/133Mhz NB clk AMD CPU Mem Ref 1.25V fr S3 VDDA 2.5V S0 SB clk VDD VCC_core S0 VGA clk 200-PIN DDR SODIMM UMA HyperTransport 6.4GB/S 16b/8b ATI VDD 1.8V S0 VDD mem 2.5V S3 AVDD 3.3 S0( CRT/TV) AVDDDI , AVDDQ 1.8V S0 ( CRT/TV) LVDS 1.8V S0 RS480M AGTL+ CPU I/F + UMA Discrete ATI M26/M24 PWR SW TPS2224AP 3.3 S5, 1.8 S5 ACPI 2.0 PCI 6xUSB 2.0 DVI-D 15 RJ11 CONN 29 24 33 30 10/100Mb 2D5V_S3 1D8V_S5 1D2V_S0 ISL6559CR INPUT 33 OUTPUT DCBATOUT B VCC_CORE_S0 SYSTEM POWER 47 LP2951ACM/APL5331KAC-TR HDD DVD/ CD-RW 25 Thermal & Fan G791 23 NS SIO PC87381 SIDE TXFM 45,46 OUTPUT CPU V_CORE 42,43 33 18,19,20,21,22 PIDE 30 5V_S5 , 3D3V_S5 Line Out OP AMP G1421 LPC Bus / 33MHz LPC I/F ATA 133 OUTPUT DCBATOUT Int SPKR PCI LAN Realtek RTL8110SBL 1000/100/10 RTL8100C 100/10 29 44 MAX1999EEI INPUT Line In 33 MIC In 32 31 1000Mb C SYSTEM DC/DC TPS 5130 AC97 TXFM DCBATOUT INPUT CODEC ALC655 24 MODEM MDC Card 30 AD+ BAT+ SYSTEM DC/DC USB x PCI Bus / 33MHz 48 OUTPUTS DCBATOUT 6-CH AC97 2.2 RJ45 INPUTS 4Mx 32 bit x4= 64MB 8Mx 32 bit x4= 128MB 16Mx 32 bit x4= 256MB HY5DS573222F 53,54 28 Mini-PCI 802.11a/b/g 16 SB400 VDD 1.8V S0 26,27 17 MAX1909ETI CRT VRAM x4 ATI VDDQ 3.3V S0 PCMCIA I/F RGB CRT TMDS PCIE 1.8V S0 2* Slot Cardbus 1* 1394 LCD Battery Charger 50,51,52 PCI-Express x2 TI PCI 7421 28 LVDS 11,12,13,14 Xtal 32.768 Khz C TVOUT 16 0.11um, CSP/ BGA 708Pin , 31mmx 31mm 1.0~1.3V CMOS technology PCI Express x16 0.13um, 706 BGA package 31mmx 31mm 1.0~1.2V CMOS technology PLL 1.8V S0 Clock 3.3V S0 SVIDEO/COMP D L1: Signal L2: GND L3: Signal L4: Signal L5: VCC L6: Signal 4,5,6,7 VDD HT 1.2V S0 B PCB Layer Stackup 8,9,10 VDDIO 2.5V S3 Vcore 1.2V S0 1394 Conn DDR x2 DDR 333/400 Sempron / Athlon K8 48Mhz for USB/ Cardbus 28 VDD 2.5V S3 Vref DDR 1.25V S3 VTT 1.25V S3 CPU clk PCMCIA SLOT Support TypeII VLDT 1.2V S0 200Mhz CLK GEN ICS 951412 IDT CV137 D 37 OUTPUT INPUT XBUS KBC KB3910 2D5V_S3 DCBATOUT 34 1D25V_S3 5V_AUX_S5 25 FIR TFDU6102 37 Touch Pad 35 Int KB ISA ROM 35 36 A A Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title BLOCK DIAGRAM hexainf@hotmail.com GRATIS - FOR FREE Size A3 Document Number Rev SA SNIPE Date: Monday, November 22, 2004 Sheet 1 of 56 D SA to SB need to check connect G781 Thermal Alert pin to VGA_GPIO14 ene KBC P165 LPCRST# , we suggest pull low avoid leakage Clk to NB need to add Cap when the trace change layer check page what is the value of R481,R486, R498 and R499 is 100 ohm or 12 ohm check page 15, if on discrete mode does the 1D8V_S0 power for lvds should dummy or still contect on power plan check page 19, can the ohm resistance be dummied on P.19 right hand side? check page 20, R203's voltage on pin page 21 check when the unused USB pin should be pull down or floating Can R471 change to common value? 10 check giga lan and 10/100 connect Does them the same or can chose a cheaper one? 11 page 38 12VGATE_S0 can decreased resistance 12 Does the 1D5V_VGA_S0 can come from TPS5130? D Schematic change: R659, change from 0R2 to 10Kr2 C C B B A A Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title CHANGE HISTORY Size A3 Document Number SNIPE Date: Thursday, November 18, 2004 Rev SA Sheet of 56 A B C D E 3D3V_S0 3D3V_S0 3D3V_CLK_VDD 3D3V_CLK_VDDA 1 SC22U10V6ZY-U C253 SCD1U16V 2 C808 SCD1U16V C252 1 C810 SCD1U16V C807 SCD1U16V 2 C793 SCD1U16V 1 0R3-U 2 L8 1 C794 L24 0R3-U SC22U10V6ZY-U RN5 C811 SCD1U16V RN4 C812 3D3V_S0 SCD1U16V 3D3V_CLK_VDD U28 L22 3D3VDD48_S0 1 C801 SCD1U16V 2 C800 SCD1U16V 3D3V_CLK_VDDA 0R3-U C787 SC2D2U16V5ZY C206 SC33P50V2JN XI_CLK R145 DUMMY-R3 DY X3 39 32 VDD_48 VDDA VDD_SRC 21 14 35 VDD_SRC VDD_SRC VDD_SRC 56 51 43 48 VDD_REF VDD_PC1 VDD_CPU VDD_HTT XIN XOUT USB_48 SCL SDA 27 21 8,21 8,21 X-14D318MHZ-1-U1 XO_CLK SC33P50V2JN R152 CLK48_CARDBUS R151 CLK48_USB R158 SMBC_SB R159 SMBD_SB USB_48M SMBC_CLK SMBD_CLK C227 1 1 2 2 22R2 22R2 0R2-0 0R2-0 10 11 R155 33R2 FS2 FS1 FS0 R162 33R2 CLK_REF2 52 REF2 R161 33R2 CLK_HTT66 47 50 HTT66 PCI0 21 SB_OSC_CLK R146 13 CLK14_NB 33R2 32 CLK14_AUDIO R147 33R2 37 CLK14_SIO 13 HTREF_CLK R170 49D9R2F R182 37 IREF NC#6 SBLINK_CLK# 13 SBLINK_CLK 13 SRN33-2-U2 SBSRC_CLK# 18 SBSRC_CLK 18 33 34 25 24 23 22 19 18 17 16 13 12 CPUC1 CPUT1 CPUC0 CPUT0 40 41 44 45 CPUCLKJ_CY CPUCLK_CY SRCC1 SRCT1 SRCC2 SRCT2 29 30 28 27 ATI_CLK0# ATI_CLK0 ATI_CLK1# ATI_CLK1 VSS_SRC VSS_SRC RESET# TURBO1 36 20 15 26 VSS_CPU VSS_PCI VSS_HTT VSS_SRC VSSA VSS_48 VSS_REF 42 49 46 31 38 55 R171 R172 RN7 RN6 2 15R2J 15R2J 4 SRN33-2-U2 SRN33-2-U2 CPUCLK# CPUCLK NBSRC_CLK# 13 NBSRC_CLK 13 GFX_CLK# 449 GFX_CLK 449 VGA Do not stuff when using UMA IDTCV137PAG 475R2F SEL24/24_48# REF1 REF0 1 IREF_CLKGEN 53 54 SRN33-2-U2 SRC_CLK0# SRC_CLK0 SRC_CLK3# SRC_CLK3 SRCC0 SRCT0 SRCC3 SRCT3 SRCC4 SRCT4 SRCC5 SRCT5 SRCC6 SRCT6 SRCC7 SRCT7 CLKREQ0# CLKREQ1# SBLINK_CLK# R192 49D9R2F SBLINK_CLK R193 49D9R2F SBSRC_CLK# R190 49D9R2F SBSRC_CLK R191 49D9R2F GFX_CLK# R198 49D9R2F GFX_CLK R189 VGA 49D9R2F VGA Do not stuff when using UMA 2 3D3V_CLK_VDD DY R148 1 R153 DY R199 49D9R2F NBSRC_CLK R200 49D9R2F C805 SCD1U16V 1 C803 SCD1U16V NBSRC_CLK# C806 SCD1U16V 2K2R2 FS0 R1492 DUMMY-R2 DY 2K2R2 FS1 R1542 DUMMY-R2 1 C804 SCD1U16V 2 VGA_CORE_S0 DY R169 2K2R2 DY FS2 Wistron Corporation R1602 DUMMY-R2 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C DY Title CLKGEN_IDTCV137 hexainf@hotmail.com GRATIS - FOR FREE A Size A3 Document Number Rev B C D SA SNIPE Date: Thursday, November 18, 2004 Sheet E of 56 A B C D E C82 SCD22U16V3ZY C83 SCD22U16V3ZY C67 SCD22U16V3ZY 2 C81 SCD22U16V3ZY 1D2V_HT0A_S0 4 HTT for CPU sideB Receive power and NB sideA Transmit power HTT for CPU sideA Transmit power and NB sideA Receive power U13A NB0CADOUT15 NB0CADOUTJ15 NB0CADOUT14 NB0CADOUTJ14 NB0CADOUT13 NB0CADOUTJ13 NB0CADOUT12 NB0CADOUTJ12 NB0CADOUT11 NB0CADOUTJ11 NB0CADOUT10 NB0CADOUTJ10 NB0CADOUT9 NB0CADOUTJ9 NB0CADOUT8 NB0CADOUTJ8 NB0CADOUT7 NB0CADOUTJ7 NB0CADOUT6 NB0CADOUTJ6 NB0CADOUT5 NB0CADOUTJ5 NB0CADOUT4 NB0CADOUTJ4 NB0CADOUT3 NB0CADOUTJ3 NB0CADOUT2 NB0CADOUTJ2 NB0CADOUT1 NB0CADOUTJ1 NB0CADOUT0 NB0CADOUTJ0 11 NB0CADOUT[15 0] 11 NB0CADOUTJ[15 0] Used SideB Power Plane 1D2V_HT0A_S0 11 11 11 11 NB0HTTCLKOUT1 NB0HTTCLKOUTJ1 NB0HTTCLKOUT0 NB0HTTCLKOUTJ0 R384 R393 1 49D9R3F 49D9R3F 11 NB0HTTCTLOUT 11 NB0HTTCTLOUTJ T25 R25 U27 U26 V25 U25 W27 W26 AA27 AA26 AB25 AA25 AC27 AC26 AD25 AC25 T27 T28 V29 U29 V27 V28 Y29 W29 AB29 AA29 AB27 AB28 AD29 AC29 AD27 AD28 VLDT0_A VLDT0_A VLDT0_A VLDT0_A VLDT0_A VLDT0_A VLDT0_A L0_CADIN_H15 L0_CADIN_L15 L0_CADIN_H14 L0_CADIN_L14 L0_CADIN_H13 L0_CADIN_L13 L0_CADIN_H12 L0_CADIN_L12 L0_CADIN_H11 L0_CADIN_L11 L0_CADIN_H10 L0_CADIN_L10 L0_CADIN_H9 L0_CADIN_L9 L0_CADIN_H8 L0_CADIN_L8 L0_CADIN_H7 L0_CADIN_L7 L0_CADIN_H6 L0_CADIN_L6 L0_CADIN_H5 L0_CADIN_L5 L0_CADIN_H4 L0_CADIN_L4 L0_CADIN_H3 L0_CADIN_L3 L0_CADIN_H2 L0_CADIN_L2 L0_CADIN_H1 L0_CADIN_L1 L0_CADIN_H0 L0_CADIN_L0 VLDT0_B VLDT0_B VLDT0_B VLDT0_B VLDT0_B VLDT0_B VLDT0_B AH29 AH27 AG28 AG26 AF29 AE28 AF25 LAYOUT: Place bypass cap on topside of board near HTT power pins that are not connected directly to HTT device, but connected internally to other HTT power pins D29 D27 D25 C28 C26 B29 B27 1D2V_HT0B_S0 1D2V_HT0A_S0 L0_CADOUT_H15 L0_CADOUT_L15 L0_CADOUT_H14 L0_CADOUT_L14 L0_CADOUT_H13 L0_CADOUT_L13 L0_CADOUT_H12 L0_CADOUT_L12 L0_CADOUT_H11 L0_CADOUT_L11 L0_CADOUT_H10 L0_CADOUT_L10 L0_CADOUT_H9 L0_CADOUT_L9 L0_CADOUT_H8 L0_CADOUT_L8 L0_CADOUT_H7 L0_CADOUT_L7 L0_CADOUT_H6 L0_CADOUT_L6 L0_CADOUT_H5 L0_CADOUT_L5 L0_CADOUT_H4 L0_CADOUT_L4 L0_CADOUT_H3 L0_CADOUT_L3 L0_CADOUT_H2 L0_CADOUT_L2 L0_CADOUT_H1 L0_CADOUT_L1 L0_CADOUT_H0 L0_CADOUT_L0 N26 N27 L25 M25 L26 L27 J25 K25 G25 H25 G26 G27 E25 F25 E26 E27 N29 P29 M28 M27 L29 M29 K28 K27 H28 H27 G29 H29 F28 F27 E29 F29 CPUCADOUT15 CPUCADOUTJ15 CPUCADOUT14 CPUCADOUTJ14 CPUCADOUT13 CPUCADOUTJ13 CPUCADOUT12 CPUCADOUTJ12 CPUCADOUT11 CPUCADOUTJ11 CPUCADOUT10 CPUCADOUTJ10 CPUCADOUT9 CPUCADOUTJ9 CPUCADOUT8 CPUCADOUTJ8 CPUCADOUT7 CPUCADOUTJ7 CPUCADOUT6 CPUCADOUTJ6 CPUCADOUT5 CPUCADOUTJ5 CPUCADOUT4 CPUCADOUTJ4 CPUCADOUT3 CPUCADOUTJ3 CPUCADOUT2 CPUCADOUTJ2 CPUCADOUT1 CPUCADOUTJ1 CPUCADOUT0 CPUCADOUTJ0 C536 downstream SC4D7U10V5ZY CPUCADOUT[15 0] 11 CPUCADOUTJ[15 0] 11 Used SideA Power Plane NB0HTTCLKOUT1 NB0HTTCLKOUTJ1 NB0HTTCLKOUT0 NB0HTTCLKOUTJ0 Y25 W25 Y27 Y28 L0_CLKIN_H1 L0_CLKIN_L1 L0_CLKIN_H0 L0_CLKIN_L0 L0_CLKOUT_H1 L0_CLKOUT_L1 L0_CLKOUT_H0 L0_CLKOUT_L0 J26 J27 J29 K29 CPUHTTCLKOUT1 CPUHTTCLKOUTJ1 CPUHTTCLKOUT0 CPUHTTCLKOUTJ0 CPUHTTCLKOUT1 CPUHTTCLKOUTJ1 CPUHTTCLKOUT0 CPUHTTCLKOUTJ0 CPUHTTCTLIN1 CPUHTTCTLINJ1 NB0HTTCTLOUT NB0HTTCTLOUTJ R27 R26 T29 R29 L0_CTLIN_H1 L0_CTLIN_L1 L0_CTLIN_H0 L0_CTLIN_L0 L0_CTLOUT_H1 L0_CTLOUT_L1 L0_CTLOUT_H0 L0_CTLOUT_L0 N25 P25 P28 P27 CPUHTTCTLOUT0 CPUHTTCTLOUTJ0 CPUHTTCTLOUT0 11 CPUHTTCTLOUTJ0 11 11 11 11 11 62.10030.041 By ME requset U11 P/N: Main 62.10030.041 Second 62.10053.191 Third 62.10053.201 BGA754-SKT-U Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title CPU(1/4)_HyperTransport I/F Size A3 Document Number Rev A B C D SA SNIPE Date: Thursday, November 18, 2004 Sheet E of 56 A B C D E 1D25V_S3 U13B 2D5V_S3 MEMVREF1 R480 R479 34D8R2F 34D8R2F MEMZN MEMZP D14 C14 MEMZN MEMZP VREF_DDR_MEM M_DATA[63 0] NOTE: Test with passive probes only C330 SCD1U VREF_DDR_MEM C422 SC1000P50V2KX 2 R234 100R3F C329 SCD1U R235 100R3F 2D5V_S3 NOTE: Install to bypass op-amp LAYOUT: Locate close to DIMMs NOTE: Remove to bypass op-amp VREF_DDR_CLAW C671 SCD1U VREF_DDR_CLAW C682 SCD1U R506 100R3 1 R500 100R3 2D5V_S3 C693 SC1000P50V2KX M_ADM[7 0] LAYOUT: Locate close to CPU M_DQS[7 0] hexainf@hotmail.com GRATIS - FOR FREE A D17 A18 B17 C17 AF16 AG16 AH16 AJ17 MEMRESET_L AG10 MEMRESET# AE8 AE7 M_CKE#0 M_CKE#1 M_CKE#0 8,9 M_CKE#1 8,9 D10 C10 E12 E11 AF8 AG8 AF10 AE10 V3 V4 K5 K4 R5 P5 P3 P4 M_CLK7 M_CLK#7 M_CLK6 M_CLK#6 M_CLK5 M_CLK#5 M_CLK4 M_CLK#4 M_CLK7 8,9 M_CLK#7 8,9 M_CLK6 8,9 M_CLK#6 8,9 M_CLK5 8,9 M_CLK#5 8,9 M_CLK4 8,9 M_CLK#4 8,9 MEMCS_L7 MEMCS_L6 MEMCS_L5 MEMCS_L4 MEMCS_L3 MEMCS_L2 MEMCS_L1 MEMCS_L0 D8 C8 E8 E7 D6 E6 C4 E5 M_CS#7 M_CS#6 M_CS#5 M_CS#4 M_CS#3 M_CS#2 M_CS#1 M_CS#0 M_CS#3 M_CS#2 M_CS#1 M_CS#0 MEMRASA_L MEMCASA_L MEMWEA_L H5 D4 G5 M_ARAS# M_ACAS# M_AWE# M_ARAS# 8,9 M_ACAS# 8,9 M_AWE# 8,9 MEMBANKA1 MEMBANKA0 K3 H3 M_ABS#1 M_ABS#0 M_ABS#1 8,9 M_ABS#0 8,9 NC_E13 NC_C12 MEMADDA13 MEMADDA12 MEMADDA11 MEMADDA10 MEMADDA9 MEMADDA8 MEMADDA7 MEMADDA6 MEMADDA5 MEMADDA4 MEMADDA3 MEMADDA2 MEMADDA1 MEMADDA0 E13 C12 E10 AE6 AF3 M5 AE5 AB5 AD3 Y5 AB4 Y3 V5 T5 T3 N5 RSVD_M_AA15 RSVD_M_AA14 M_AA13 M_AA12 M_AA11 M_AA10 M_AA9 M_AA8 M_AA7 M_AA6 M_AA5 M_AA4 M_AA3 M_AA2 M_AA1 M_AA0 MEMRASB_L MEMCASB_L MEMWEB_L H4 F5 F4 M_BRAS# M_BCAS# M_BWE# M_BRAS# 8,9 M_BCAS# 8,9 M_BWE# 8,9 MEMBANKB1 MEMBANKB0 L5 J5 M_BBS#1 M_BBS#0 M_BBS#1 8,9 M_BBS#0 8,9 NC_E14 NC_D12 MEMADDB13 MEMADDB12 MEMADDB11 MEMADDB10 MEMADDB9 MEMADDB8 MEMADDB7 MEMADDB6 MEMADDB5 MEMADDB4 MEMADDB3 MEMADDB2 MEMADDB1 MEMADDB0 E14 D12 E9 AF6 AF4 M4 AD5 AC5 AD4 AA5 AB3 Y4 W5 U5 T4 M3 RSVD_M_BA15 RSVD_M_BA14 M_BA13 M_BA12 M_BA11 M_BA10 M_BA9 M_BA8 M_BA7 M_BA6 M_BA5 M_BA4 M_BA3 M_BA2 M_BA1 M_BA0 MEMCHECK7 MEMCHECK6 MEMCHECK5 MEMCHECK4 MEMCHECK3 MEMCHECK2 MEMCHECK1 MEMCHECK0 N3 N1 U3 V1 N2 P1 U1 U2 MEMCKEA MEMCKEB M_DATA63 M_DATA62 M_DATA61 M_DATA60 M_DATA59 M_DATA58 M_DATA57 M_DATA56 M_DATA55 M_DATA54 M_DATA53 M_DATA52 M_DATA51 M_DATA50 M_DATA49 M_DATA48 M_DATA47 M_DATA46 M_DATA45 M_DATA44 M_DATA43 M_DATA42 M_DATA41 M_DATA40 M_DATA39 M_DATA38 M_DATA37 M_DATA36 M_DATA35 M_DATA34 M_DATA33 M_DATA32 M_DATA31 M_DATA30 M_DATA29 M_DATA28 M_DATA27 M_DATA26 M_DATA25 M_DATA24 M_DATA23 M_DATA22 M_DATA21 M_DATA20 M_DATA19 M_DATA18 M_DATA17 M_DATA16 M_DATA15 M_DATA14 M_DATA13 M_DATA12 M_DATA11 M_DATA10 M_DATA9 M_DATA8 M_DATA7 M_DATA6 M_DATA5 M_DATA4 M_DATA3 M_DATA2 M_DATA1 M_DATA0 A16 B15 A12 B11 A17 A15 C13 A11 A10 B9 C7 A6 C11 A9 A5 B5 C5 A4 E2 E1 A3 B3 E3 F1 G2 G1 L3 L1 G3 J2 L2 M1 W1 W3 AC1 AC3 W2 Y1 AC2 AD1 AE1 AE3 AG3 AJ4 AE2 AF1 AH3 AJ3 AJ5 AJ6 AJ7 AH9 AG5 AH5 AJ9 AJ10 AH11 AJ11 AH15 AJ15 AG11 AJ12 AJ14 AJ16 MEMDATA63 MEMDATA62 MEMDATA61 MEMDATA60 MEMDATA59 MEMDATA58 MEMDATA57 MEMDATA56 MEMDATA55 MEMDATA54 MEMDATA53 MEMDATA52 MEMDATA51 MEMDATA50 MEMDATA49 MEMDATA48 MEMDATA47 MEMDATA46 MEMDATA45 MEMDATA44 MEMDATA43 MEMDATA42 MEMDATA41 MEMDATA40 MEMDATA39 MEMDATA38 MEMDATA37 MEMDATA36 MEMDATA35 MEMDATA34 MEMDATA33 MEMDATA32 MEMDATA31 MEMDATA30 MEMDATA29 MEMDATA28 MEMDATA27 MEMDATA26 MEMDATA25 MEMDATA24 MEMDATA23 MEMDATA22 MEMDATA21 MEMDATA20 MEMDATA19 MEMDATA18 MEMDATA17 MEMDATA16 MEMDATA15 MEMDATA14 MEMDATA13 MEMDATA12 MEMDATA11 MEMDATA10 MEMDATA9 MEMDATA8 MEMDATA7 MEMDATA6 MEMDATA5 MEMDATA4 MEMDATA3 MEMDATA2 MEMDATA1 MEMDATA0 M_ADM8 M_ADM7 M_ADM6 M_ADM5 M_ADM4 M_ADM3 M_ADM2 M_ADM1 M_ADM0 M_DQS8 M_DQS7 M_DQS6 M_DQS5 M_DQS4 M_DQS3 M_DQS2 M_DQS1 M_DQS0 R1 A13 A7 C2 H1 AA1 AG1 AH7 AH13 T1 A14 A8 D1 J1 AB1 AJ2 AJ8 AJ13 MEMDQS17 MEMDQS16 MEMDQS15 MEMDQS14 MEMDQS13 MEMDQS12 MEMDQS11 MEMDQS10 MEMDQS9 MEMDQS8 MEMDQS7 MEMDQS6 MEMDQS5 MEMDQS4 MEMDQS3 MEMDQS2 MEMDQS1 MEMDQS0 MEMCLK_H7 MEMCLK_L7 MEMCLK_H6 MEMCLK_L6 MEMCLK_H5 MEMCLK_L5 MEMCLK_H4 MEMCLK_L4 MEMCLK_H3 MEMCLK_L3 MEMCLK_H2 MEMCLK_L2 MEMCLK_H1 MEMCLK_L1 MEMCLK_H0 MEMCLK_L0 AG12 VREF_DDR_CLAW VTT_A VTT_A VTT_A VTT_A VTT_B VTT_B VTT_B VTT_B C653 SCD1U C114 SC1000P50V2KX VTT_SENSE DDRVTT_SENSE AE13 TP75 For REGISTED DIMM Only UNBUFFER DIMM NC 2D5V_S3 RN72 M_CLK#1 M_CLK#0 M_CLK1 M_CLK0 M_CLK1 M_CLK#1 M_CLK0 M_CLK#0 SRN10K-2 8,9 8,9 8,9 8,9 M_AA[13 0] 8,9 AMD suggested M_AA13 connect to DIMM pin123 M_BA[13 0] 8,9 MEMRESET# M_CS#7 M_CS#6 M_CS#5 M_CS#4 RSVD_M_AA15 RSVD_M_AA14 RSVD_M_BA15 RSVD_M_BA14 TP84 TP82 TP81 TP83 TP87 TP73 TP70 TP72 TP71 CB7 CB6 CB5 CB4 CB3 CB2 CB1 CB0 TP94 TP16 TP95 TP19 TP21 TP22 TP23 TP24 NOT SUPPORT ECC CHECK AMD suggested remove PULL-HI resistor Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title CPU(2/4)_DDR Size A3 Document Number Rev D SA SNIPE Date: Thursday, November 18, 2004 C TP69 TP68 TP18 TP17 AMD suggested M_BA13 connect to DIMM pin123 BGA754-SKT-U B MEMZN MEMZP M_DQS8 M_ADM8 Sheet E of 56 A B C D E 2D5V_CPUA_S0 22D5V_CPUR_S0 2 G913C-U C525 DY SC1U10V3KX C524 SC1U10V3KX U13C SANYO, NT$:6.1 Iripple=1.1A,ESR=70mohm 3.5/2.8/2.0 77.21071.031 CPUCLK differentially impedance 100 41 41 COREFB COREFB# C584 SC3900P50V3KX CPUCLK# 820R3 820R3 C581 SC3900P50V3KX VDDIOFB VDDIOFBJ VDDIOSENSE AE12 AF12 AE11 VDDIOFB_H VDDIOFB_L VDDIO_SENSE CLKIN AJ21 AH21 CLKIN_H CLKIN_L AJ23 AH23 NC_AJ23 NC_AH23 AE24 AF24 NC_AE24 NC_AF24 C16 AG15 VTT_A VTT_B AH17 DBRDY 2D5V_S0 LDT_RST# SB_CPUPWRGDR441 LDT_STP# R440 R408 2D5V_S0 2D5V_S0 Add HDT connector for AMD suggested R89 2D5V_S0 R88 2D5V_S3 R359 680R3 DY CHANGE FROM 1KR3 TO 680R2 FOR AMD CHECK LIST RN70 NC_AG17 NC_AJ18 NC_D18 SRN680-U RN3 NC_B19 NC_C19 NC_D20 NC_C21 SRN680-U 5 11 13 15 17 19 21 23 C15 NC_C15 TMS TCK TRST_L TDI E20 E17 B21 A21 TMS TCK TRST_L TDI 680R3 NC_C18 C18 NC_C18 NC_A19 A19 NC_A19 680R3 A28 AJ28 10 12 14 16 18 20 22 24 26 THERMTRIP# THERMDP 23 THERMDN 23 VID[4 0] VID4 VID3 VID2 VID1 VID0 AG13 AF14 AG14 AF15 AE15 VID4 VID3 VID2 VID1 VID0 NC_AG18 NC_AH18 NC_AG17 NC_AJ18 AG18 AH18 AG17 AJ18 NC_AG18 NC_AH18 NC_AG17 NC_AJ18 41 TP62 TP63 LAYOUT: Route FBCLKOUT_H/L differentially impedance 80 FBCLKOUT_H FBCLKOUT_L AE23 AF23 AF22 AF21 NC_AE23 NC_AF23 NC_AF22 NC_AF21 RN67 C1 J3 R3 AA2 D3 AG2 B18 AH1 AE21 C20 AG4 C6 AG6 AE9 AG9 NC_C1 NC_J3 NC_R3 NC_AA2 NC_D3 NC_AG2 NC_B18 NC_AH1 NC_AE21 NC_C20 NC_AG4 NC_C6 NC_AG6 NC_AE9 NC_AG9 R452 80D6R3F-U AH19 AJ19 FBCLKOUTJ AE19 DBREQJ NC_D20 NC_C21 NC_D18 NC_C19 NC_B19 D20 C21 D18 C19 B19 NC_D20 NC_C21 NC_D18 NC_C19 NC_B19 TDO A22 TDO NC_AF18 R4512 DUMMY-R3 DY AF18 2D5V_S3 Connect to VDDIO for AMD suggest KEY1 KEY0 NC_AE23 NC_AF23 NC_AF22 NC_AF21 SRN680-U DY SMC-CONN26A-FP 20.F0357.025 DY Validation Test Points NC_D22 NC_C22 2D5V_S0 NC_B13 NC_B7 NC_C3 NC_K1 NC_R2 NC_AA3 NC_F3 NC_C23 NC_AG7 NC_AE22 NC_C24 NC_A25 NC_C9 D22 C22 3D3V_S5 R427 680R3 B13 B7 C3 K1 R2 AA3 F3 C23 AG7 AE22 C24 A25 C9 THERMTRIP# R392 10KR2 CPU_THERMTRIP# 21,23 Q26 MMBT3904-U1 NS3 2D5V_S0 R414 1KR3 THERMTRIP#Level shift to SB400 BGA754-SKT-U LAYOUT: Place close to the CPU NC_C15 NC_AE23 NC_AF23 NC_AF22 NC_AF21 TP66 TP51 TP52 TP53 TP54 LDT_RST# CLKIN CLKIN# CORE_SENSE VDDIOFB VDDIOFBJ VDDIOSENSE NC_AE24 NC_AF24 TP60 TP58 TP59 TP56 TP76 TP77 TP74 TP55 TP57 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title CPU(3/4)_Control & Debug Size A3 Document Number Rev B C D SA SNIPE Date: Thursday, November 18, 2004 A FBCLKOUT DY DY R357 680R3 C519 DYSCD1UCN5 A26 A27 DBREQ_L NC_C15 DY 2 DBREQJ DY DBRDY TCK TMS TDI TRST_L TDO R358 680R3 RN66 SRN680-U C518 SCD1U A20 THERMDA THERMDC HDT Connectors DBRDY 2 680R3 680R3 680R3 L0_REF1 L0_REF0 COREFB_H COREFB_L CORE_SENSE CLKIN# NC_AJ23 NC_AH23 NC_AE24 NC_AF24 1D25V_S3 AF27 AE26 A23 A24 B23 R431 169R3F RESET_L PWROK LDTSTOP_L COREFB COREFB# CORE_SENSE 2D5V_S3 R428 1 R415 AF20 AE18 AJ27 THERMTRIP_L AMD suggest voltege from 2D5V_S0 to 2D5V_S3 C534 SC1000P50V2KX C535 SC1000P50V2KX VDDA1 VDDA2 1 L0_REF1 L0_REF0 KEMET,NT:5.7, B2 size ST100U4VBM-1 (80.10716.321) Iripple=1.1A,ESR=70mohm C571 SCD22U16V3ZY13,18 LDT_RST# 18 SB_CPUPWRGD 13,18 LDT_STP# AMD SUGGEST TO USE 2D5V_CPUA_S0 C556 SC3300P50V2KX AH25 AJ25 44D2R3F R389 2 44D2R3F R388 64.44R25.551 C543 SC4D7U10V5ZY 78.47593.411 1D2V_HT0A_S0 TC9 ST100U4VBM-1 LAYOUT: Route VDDA trace approx 50 mils wide (use 2x25 mil traces to exit ball field) and 500 mils long LAYOUT: Route trace 50 mils wide and 500 to 750 mils long between these caps 1 DY 63.R0004.151 2D5V_VDDA_S0 L19 0R5J R382 0R3-U R2 DY Change L270H 2 C544 SC10U10V5ZY 2D5V_CPUA_S0 R361 20KR3F 0R3-U Vout = 1.25*(1+ R1/R2) SET OUT 1 R385 SHDN# GND IN 2D5V_VDDA_VREF R1 2 DY R360 20KR3F C520 SC22P50V2JN-1 Iomax=120mA U51 AMD SUGGEST TO USE 100 ~ 300UH 3D3V_S0 2D5V_S0 2D5V_VDDA_S0 Sheet E of 56 A B C D E U13E hexainf@hotmail.com BGA754-SKT-U GRATIS - FOR FREE A U13D 1 1 1 1 2 2 2 C100 C109 C101 C106 C108 C92 C93 C115 C116 SCD22U16V3ZY SC10U10V5ZY SC10U10V5ZY SCD22U16V3ZY SCD22U16V3ZY SCD22U16V3ZY SC10U10V5ZY SC10U10V5ZY SCD22U16V3ZY SCD22U16V3ZY 2 C107 LAYOUT: Place on backside of processor 1 2 VCC_CORE_S0 DY 0.22u x DY DY DY C607 C634 C608 C636 C600 C635 SCD22U16V3ZY SCD22U16V3ZY SC10U10V5ZY SCD22U16V3ZY SCD22U16V3ZY SC10U10V5ZY 10u x 2D5V_S3 78.47593.411 2 2 10u x 4.7u x 1D25V_S3 1D25V_S3 1 1 C160 C748 C606 C285 C283 C281 C282 SC10U10V5ZY SC4D7U10V5ZY SC4D7U10V5ZY SC4D7U10V5ZY SC4D7U10V5ZY SC4D7U10V5ZY SC4D7U10V5ZY 2 2 1 1 C164 C177 C176 C175 C174 C731 SCD22U16V3ZY SCD22U16V3ZY SCD22U16V3ZY SCD22U16V3ZY SCD22U16V3ZY SCD22U16V3ZY VCC_CORE_S0 2D5V_S3 2 C618 C105 C104 C609 SCD22U16V3ZY SCD22U16V3ZY SC4D7U10V5ZY SC4D7U10V5ZY N28 U28 AA28 AE27 R7 U7 W7 K8 M8 P8 T8 V8 Y8 J9 N9 R9 U9 W9 AA9 H10 K10 M10 P10 T10 Y10 AB10 G11 J11 AA11 AC11 H12 K12 Y12 AB12 J13 AA13 AC13 H14 AB26 E28 J28 10u x 0.22u x VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD LAYOUT: Place in uPGA socket cavity VCC_CORE_S0 E4 G4 J4 L4 N4 U4 W4 AA4 AC4 AE4 D5 AF5 F6 H6 K6 M6 P6 T6 V6 Y6 AB6 AD6 D7 G7 J7 AA7 AC7 AF7 F8 H8 AB8 AD8 D9 G9 AC9 AF9 F10 AD10 D11 AF11 F12 AD12 D13 AF13 F14 AD14 F16 AD16 D15 R4 VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD L7 AC15 H18 B20 E21 H22 J23 H24 F26 N7 L9 V10 G13 K14 Y14 AB14 G15 J15 AA15 H16 K16 Y16 AB16 G17 J17 AA17 AC17 AE17 F18 K18 Y18 AB18 AD18 AG19 E19 G19 AC19 AA19 J19 F20 H20 K20 M20 P20 T20 V20 Y20 AB20 AD20 G21 J21 L21 N21 R21 U21 W21 AA21 AC21 F22 K22 M22 P22 T22 V22 Y22 AB22 AD22 E23 G23 L23 N23 R23 U23 W23 AA23 AC23 B24 D24 F24 K24 M24 P24 T24 V24 Y24 AB24 AD24 AH24 AE25 K26 P26 V26 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 2D5V_S3 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCC_CORE_S0 Y17 K17 H17 F17 E18 AJ26 AE29 AC16 AA16 J16 G16 E16 AH14 AD15 AB15 K15 E15 D16 AE14 AC14 AA14 J14 G14 AF17 AD13 AB13 Y13 K13 H13 F13 AH12 AC12 AA12 G12 B12 AD11 AB11 Y11 K11 H11 F11 AH10 AC10 W10 U10 R10 N10 L10 J10 G10 B10 AD9 Y9 V9 T9 P9 M9 K9 H9 F9 AH8 AC8 W8 U8 R8 N8 L8 J8 G8 B8 AD7 AB7 V7 T7 P7 M7 K7 H7 F7 AH6 AC6 AA6 U6 R6 N6 L6 J6 G6 B6 AH4 B4 AH2 AD2 AB2 Y2 V2 T2 P2 M2 K2 H2 F2 C29 AH28 AF28 AC28 W28 R28 L28 N20 L20 J20 AF19 AD19 AB19 Y19 K19 H19 F19 D19 AC18 AA18 G18 B16 AD17 AB17 H15 F15 G28 D28 B28 C27 AH26 AF26 AD26 Y26 T26 M26 H26 D26 B26 C25 B25 AJ24 AG24 AC24 AA24 W24 U24 R24 N24 J24 G24 E24 AG23 AD23 AB23 Y23 V23 T23 P23 K23 H23 F23 D23 AJ22 AH22 AG22 AC22 AA22 AG29 U22 R22 N22 L22 J22 G22 E22 B22 AG21 AD21 Y21 V21 T21 P21 M21 K21 H21 F21 D21 AJ20 AG20 AE20 AC20 AA20 W20 U20 R20 G20 J18 AE16 Y15 B14 J12 AA10 AB9 AA8 Y7 W6 AF2 D2 AG27 AG25 L24 M23 W22 AB21 AH20 B2 0.22u x 4.7u x BGA754-SKT-U Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title CPU(4/4)_Power Size A3 Document Number Rev B C D SA SNIPE Date: Thursday, November 18, 2004 Sheet E of 56 A B C 13 17 14 18 19 23 29 31 20 24 30 32 41 43 49 53 42 44 50 54 55 59 65 67 56 60 66 68 127 129 135 139 128 130 136 140 141 145 151 153 142 146 152 154 163 165 171 175 164 166 172 176 177 181 187 189 178 182 188 190 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 C304 SCD1U Layout trace 20 mil 3D3V_S0 12 26 48 62 134 148 170 184 78 M_ADM_R0 M_ADM_R1 M_ADM_R2 M_ADM_R3 M_ADM_R4 M_ADM_R5 M_ADM_R6 M_ADM_R7 CK0 /CK0 CK1 /CK1 CK2 /CK2 35 37 160 158 89 91 DDR_CLK0 DDR_CLK#0 SCL SDA 195 193 SMBC_SB SMBD_SB SA0 SA1 SA2 194 196 198 VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD 10 21 22 33 34 36 45 46 57 58 69 70 81 82 92 93 94 113 114 131 132 143 144 155 156 157 167 168 179 180 191 192 15 16 27 28 38 39 40 51 52 63 64 75 76 87 88 90 103 104 125 126 137 138 149 150 159 161 162 173 174 185 186 202 /RAS /CAS /WE 197 199 VREF VREF VDDSPD VDDID 201 GND GND CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 NC NC/(RESET#) NC/A13 NC/BA2 NC NC NC VREF_DDR_MEM DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 DM8 118 120 119 85 DM1_RESET# 86 DM1_A13 97 DM1_BA2 98 M_AA13 123 124 200 5,9 M_ARAS# 5,9 M_ACAS# 5,9 M_AWE# M_DQS_R0 M_DQS_R1 M_DQS_R2 M_DQS_R3 M_DQS_R4 M_DQS_R5 M_DQS_R6 M_DQS_R7 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 71 73 79 83 72 74 80 84 TP111 TP33 TP110 DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS8 11 25 47 61 133 147 169 183 77 M_CKE#0 M_CKE#0 5,9 M_ADM#0 M_ADM#1 M_ADM#2 M_ADM#3 M_ADM#4 M_ADM#5 M_ADM#6 M_ADM#7 M_CLK5 5,9 M_CLK#5 5,9 M_CLK7 5,9 M_CLK#7 5,9 2D5V_S3 NOT SUPPORT ECC CHECK AMD suggested pull-low M_BA0 M_BA1 M_BA2 M_BA3 M_BA4 M_BA6 M_BA5 M_BA7 M_BA8 M_BA9 M_BA10 M_BA11 M_BA12 112 111 110 109 108 107 106 105 102 101 115 100 99 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 / AP A11 A12 M_BBS#0 M_BBS#1 117 116 BA0 BA1 M_DATA_R_0 M_DATA_R_1 M_DATA_R_2 M_DATA_R_3 M_DATA_R_4 M_DATA_R_5 M_DATA_R_6 M_DATA_R_7 M_DATA_R_8 M_DATA_R_9 M_DATA_R_10 M_DATA_R_11 M_DATA_R_12 M_DATA_R_13 M_DATA_R_14 M_DATA_R_15 M_DATA_R_16 M_DATA_R_17 M_DATA_R_18 M_DATA_R_19 M_DATA_R_20 M_DATA_R_21 M_DATA_R_22 M_DATA_R_23 M_DATA_R_24 M_DATA_R_25 M_DATA_R_26 M_DATA_R_27 M_DATA_R_28 M_DATA_R_29 M_DATA_R_30 M_DATA_R_31 M_DATA_R_32 M_DATA_R_33 M_DATA_R_34 M_DATA_R_35 M_DATA_R_36 M_DATA_R_37 M_DATA_R_38 M_DATA_R_39 M_DATA_R_40 M_DATA_R_41 M_DATA_R_42 M_DATA_R_43 M_DATA_R_44 M_DATA_R_45 M_DATA_R_46 M_DATA_R_47 M_DATA_R_48 M_DATA_R_49 M_DATA_R_50 M_DATA_R_51 M_DATA_R_52 M_DATA_R_53 M_DATA_R_54 M_DATA_R_55 M_DATA_R_56 M_DATA_R_57 M_DATA_R_58 M_DATA_R_59 M_DATA_R_60 M_DATA_R_61 M_DATA_R_62 M_DATA_R_63 13 17 14 18 19 23 29 31 20 24 30 32 41 43 49 53 42 44 50 54 55 59 65 67 56 60 66 68 127 129 135 139 128 130 136 140 141 145 151 153 142 146 152 154 163 165 171 175 164 166 172 176 177 181 187 189 178 182 188 190 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 M_BRAS# M_BCAS# M_BWE# VREF_DDR_MEM Layout trace 20 mil C381 SCD1U 3D3V_S0 CKE0 CKE1 96 95 DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS8 11 25 47 61 133 147 169 183 77 M_DQS_R0 M_DQS_R1 M_DQS_R2 M_DQS_R3 M_DQS_R4 M_DQS_R5 M_DQS_R6 M_DQS_R7 DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 DM8 12 26 48 62 134 148 170 184 78 M_ADM_R0 M_ADM_R1 M_ADM_R2 M_ADM_R3 M_ADM_R4 M_ADM_R5 M_ADM_R6 M_ADM_R7 CK0 /CK0 CK1 /CK1 CK2 /CK2 35 37 160 158 89 91 SCL SDA 195 193 SA0 SA1 SA2 194 196 198 VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD 10 21 22 33 34 36 45 46 57 58 69 70 81 82 92 93 94 113 114 131 132 143 144 155 156 157 167 168 179 180 191 192 15 16 27 28 38 39 40 51 52 63 64 75 76 87 88 90 103 104 125 126 137 138 149 150 159 161 162 173 174 185 186 201 118 120 119 /RAS /CAS /WE 197 199 VREF VREF VDDSPD VDDID 202 GND GND 85 DM2_RESET# 86 DM2_A13 97 DM2_BA2 98 M_BA13 123 124 200 5,9 M_BRAS# 5,9 M_BCAS# 5,9 M_BWE# 121 122 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 71 73 79 83 72 74 80 84 TP41 TP119 TP40 /CS0 /CS1 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 NC NC/(RESET#) NC/A13 NC/BA2 NC NC NC M_CS#2 5,9 M_CS#3 5,9 M_CKE#1 M_CKE#1 5,9 M_ADM_R[7 0] M_DATA_R_[63 0] M_ADM#0 M_ADM#1 M_ADM#2 M_ADM#3 M_ADM#4 M_ADM#5 M_ADM#6 M_ADM#7 M_DQS_R[7 0] M_ABS#[1 0] 5,9 M_BA[13 0] 5,9 M_BBS#[1 0] 5,9 DDR_CLK1 DDR_CLK#1 M_CLK4 5,9 M_CLK#4 5,9 M_CLK6 5,9 M_CLK#6 5,9 SMBC_SB 3,21 SMBD_SB 3,21 DM2_SA0 R233 4K7R3 3D3V_S0 2D5V_S3 DDR_CLK#1 DDR_CLK#0 DDR_CLK1 DDR_CLK0 SRN10K-2 DY AMD K8 ClawHummar MD63 SMA11 2D5V_S3 TOP VIEW PERSPECTIVE DRAWING By ME requset DM1 P/N: Main 62.10017.191 Second 62.10017.381 DM1 Pin 199 Pin Pin 200 Pin DM2(Reverse) By ME requset DM2 P/N: Main 62.10017.201 Second 62.10017.371 Third 62.10017.701 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title DDR SO-DIMM SKT Size A3 DDR-SODIMM-N-U1 C SMA10 SMA0 SMA14 MD0 SMA12 DDR SOCKET PLACEMENT Document Number Rev D SA SNIPE Date: Thursday, November 18, 2004 B RN41 DDR-SODIMM-R-U2 A M_AA[13 0] 5,9 Pin M_DATA_R_0 M_DATA_R_1 M_DATA_R_2 M_DATA_R_3 M_DATA_R_4 M_DATA_R_5 M_DATA_R_6 M_DATA_R_7 M_DATA_R_8 M_DATA_R_9 M_DATA_R_10 M_DATA_R_11 M_DATA_R_12 M_DATA_R_13 M_DATA_R_14 M_DATA_R_15 M_DATA_R_16 M_DATA_R_17 M_DATA_R_18 M_DATA_R_19 M_DATA_R_20 M_DATA_R_21 M_DATA_R_22 M_DATA_R_23 M_DATA_R_24 M_DATA_R_25 M_DATA_R_26 M_DATA_R_27 M_DATA_R_28 M_DATA_R_29 M_DATA_R_30 M_DATA_R_31 M_DATA_R_32 M_DATA_R_33 M_DATA_R_34 M_DATA_R_35 M_DATA_R_36 M_DATA_R_37 M_DATA_R_38 M_DATA_R_39 M_DATA_R_40 M_DATA_R_41 M_DATA_R_42 M_DATA_R_43 M_DATA_R_44 M_DATA_R_45 M_DATA_R_46 M_DATA_R_47 M_DATA_R_48 M_DATA_R_49 M_DATA_R_50 M_DATA_R_51 M_DATA_R_52 M_DATA_R_53 M_DATA_R_54 M_DATA_R_55 M_DATA_R_56 M_DATA_R_57 M_DATA_R_58 M_DATA_R_59 M_DATA_R_60 M_DATA_R_61 M_DATA_R_62 M_DATA_R_63 CKE0 CKE1 96 95 M_CS#0 5,9 M_CS#1 5,9 Pin BA0 BA1 121 122 Pin 200 117 116 E Pin 199 M_ABS#0 M_ABS#1 /CS0 /CS1 REVERSE TYPE A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 / AP A11 A12 112 111 110 109 108 107 106 105 102 101 115 100 99 M_AA0 M_AA1 M_AA2 M_AA3 M_AA4 M_AA6 M_AA5 M_AA7 M_AA8 M_AA9 M_AA10 M_AA11 M_AA12 D DM2 NORMAL TYPE DM1 Sheet E of 56 A B PARALLEL TERMINATION PULL HIGH STUBS < 0.8", PLACE RPs CLOSE TO SECOND DM ( DM2 ) NO EQUAL LENGTH LIMITATION 1D25V_S3 M_DATA_R_4 M_DATA_R_5 M_ADM_R0 M_DATA_R_6 M_DATA_R_7 M_DATA_R_13 M_DATA_R_12 M_ADM_R1 M_DATA34 M_DATA32 M_DQS4 M_DATA33 M_DATA36 M_DATA37 M_ADM4 M_DATA39 M_DATA_R_1 M_DATA_R_0 M_DQS_R0 M_DATA_R_2 M_DATA_R_3 M_DATA_R_8 M_DATA_R_9 M_DQS_R1 M_DATA35 M_DATA41 M_DATA40 M_DQS5 M_DATA42 M_DATA43 M_DATA49 M_DATA48 M_DATA_R_14 M_DATA_R_15 M_DATA_R_21 M_DATA_R_20 M_ADM_R2 M_DATA_R_23 M_DATA_R_22 M_DATA_R_25 M_DATA38 M_DATA45 M_DATA44 M_ADM5 M_DATA47 M_DATA46 M_DATA53 M_DATA52 M_DATA_R_35 M_DATA_R_41 M_DATA_R_40 M_DQS_R5 M_DATA_R_42 M_DATA_R_43 M_DATA_R_49 M_DATA_R_48 16 15 14 13 12 11 10 M_DATA_R_38 M_DATA_R_45 M_DATA_R_44 M_ADM_R5 M_DATA_R_47 M_DATA_R_46 M_DATA_R_53 M_DATA_R_52 RN27 16 15 14 13 12 11 10 M_DATA_R_11 M_DATA_R_10 M_DATA_R_17 M_DATA_R_16 M_DQS_R2 M_DATA_R_19 M_DATA_R_18 M_DATA_R_24 M_DQS6 M_DATA50 M_DATA51 M_DATA56 M_DATA57 M_DQS7 M_DATA58 M_DATA59 SRN10J-3 M_DQS_R6 M_DATA_R_50 M_DATA_R_51 M_DATA_R_56 M_DATA_R_57 M_DQS_R7 M_DATA_R_58 M_DATA_R_59 16 15 14 13 12 11 10 SRN10J-3 RN19 RN16 16 15 14 13 12 11 10 M_DATA_R_29 M_DATA_R_28 M_DQS_R3 M_ADM_R3 M_DATA_R_26 M_DATA_R_27 M_DATA_R_30 M_DATA_R_31 SRN10J-3 M_ADM6 M_DATA54 M_DATA55 M_DATA61 M_DATA60 M_ADM7 M_DATA62 M_DATA63 RN38 16 15 14 13 12 11 10 M_DATA_R_1 M_DATA_R_0 M_DQS_R0 M_DATA_R_2 M_DATA_R_3 M_DATA_R_8 M_DATA_R_9 M_DQS_R1 M_ADM_R6 M_DATA_R_54 M_DATA_R_55 M_DATA_R_61 M_DATA_R_60 M_ADM_R7 M_DATA_R_62 M_DATA_R_63 16 15 14 13 12 11 10 M_DATA_R_25 M_DATA_R_22 M_DATA_R_23 M_ADM_R2 M_DATA_R_20 M_DATA_R_21 M_DATA_R_14 M_DATA_R_15 16 15 14 13 12 11 10 8 M_DATA_R_30 M_DATA_R_31 M_DATA_R_26 M_DATA_R_27 M_ADM_R3 M_DQS_R3 M_DATA_R_29 M_DATA_R_28 M_DATA_R_36 M_DATA_R_32 M_DATA_R_37 M_DATA_R_33 M_ADM_R4 M_DQS_R4 M_DATA_R_38 M_DATA_R_39 16 15 14 13 12 11 10 1 16 15 14 13 12 11 10 SRN68J-1 RN42 M_CKE#0 M_AA12 M_ADM[7 0] M_DATA[63 0] M_DATA_R_[63 0] M_DATA_R_48 M_DATA_R_49 M_DATA_R_43 M_DATA_R_42 M_DQS_R5 M_DATA_R_41 M_DATA_R_40 M_DATA_R_34 16 15 14 13 12 11 10 M_DATA_R_35 M_DATA_R_46 M_DATA_R_47 M_ADM_R5 M_DATA_R_44 M_DATA_R_45 M_DATA_R_53 M_DATA_R_52 16 15 14 13 12 11 10 M_DATA_R_59 M_DATA_R_58 M_DQS_R7 M_DATA_R_57 M_DATA_R_56 M_DATA_R_51 M_DATA_R_50 M_DQS_R6 16 15 14 13 12 11 10 M_DATA_R_55 M_DATA_R_54 M_ADM_R6 M_DATA_R_60 M_DATA_R_61 M_ADM_R7 M_DATA_R_63 M_DATA_R_62 M_DQS_R[7 0] RN31 SRN68J-1 M_AA11 M_AA9 M_AA7 M_AA5 M_AA4 M_AA8 M_AA6 M_AA3 16 15 14 13 12 11 10 M_CS#3 M_BA13 M_CS#2 M_BRAS# M_BBS#1 M_BCAS# M_BA0 M_BA2 SRN47J-1-U RN39 16 15 14 13 12 11 10 M_AA1 M_AA10 M_AA2 M_AA0 M_ABS#1 M_ARAS# M_AWE# M_ABS#0 SRN47J-1-U RN30 16 15 14 13 12 11 10 M_BA7 M_BA3 M_BA6 M_BA9 M_BA10 M_BA1 M_BBS#0 M_BWE# SRN47J-1-U RN49 16 15 14 13 12 11 10 M_BA5 M_BA8 M_BA11 M_BA4 SRN10J-3 4 M_DQS[7 0] SRN47J 16 15 14 13 12 11 10 SRN68J-1 RN36 SRN68J-1 SRN47J RN32 SRN68J-1 RN47 16 15 14 13 12 11 10 M_ADM_R[7 0] RN50 M_CKE#1 M_BA12 SRN68J-1 RN37 SRN68J-1 RN51 M_DATA_R_11 M_DATA_R_10 M_DATA_R_16 M_DATA_R_17 M_DQS_R2 M_DATA_R_19 M_DATA_R_18 M_DATA_R_24 16 15 14 13 12 11 10 SRN68J-1 RN48 SRN68J-1 RN43 SRN10J-3 RN33 M_DATA29 M_DATA28 M_DQS3 M_ADM3 M_DATA26 M_DATA27 M_DATA30 M_DATA31 16 15 14 13 12 11 10 RN17 16 15 14 13 12 11 10 SRN10J-3 M_DATA11 M_DATA10 M_DATA17 M_DATA16 M_DQS2 M_DATA19 M_DATA18 M_DATA24 SRN10J-3 RN20 M_ADM_R1 M_DATA_R_13 M_DATA_R_12 M_DATA_R_6 M_DATA_R_7 M_ADM_R0 M_DATA_R_5 M_DATA_R_4 SRN68J-1 RN52 RN28 16 15 14 13 12 11 10 SRN10J-3 M_DATA_R_34 M_DATA_R_32 M_DQS_R4 M_DATA_R_33 M_DATA_R_36 M_DATA_R_37 M_ADM_R4 M_DATA_R_39 16 15 14 13 12 11 10 SRN10J-3 RN34 1D25V_S3 RN44 RN18 16 15 14 13 12 11 10 SRN10J-3 M_DATA14 M_DATA15 M_DATA21 M_DATA20 M_ADM2 M_DATA23 M_DATA22 M_DATA25 E SERIES DAMPING M_DATA1 M_DATA0 M_DQS0 M_DATA2 M_DATA3 M_DATA8 M_DATA9 M_DQS1 D PLACE RNs CLOSE TO FIRST DM ( DM1 ), < 0.75" STRICT EQUAL LENGTH LIMITATION WITH DQS, CB PINS RN21 M_DATA4 M_DATA5 M_ADM0 M_DATA6 M_DATA7 M_DATA13 M_DATA12 M_ADM1 C M_AA[13 0] 5,8 M_ABS#[1 0] 5,8 M_BA[13 0] 5,8 M_BBS#[1 0] 5,8 M_AWE# 5,8 M_ACAS# 5,8 M_ARAS# 5,8 M_BWE# 5,8 M_BCAS# 5,8 M_BRAS# 5,8 M_CS#0 M_CS#1 M_CS#2 M_CS#3 5,8 5,8 5,8 5,8 SRN47J-1-U RN40 SRN47-1 2 RN29 M_AA13 M_CS#0 M_CS#1 M_ACAS# SRN47-1 Place it near CPU 5,8 M_CKE#0 M_CKE#0 5,8 M_CKE#1 M_CKE#1 05/10 Remove the damping resistor for AMD suggest R498 121R3F M_CLK7 M_CLK#7 M_CLK7 5,8 M_CLK#7 5,8 R481 121R3F M_CLK6 M_CLK#6 M_CLK6 5,8 M_CLK#6 5,8 R499 121R3F M_CLK5 M_CLK#5 M_CLK5 5,8 M_CLK#5 5,8 R486 121R3F M_CLK4 M_CLK#4 M_CLK4 5,8 M_CLK#4 5,8 1 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title DDR DAMPING & TERMINATION hexainf@hotmail.com GRATIS - FOR FREE A Size A3 Document Number Date: Thursday, November 18, 2004 B C D Rev SA SNIPE Sheet E of 56 A B C D E 4 DY DY DY DY SCD1U 1 C451 DY SCD1U C454 SCD1U SCD1U DY C325 C452 SCD1U C324 C378 SCD1U SCD1U 2 C416 DY SCD1U C379 SCD1U SCD1U C449 C415 SCD1U C450 C414 SCD1U SCD1U 2 C447 DY SCD1U C448 SCD1U SCD1U C445 C413 SCD1U C446 C328 SCD1U SCD1U C443 DY C327 SCD1U SCD1U SCD1U C441 C444 SCD1U C442 C409 SCD1U SCD1U 1 C439 DY SCD1U C410 SCD1U SCD1U C437 C440 SCD1U C438 1 C435 SCD1U SCD1U C291 DY 2 C436 SCD1U SCD1U C290 1D25V_S3 LAYOUT:Place altemating caps to GND and 2D5_S3 2D5V_S3 C453 SCD1U DY 3 2D5V_S3 SCD1U C284 SCD1U DY DY DY DY C268 SCD1U C207 SCD1U DY DY C248 SCD1U C263 SCD1U C390 SCD1U C430 SCD1U C434 SCD1U SCD1U C280 DY C165 SCD1U 1 SCD1U C423 SCD1U C460 C275 C269 SCD1U SCD1U 2 C245 DY SCD1U SCD1U C319 C288 SCD1U SCD1U C399 C235 C376 SCD1U SCD1U 2 C407 DY SCD1U SCD1U C208 C310 SCD1U SCD1U C355 C408 C254 SCD1U SCD1U C293 DY SCD1U SCD1U C356 C228 SCD1U SCD1U C249 C292 C459 SCD1U SCD1U 2 C420 DY SCD1U SCD1U C457 C345 SCD1U SCD1U C421 C458 C418 SCD1U 2 SCD1U C455 DY 2 C419 SCD1U SCD1U C456 1D25V_S3 1D25V_S3 DY DY DY DY DY DY DY 2 LAYOUT:Place close to Power Pin of DDR socket 2D5V_S3 LAYOUT:Place at end of the DIMMs C917 C302 SCD22U16V3ZY C323 SCD22U16V3ZY C303 SCD22U16V3ZY SC22U10V6ZY-U C925 SC22U10V6ZY-U C880 SC22U10V6ZY-U C872 TC28 ST100U4VBM-1 SC22U10V6ZY-U TC27 ST100U4VBM-U 2D5V_S3 C301 SCD22U16V3ZY 2 1D25V_S3 DY C380 SCD22U16V3ZY C377 DY SCD22U16V3ZY DY C326 SCD22U16V3ZY C411 DY SCD22U16V3ZY C412 SCD22U16V3ZY C417 SCD22U16V3ZY 0.22u x 10 1 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title DDR DECOUPLING Size A3 Document Number Rev A B C D SA SNIPE Date: Thursday, November 18, 2004 Sheet E 10 of 56 A B C D E C789 SC10U35V0ZY-U DY DCBATOUT_ISL 4 C229 2 C788 ISL6559_UG3 ISL6559_PHASE_3 U70 L7 Power-PAK Id=7A Qg=10~15nC Rdson=13~16.5mohm NC2 NC1 U69 SI7392DP 84.07392.037 VCC_CORE_S0 L-D48UH-U 4 2 C236 SC1U10V3KX 1 D29 SSM54-U DY Power-PAK Id=13A Qg=32~50nC Rdson=4~4.8mohm R564 2KR3F 2 2 U22 SI7636DP 84.07636.037 S S S G C785 S S S G R556 DUMMY-R3 SCD01U50V3KX U67 SI7636DP 84.07636.037 R560 0R3-U ISL6207CB-U 74.06207.071 ISL6559_LG_3 ISL6207_EN3 PHASE EN VCC LGATE UGATE BOOT PWM GND D D D D R579 499KR3F D D D D ISL6559_PWM2 4 SCD22U16V3KX-1 41 ISL6559_PWM2 8 1 BOOT_3# S S S G S S S G 2D2R3 D D D D D D D D R566 U24 SI7392DP 84.07392.037 C166 C761 SCD1U50V3ZY DY SCD1U50V3ZY 5V_S0 DCR=1.3mohm+-10% / Imax=40A / Panasonic / ETQP2H0R7BF / 0.48uH / 13.4*13.3*4.9 DUMMY-C3 Follow MOSFET rise time spec BOOT_3 2 1 SB Version: Change U68 from ISL6209CB (74.06209.071) to ISL6207CB-U (74.06207.071) ISEN2 ISEN2 41 2 1 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title CPU Vcore Power_2 Size A3 Document Number Rev A B C D SA SNIPE Date: Thursday, November 18, 2004 Sheet E 42 of 56 5V_DC_S5 GAP-OPEN-PWR GAP-OPEN-PWR G75 GAP-OPEN-PWR G76 GAP-OPEN-PWR G71 GAP-OPEN-PWR MAX1999_LDO5 GAP-OPEN-PWR DCBATOUT_MAX1999_1 4D7R5 19 22 OUT3 OUT5 21 MAX1999_SD_3 MAX1999_ON5 MAX1999_SHDN# ON3 ON5 SHDN# FB5 MAX1999_FB5 R273 10 PRO# NC MAX1999_PRO#1 100KR3 MAX1999_ILIM5 ILIM3 MAX1999_ILIM3 MAX1999_PGD 30mA MAX SC1U25V5ZY C382 SC: 5V R214=>40K2R3F OCP: Main Source Adapter=12.6A Battery=11.6A Second Source Adapter=16.4A Battery=14.4A SCD1U 100KR3 25 MAX1999_ILIM5 C346 SC4D7U10V5ZY DY MAX1999_ILIM3 D G S5PWR_ENABLE 23,44 2N7002 R648 100KR3 R282 10KR3F Wistron Corporation R244 10KR3F 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title 5V_UP_S5/3D3V_S5/5V_S5 PM_SLP_S3# 18,21,34,38,39,44,55 Size A3 Adjust 3V/5V current limit Document Number Date: Thursday, November 18, 2004 B R248 Q40 A MAX1999_SHDN# TPAD30 S hexainf@hotmail.com GRATIS - FOR FREE MAX1999_VCC 1 0R3-U SC: 3.3V R186=>20KR3F OCP: Main Source Adapter=10.6A Battery=10.4A Second Source Adapter=9.4A Battery=9.2A Q32_D MAX1999_SD_3 TP112 2 0R3-U R240 MAX1999_SKIP# MAX1999_ON5 R241 2 U93 2N7002DW R272 MAX1999_ILIM5_3 GAP-CLOSE-PWR R647 100KR3 R281 100KR3 Open Drian 2 SC1U25V5ZY C401 R301 9K76R3F 20KR3F 1 2 MAX1999_LDO5 C357 MAX1999_LDO5 R274 MAX1999_LDO5 30mA MAX 2 10KR3 OCP Setting 3D3V_AUX_S5 MAX1999_ILIM5_3 R243 8K66R3F MAX1999EEI C424 SC100P50V2JN 15KR3F R673 R687 DUMMY-R3 23 GND SKIP# LDO5 12 18 MAX1999_SKIP# LDO3 PGOOD Ton = VCC : 200KHz/300KHz Ton = GND : 400KHz/500KHz (5V/3D3V) R271 100KR3 R300 MAX1999_FB5 DY REF C881 SCD22U16V3ZY MAX1999_VCC R260 NC,SO-8 2MR3 Id=9.6A DY Rdson=13.5~16.5mohm 11 KEMET, NT:8.5 ESR=25mohm Iripple=2.2A 7.3/4.3/1.9 ILIM5 TC26 ST220U6D3VDM-4 80.22715.191 2 DUMMY-R3 MAX1999_REF MAX1999_VCC C875 DUMMY-C3 R283 MAX1999_TON 13 TON 10KR3 R284 MAX1999_VCC 1 R236 10K2R3F C391 SC47P50V2JN U95 AO4406 MAX1999_LX5_1 84.04406.037 FB3 2 IND-6D8UH-14 68.6R810.10A MAX1999_DL5 15 DL5 LX5 DL3 5V_DC_S5 LX3 24 Imax=6.0A, DCR=25mohm 12*12*3.9 27 MAX1999_DL3 L30 Iomax=6A OCP:12~14A MAX1999_LX5 MAX1999_LX3 NC,SO-8 Id=9.3A Rdson=19.6~24mohm MAX1999_DH5 1 16 GAP-OPEN-PWR U89 AO4422 84.04422.037 V+ DH5 DH3 D D D D 1 BST5 26 2 MAX1999_BST5_1 14 MAX1999_FB3 MAX1999_SKIP C892 SCD1U C895 SCD1U C894 SC10U35V0ZY-U S S S G KEMET, NT=6.6 ST150U6D3VDM-9 80.15715.191 ESR=40mohm Iripple=1.7A 7.3/4.3/1.9 GAP-CLOSE-PWR MAX1999_BST3_1 28 BST3 R261 2MR3 DY R242 6K65R3F U39 C893 SC4D7U25V6KX DY MAX1999_LX3_1 2 DUMMY-C3 ST150U6D3VDM-9 80.15715.191 C392 SC47P50V2JN 1 1 Imax=6.0A, DCR=25mohm 12*12*3.9 C347 SC100P50V2JN R699 GAP-CLOSE-PWR R661 MAX1999_DH3 TC24 MAX1999_BST5 D D D D C876 78.47522.521 VCC C874 SCD1U 300KR3 L27 IND-6D8UH-14 68.6R810.10A DCBATOUT_MAX1999 D38 BAW56 G S S S U82 AO4422 84.04422.037 NC,SO-8 Id=9.3A Rdson=19.6~24mohm 3D3V_DC_S5 C882 SC1U10V3KX SCD1U 20 D D D D Iomax=4.0A OCP:8A~9.5A MAX1999_BST3 R672 10R3 NC,SO-8 Id=9.3A Rdson=19.6~24mohm SC1U25V5ZY U88 AO4422 84.04422.037 C393 G S S S GAP-OPEN-PWR 1 C400 C855 C854 DY SCD1U50V5ZY SC10U35V0ZY-U GAP-OPEN-PWR D D D D MAX1999_VCC R688 G S S S GAP-OPEN-PWR G1142 1 DCBATOUT_MAX1999 R249 DCBATOUT_MAX1999 GAP-OPEN-PWR G1202 GAP-OPEN-PWR G1152 1 3D3V_S5 GAP-OPEN-PWR G60 2 GAP-OPEN-PWR G1122 5V_S5 GAP-OPEN-PWR G1182 17 3D3V_DC_S5 DCBATOUT_MAX1999 G1112 G1172 GAP-OPEN-PWR G1192 GAP-OPEN-PWR G66 GAP-OPEN-PWR G1132 G116 E GAP-OPEN-PWR G65 DCBATOUT D G67 G104 C SYSTEM DC/DC 3D3V_S5/5V_S5 G70 B A C D Rev SA SNIPE Sheet E 43 of 56 (2D5V=>CH1 , 1D2V=>CH2 , 1D8V =>CH3) close to IC 1 R698 1 5130_FB2 5130_TRIP2 R704 5130_OUT1U 45 5130_OUT1D 45 5130_TRIP2 48 47 46 45 44 43 42 41 40 39 38 37 1D2V_S0_EN R307 100KR2 R308 2N7002DW C465 84.27002.03F SC4700P50V3KX PM_SLP_S3# 5130_FB1 5130_SS_STBY1 5130_INV2 5130_FB2 5130_SS_STBY2 5130_PWMSEL 5130_CT DUMMY-R2 ZZ.DUMMY.X02 R731 DCBATOUT_5130 5130_REF STBY_REF 5130_STBY_LDO 100KR2 C879 5130_LH2 FB1 SS_STBY1 INV2 FB2 SS_STBY2 PWM_SEL CT GND REF STBY_VREF5 STBY_VREF3.3 STBY_LDO LL2 OUT2_U LH2 VIN VREF3.3 VREF5 REG5V_IN LDO_IN LDO_CUR LDO_GATE LDO_OUT INV_LDO TPS5130 TPS5130_1D5V_EN# DCBATOUT_5130 C395 5130_5V_LDO 5130_OUT2U 45 5130_3D3V_LDO SCD1U50V3KX 5130_REGIN R685 0R5J-1 5130_3D3V_LDO 5V_S5 C394 SC4D7U10V5ZY 78.47593.411 C406 SC4D7U10V5ZY 78.47593.411 5130_OUT3D 5130_LL3 5130_OUT3U 5130_REF S5PWR_ENABLE 5130_SS_STBY3 C927 SCD1U 5130_LH3 5V_S0 5130_OUT3U 45 5130_LL3 45 PWM_SEL Condition Voltage H : Auto PWM/SKIP 2.2V(Min)~ L : PWM fixed (300KHz) ~0.3V(Max) 1 R298 10KR2 * D37 BAT54-1 83.00054.L03 DCBATOUT_5130 5130_TRIP3 A R299 0R2-0 5130_PG_DELAY C922 SC4700P50V3KX 78.47224.2B1 2 2N7002DW 84.27002.03F 5130_OUT3D 45 C885 SCD1U50V3KX 5130_5V_LDO 5130_SS_STBY3 5130_FB3 5130_INV3 100KR2 R306 0R2-0 63.R0034.1D1 5130_STBY_LDO C428 DY Wistron Corporation DUMMY-C3 ZZ.DUMMY.XC3 R305 0R2-0 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C PM_SLP_S3# PM_SLP_S3# Title TI TPS5130 2D5V/1D2V/1D8V (1/2) ,34,38,39,43,55 close to IC 5130_OUT2U TPS5130PT-U 13 14 15 16 17 18 19 20 21 22 23 24 C924 SC47P50V2JN 78.47034.1F1 U44 A 36 35 34 33 32 31 30 29 28 27 26 25 B 5V_AUX_S5 R320 5130_LL2 45 LDO SETTING S5PWR_ENABLE 5130_CT 5130_LL2 SCD1U50V3KX 1D2V_S0_EN 23,43 S5PWR_ENABLE C SS_STBY3 FB3 INV3 PGOUT PG_DELAY TRIP3 VIN_SENSE3 LH3 OUT3_U LL3 OUT3_D OUTGND3 B 10 11 12 GAP-CLOSE ZZ.CON2C.XX1 U94 INV1 FLT LH1 OUT1_U LL1 OUT1_D OUTGND1 TRIP1 VIN_SENSE12 TRIP2 OUTGND2 OUT2_D G121 5130_OUT2D 45 2 R309 100KR2 5130_SS_STBY2 5130_SS_STBY1 ,34,38 PM_SLP_S5# 5130_OUT2D OCP 8.4A=>R229=12.65K 10A=>R229=22K 2 SC4700P50V3KX 5130_3D3V_LDO close to IC U45 39 1D2V_S0_EN C889 22K1R3F SCD1U 5130_FLT 5130_FLT 5130_INV1 GAP-OPEN-PWR DCBATOUT_5130 5130_FB1 C916 SCD01U16V2KX GAP-OPEN-PWR G68 OCP 8.4A=>R226=13K 10A=>R226=22K DCBATOUT_5130 5130_TRIP3 T(soft)=1.736ms 1D8V_OCP 5130_TRIP1 5130_INV1 C466 GAP-OPEN-PWR G69 close to IC 5130_LL1 45 SCD1U50V3KX 5130_OUT1U 5130_OUT1D DCBATOUT_5130 SCD1U 5130_LL1 D GAP-OPEN-PWR G62 C886 22K1R3F D36 BAT54-1 83.00054.L03 C907 C GAP-OPEN-PWR G61 2 5130_LH1 close to IC C930 SC3900P50V3KX OCP 12A=>R225=18K 18A=>R225=28K 1D2V_OCP 5130_INV2 R734 2KR3 63.20234.151 5130_5V_LDO D39 BAT54-1 83.00054.L03 330R2F SC5600P50V3KX 78.56224.2B1 R312 19K6R3F 2 SCD1U close to IC C931 C890 28K7R3F GAP-OPEN-PWR G56 2D5V_PWR R314 10KR2F-U C928 SC3900P50V3KX 5130_5V_LDO 2KR3 63.20234.151 R735 5130_TRIP1 R732 5130_FB3 For 2.5V SETTING=2.516V 10KR2F-U 5130_INV3 C923 SC3900P50V3KX close to IC 2KR3 63.20234.151 C929 330R2F SC5600P50V3KX 78.56224.2B1 R310 4K32R3F DCBATOUT_5130 G57 DCBATOUT_5130 1D2V_PWR R733 R311 R705 For 1.2V SETTING=1.2172V R727 D DCBATOUT 2D5V_OCP 2 R726 Vo=(R1*0.85)/R2+0.85 C906 680R3F SC5600P50V3KX 78.56224.2B1 R303 11K5R3F 10KR2F-U 1D8V_PWR R304 TI TPS5130 for 2.5V, 1.2V, 1.8V For 1.8V SETTING=1.8275V Size A3 Document Number Rev SNIPE Date: Thursday, November 18, 2004 SA Sheet 44 of 56 TI TPS5130 for 2D5V, 1D2V, 1D8V 2D5V_PWR (2D5V=>CH1 , 1D2V=>CH2 , 1D8V =>CH3) 2 2D5V_PWR S S S G 1 D D D D C 5130_OUT1D Imax=9A DCR=12mOhm 12*12*4.0 2D5V Iomax=9A OCP>18A GAP-OPEN-PWR G81 GAP-OPEN-PWR G80 IND-2D2UH-16 44 5130_OUT1D GAP-OPEN-PWR G77 GAP-OPEN-PWR G78 Imax=9.3A Rdson=19.6~24mohm L32 5130_OUT1U 5130_LL1 U46 AO4406 C396 SC10U35V0ZY-U D D D D G S S S 44 5130_OUT1U 44 5130_LL1 D GAP-OPEN-PWR G74 1 D U43 AO4422 GAP-OPEN-PWR G73 DCBATOUT_5130 C429 SCD1U 2D5V_S3 G72 TC25 ST220U4VDM-L3 TC29 ST330U6D3VDM-7 GAP-OPEN-PWR G79 G83 KEMET, NTD:10.5 (Q1) ESR=25mohm Iripple=2.2A 7.3*4.3*1.9 Imax=9.6A Rdson=13.5~16.5mohm KEMET, NTD:6.5 (Q1) ESR=40mohm Iripple=1.7A 7.3*4.3*1.2 DCBATOUT_5130 GAP-OPEN-PWR 1 G82 C GAP-OPEN-PWR 1 GAP-OPEN-PWR 44 5130_OUT2U 44 5130_LL2 C860 SC10U35V0ZY-U 1D2V_PWR 1D2V_PWR GAP-OPEN-PWR G53 1D2V Iomax=5A OCP>10A GAP-OPEN-PWR G52 G51 2 Imax=9.3A Rdson=19.6~24mohm 44 5130_OUT2D GAP-OPEN-PWR TC5 ST220U4VDM-10 KEMET, NTD:7.8 (Q1) ESR=25mohm Iripple=2.2A 7.3*4.3*1.9 G S S S B D D D D IND-3D3UH-18 Imax=6A DCR=13mOhm 10*10*4.0 GAP-OPEN-PWR G43 Imax=9.3A Rdson=19.6~24mohm L26 5130_OUT2U 5130_LL2 U81 AO4422 1D2V_S0 G42 D D D D C853 SCD1U G S S S U86 AO4422 5130_OUT2D G55 GAP-OPEN-PWR G54 GAP-OPEN-PWR GAP-OPEN-PWR DCBATOUT_5130 G S S S 44 5130_OUT3U 44 5130_LL3 C374 SCD1U Imax=9.3A Rdson=19.6~24mohm L25 5130_OUT3U 5130_LL3 1D8V_PWR G S S S Imax=6A DCR=25mOhm 10*10*4.0 44 5130_OUT3D hexainf@hotmail.com GRATIS - FOR FREE 5130_OUT3D Imax=9.3A Rdson=19.6~24mohm 1D8V Iomax=5A OCP>10A D D D D U36 AO4422 C354 SC10U35V0ZY-U GAP-OPEN-PWR G45 GAP-OPEN-PWR G46 IND-4D7UH-25 A 1D8V_S5 G44 D D D D 1D8V_PWR U37 AO4422 B TC23 ST220U4VDM-10 KEMET, NTD:7.8 (Q1) ESR=25mohm Iripple=2.2A 7.3*4.3*1.9 GAP-OPEN-PWR G47 GAP-OPEN-PWR G48 A GAP-OPEN-PWR G49 GAP-OPEN-PWR G50 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title TI TPS5130 2D5V/1D2V/1D8V (2/2) GAP-OPEN-PWR Size A3 Document Number Rev SA SNIPE Date: Thursday, November 18, 2004 Sheet 45 of 56 A B C D E 5V_AUX_S5 5/17 power team change 5V_AUX_S5 C870 LP2951ACM_FB SC330P50V2KX C858 SC10U10V5ZY DY OUT INPUT SENSE FB SD 5V/TAP GND 100mA ERROR 4 1 C867 SCD1U DCBATOUT U35 LP2951ACM C427 C427 SC1U50V5ZY 78.10594.411 DY 3 G63 5V_S5 C375 SCD1U GND GND C389 SCD1U VOUT NC NC NC VIN VREF VCNTL 1 TC6 ST100U4VBM-1 GAP-OPEN-PWR C344 SC22U10V6ZY-U 78.22693.421 APL5331KAC-TR SO-8-P 1D25V_S3 GAP-OPEN-PWR G64 2 R258 1KR3F 1D25V_LDO APL5331_1D25V_VREF GAP-OPEN-PWR G59 Vo(cal.)=1.250V U38 R259 1KR3F 2 GAP-OPEN-PWR G58 1D25V_S3 Iomax=1.5A 2D5V_S3 C397 SC10U10V5ZY 78.10693.411 DY C398 SC10U10V5ZY 78.10693.411 2 2D5V_S3 KEMET 100uF / 4V / B2 Size / NTD:5.615 Iripple=1.1A / ESR=70mohm Trace Length=1cm (500mils) Trace Width=8mils Trace Resistance>25mohm 1 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title 1D2V_LDO/5V_AUX Size A3 Document Number Date: Thursday, November 18, 2004 A B C D Rev SA SNIPE Sheet E 46 of 56 BT+ DCBATOUT C873 SCD1U25V3KX DY R686 DUMMY-R3 G103 G102 C850 SC1U50V5ZY DY AO4407 MAX1909_ACIN MAX1909_PDL GAP-CLOSE-PWR Close to MAX1909 pin 24 R617 13K3R3F D D D D AO4407 U91 S S S G D D D D C462 SCD1U AO4407 ACOK is 17.8V GAP-CLOSE-PWR U92 S S S G 1 AC_IN Threshold 2.089V Max AC_IN > 2.089V > AC DETECT For EMI AD+_TO_SYS 2 R612 100KR3F S S S G 1 1 DY C844 C845 SC1000P50V2KX SC1000P50V2KX D D D D R635 D01R2512F-1 U79 AD+ R247 D33 C842 SCD1U 22 28 DLOV 21 DHI 23 MAX1909_DHI DLO 20 MAX1909_DLO PGND 19 PGND 29 CSIP 18 CSIN BATT GND 17 16 15 Near MAX1909 Pin 21 2 1 1 C933 C932 C891 SC10U25V0KX SC10U25V0KX SC10U25V0KXDY GAP-CLOSE-PWR 2 2 G100 NC Id=5.0A Rdson=23~30mohm G101 GAP-CLOSE-PWR BAT+SENSE 48 From Battery Connector V_REF :4.2235V (Fixed PWM Mode FPWM (Low)=>Hysteretic Mode C818 SCD1U TP30 TC20 ST220U2D5VBM 77.C2271.031 5234_HDRV 5234_LDRV 14 10 HDRV LDRV 11 5234_VIN VGA_CORE_PWR L45 IND-2D2UH-4 R217 1 5234_VSEN DCBATOUT_5234 2 VSEN VOUT VIN VCC 10KR2 1 5234_ISEN 5234_SW 12 13 ISNS SW Vishay IHCP-5050 Imax=16A, DCR=8mohm 12.9*13.58*3.5, NTD:11.05 R227 1K2R3F PM_SLP_S3# 5234_SS 5234_ILIM 5234_EN 1D2V or 1D15V Iomax=11 or 5.2A OCP>20A DY IND-2D2UH-18 PGND AGND 2 18,21,34,38,39,43,44 R215 FPWM BOOT SS ILIM EN GAP-OPEN-PWR L61 U34 16 15 GAP-OPEN-PWR G93 TC21 ST330U3VDM GAP-OPEN-PWR G40 1 5234_BOOT SSM5818SL G D34 C833 SC10U25V6MX Id=30A,Qg=15~20nC Rdson=22~28mohm USD:0.12 C835 SCD1U U78 APM3023NUCTR C312 R216 DUMMY-R2 C834 SC10U25V6MX GAP-OPEN-PWR 2 D C311 SCD1U16V GAP-OPEN-PWR G110 GAP-OPEN-PWR G107 5V_S0 GAP-OPEN-PWR G106 GAP-OPEN-PWR G108 C847 SC4D7U10V5ZY GAP-OPEN-PWR G91 G105 5V_S0 GAP-OPEN-PWR G98 VGA_CORE_S0 G38 NEC B2 Size 220uF 2.5V ESR=35mohm Iripple=1.558A NTD:6.37 KEMET V Size 330uF 3V ESR=15mohm, Iripple=2.9A NTD:9.5 2 Vo=1.20V, R1775=0.698Kohm(R3F) =>Vo(cal.)=1.2141V Rilim=(11.2/Iilim)*((100+Rsense)/Rdson) for M26 & M22 3D3V_S0 G21 C777 SC10U10V5ZY G22 GAP-OPEN-PWR TC3 ST100U6D3VBM GAP-OPEN-PWR R558 10KR3F Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C C779 SCD1U 1 APL5332KAC U26 1 R557 8K66R3F VIN BS FB VOUT NC#8 NC#7 GND NC#5 GND 1D5V_VGA_S0 C778 SC10U10V5ZY 2 EPCI_PWR Title FAN5234_VGA_CORE_1D20V or 1D15V hexainf@hotmail.com GRATIS - FOR FREE A Size A3 Document Number Date: Thursday, November 18, 2004 B C D Rev SA SNIPE Sheet E 55 of 56 HOLE14 HOLE HOLE12 HOLE HOLE15 HOLE HOLE17 HOLE HOLE19 HOLE HOLE29 HOLE HOLE30 HOLE 1 HOLE4 HOLE HOLE1 HOLE 1 HOLE24 HOLE HOLE23 HOLE 1 HOLE22 HOLE HOLE10 HOLE D HOLE26 HOLE TSAHCT125 1 1 11 TSAHCT125 U73D 14 14 13 12 U73C TSLCX14MTC-L-U 8 U47D 3D3V_S0 14 U47C EC15 SCD1U 3D3V_S0 5V_S0 10 14 5V_S0 TSLCX14MTC-L-U DVI_VCC C 2D5V_S0 1 EC14 SCD1U EC19 SCD1U HOLE13 HOLE HOLE21 HOLE 1D8V_S5 5V_S5 C HOLE6 HOLE 1 EC13 SCD1U EC3 SCD1U EC20 SCD1U 2 1 EC4 SCD1U HOLE5 HOLE EC2 SCD1U 1D8V_S0 EC12 SCD1U EC16 SCD1U D 5V_S0 HOLE8 HOLE EC1 SCD1U 1 EC8 SCD1U 2 EC18 SCD1U 1 EC11 SCD1U HOLE2 HOLE 3D3V_S3 3D3V_S0 3D3V_S0 EC7 SCD1U 3D3V_S0 U73E 2D5V_S3 U73F 14 14 2 EC10 SCD1U VPP_ASKT_S0 VPP_BSKT_S0 11 10 3D3V_S5 EC6 SCD1U TSLCX14MTC-L-U HOLE28 HOLE7 HOLE3 HOLE9 HOLE18 HOLE11 HOLE16 HOLE25 HOLE20 B 1 1 1 1 EC17 SCD1U B 1 HOLE27 12 EC5 SCD1U 2 EC9 SCD1U 1 13 TSLCX14MTC-L-U DY DY DY GND15 GND13 DY 1 GND9 DY DY GND16 SPRING-23 DY DY 1 GND19 GND7 SPRING-24 1 GND3 SPRING-1 DY GND20 GNDPAD GND18 GNDPAD GND4 SPRING-1 GND1 SPRING-1 1 GND11 GNDPAD DY DY DY A A GND6 GNDPAD DY DY 1 DY GND14 GNDPAD DY GND5 GNDPAD DY GND12 GNDPAD DY GND10 GNDPAD GND8 GNDPAD GND2 DY 1 GND21 GND22 GND24 GND25 GNDPAD GNDPAD GNDPAD GNDPAD DY DY DY DY Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title EMI COMPONENTS Size A3 Document Number Rev SA SNIPE Date: Thursday, November 18, 2004 Sheet 56 of 56 ... VSSA68 VSSA67 VSSA66 VSSA65 VSSA64 VSSA63 VSSA62 VSSA61 VSSA60 VSSA59 VSSA58 VSSA57 VSSA56 VSSA55 VSSA54 VSSA53 VSSA52 VSSA51 VSSA50 VSSA49 VSSA48 VSSA47 VSSA46 VSSA45 VSSA44 VSSA43 VSSA42 VSSA41... VSSA40 VSSA39 VSSA38 VSSA37 VSSA36 VSSA35 VSSA34 VSSA33 VSSA32 VSSA31 VSSA30 VSSA29 VSSA28 VSSA27 VSSA26 VSSA25 VSSA24 VSSA23 VSSA22 VSSA21 VSSA20 VSSA19 VSSA18 VSSA17 VSSA16 VSSA15 VSSA14 VSSA13... AVDD_SATA_1 AVDD_SATA_2 AVDD_SATA_3 AVDD_SATA_4 AVDD_SATA_5 AVDD_SATA_6 AVDD_SATA_7 AVDD_SATA_8 AVSS_SATA_1 AVSS_SATA_2 AVSS_SATA_3 AVSS_SATA_4 AVSS_SATA_5 AVSS_SATA_6 AVSS_SATA_7 AVSS_SATA_8