Acer aspire 3010 5010 wistron SNIPE RevSA

5 300~400mA 100/133Mhz CLK GEN ICS 951412 IDT CV137 100Mhz 100/133Mhz CPU clk NB clk VTT 1.25V S3 AMD CPU Mem Ref 1.25V fr S3 SB clk VDDA 2.5V S0 VGA clk VDD VCC_core S0 VDDIO 2.5V S3 AVDD 3.3 S0( CRT/TV) AVDDDI , AVDDQ 1.8V S0 ( CRT/TV) LVDS 1.8V S0 ATI RS480M AGTL+ CPU I/F + UMA PCIE 1.8V S0 ACPI 2.0 PCI 6xUSB 2.0 PCI Bus / 33MHz RJ11 CONN 29 24 30 10/100Mb 44 MAX1999EEI OUTPUT 5V_S5 , 3D3V_S5 45,46 OUTPUT DCBATOUT 2D5V_S3 1D8V_S5 1D2V_S0 Line Out OP AMP G1421 33 CPU V_CORE 42,43 33 ISL6559CR INPUT 33 OUTPUT DCBATOUT B VCC_CORE_S0 SYSTEM POWER 47 LP2951ACM/APL5331KAC-TR HDD DVD/ CD-RW 25 Thermal & Fan G791 23 NS SIO PC87381 SIDE TXFM C SYSTEM DC/DC INPUT 18,19,20,21,22 PIDE 30 ATA 133 PCI LAN Realtek RTL8110SBL 1000/100/10 RTL8100C 100/10 29 DCBATOUT TPS 5130 LPC Bus / 33MHz LPC I/F 30 DVI-D 15 Line In 33 MIC In 32 31 1000Mb OUTPUTS AD+ BAT+ Int SPKR TXFM INPUTS SYSTEM DC/DC AC97 MODEM MDC Card RJ45 16 INPUT CODEC ALC655 24 6-CH AC97 2.2 B CRT 4Mx 32 bit x4= 64MB 8Mx 32 bit x4= 128MB 16Mx 32 bit x4= 256MB USB x 48 MAX1909ETI DCBATOUT 28 Mini-PCI 802.11a/b/g 17 Battery Charger RGB CRT VRAM x4 HY5DS573222F 53,54 SB400 VDD 1.8V S0 3.3 S5, 1.8 S5 LCD TMDS ATI VDDQ 3.3V S0 26,27 50,51,52 PCI-Express x2 TI PCI 7421 PCMCIA I/F LVDS 0.11um, CSP/ BGA 708Pin , 31mmx 31mm 1.0~1.3V CMOS technology PCI Express x16 D L1: Signal L2: GND L3: Signal L4: Signal L5: VCC L6: Signal TVOUT 16 11,12,13,14 Xtal 32.768 Khz 2* Slot Cardbus 1* 1394 SVIDEO/COMP Discrete ATI M26/M24 0.13um, 706 BGA package 31mmx 31mm 1.0~1.2V CMOS technology PLL 1.8V S0 Clock 3.3V S0 C PCB Layer Stackup 8,9,10 HyperTransport 6.4GB/S 16b/8b VDD 1.8V S0 VDD mem 2.5V S3 28 200-PIN DDR SODIMM UMA VDD HT 1.2V S0 PWR SW TPS2224AP DDR x2 4,5,6,7 Vcore 1.2V S0 1394 Conn VDD 2.5V S3 Vref DDR 1.25V S3 DDR 333/400 Sempron / Athlon K8 48Mhz for USB/ Cardbus 28 VLDT 1.2V S0 200Mhz PCMCIA SLOT Support TypeII SNIPE Block Diagram Xtal 14.318Mhz D 37 XBUS KBC KB3910 OUTPUT INPUT 2D5V_S3 DCBATOUT 34 1D25V_S3 5V_AUX_S5 25 FIR TFDU6102 37 Touch Pad 35 Int KB ISA ROM 35 36 A A Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title BLOCK DIAGRAM Size A3 Document Number Rev SA SNIPE Date: Monday, November 22, 2004 Sheet 1 of 56 D SA to SB need to check connect G781 Thermal Alert pin to VGA_GPIO14 ene KBC P165 LPCRST# , we suggest pull low avoid leakage Clk to NB need to add Cap when the trace change layer check page what is the value of R481,R486, R498 and R499 is 100 ohm or 12 ohm check page 15, if on discrete mode does the 1D8V_S0 power for lvds should dummy or still contect on power plan check page 19, can the ohm resistance be dummied on P.19 right hand side? check page 20, R203's voltage on pin page 21 check when the unused USB pin should be pull down or floating Can R471 change to common value? 10 check giga lan and 10/100 connect Does them the same or can chose a cheaper one? 11 page 38 12VGATE_S0 can decreased resistance 12 Does the 1D5V_VGA_S0 can come from TPS5130? D Schematic change: R659, change from 0R2 to 10Kr2 C C B B A A Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title CHANGE HISTORY Size A3 Document Number SNIPE Date: Thursday, November 18, 2004 Rev SA Sheet of 56 A B C D E 3D3V_S0 3D3V_S0 3D3V_CLK_VDD 3D3V_CLK_VDDA 1 SC22U10V6ZY-U C253 SCD1U16V 2 C808 SCD1U16V C252 1 C810 SCD1U16V C807 SCD1U16V 2 C793 SCD1U16V 1 0R3-U 2 L8 1 C794 L24 0R3-U SC22U10V6ZY-U RN5 C812 3D3V_S0 SCD1U16V 3D3V_CLK_VDD U28 L22 3D3VDD48_S0 0R3-U C787 SC2D2U16V5ZY C811 SCD1U16V RN4 C801 SCD1U16V 2 C800 SCD1U16V 3D3V_CLK_VDDA C206 SC33P50V2JN XI_CLK R145 DUMMY-R3 DY X3 27 21 8,21 8,21 X-14D318MHZ-1-U1 XO_CLK SC33P50V2JN R152 CLK48_CARDBUS R151 CLK48_USB R158 SMBC_SB R159 SMBD_SB USB_48M SMBC_CLK SMBD_CLK C227 1 1 2 2 22R2 22R2 0R2-0 0R2-0 R146 13 CLK14_NB 33R2 32 CLK14_AUDIO R147 33R2 37 CLK14_SIO 13 HTREF_CLK VDD_48 VDDA VDD_SRC 21 14 35 VDD_SRC VDD_SRC VDD_SRC 56 51 43 48 VDD_REF VDD_PC1 VDD_CPU VDD_HTT XIN XOUT USB_48 SCL SDA 10 11 R155 33R2 R162 33R2 CLK_REF2 52 REF2 R161 33R2 CLK_HTT66 47 50 HTT66 PCI0 1 IREF_CLKGEN R170 49D9R2F R182 SEL24/24_48# REF1 REF0 37 IREF NC#6 SBLINK_CLK# 13 SBLINK_CLK 13 SRN33-2-U2 SBSRC_CLK# 18 SBSRC_CLK 18 33 34 25 24 23 22 19 18 17 16 13 12 CPUC1 CPUT1 CPUC0 CPUT0 40 41 44 45 CPUCLKJ_CY CPUCLK_CY SRCC1 SRCT1 SRCC2 SRCT2 29 30 28 27 ATI_CLK0# ATI_CLK0 ATI_CLK1# ATI_CLK1 VSS_SRC VSS_SRC RESET# TURBO1 36 20 15 26 VSS_CPU VSS_PCI VSS_HTT VSS_SRC VSSA VSS_48 VSS_REF 42 49 46 31 38 55 R171 R172 RN7 RN6 2 15R2J 15R2J 4 SRN33-2-U2 SRN33-2-U2 CPUCLK# CPUCLK NBSRC_CLK# 13 NBSRC_CLK 13 GFX_CLK# 449 GFX_CLK 449 VGA Do not stuff when using UMA IDTCV137PAG 2 475R2F 53 54 SRN33-2-U2 SRC_CLK0# SRC_CLK0 SRC_CLK3# SRC_CLK3 SRCC0 SRCT0 SRCC3 SRCT3 SRCC4 SRCT4 SRCC5 SRCT5 SRCC6 SRCT6 SRCC7 SRCT7 CLKREQ0# CLKREQ1# FS2 FS1 FS0 21 SB_OSC_CLK 39 32 SBLINK_CLK# R192 49D9R2F SBLINK_CLK R193 49D9R2F SBSRC_CLK# R190 49D9R2F SBSRC_CLK R191 49D9R2F GFX_CLK# R198 49D9R2F GFX_CLK R189 VGA 49D9R2F VGA Do not stuff when using UMA 2 3D3V_CLK_VDD DY R148 1 R153 DY R199 49D9R2F NBSRC_CLK R200 49D9R2F C805 SCD1U16V 1 C803 SCD1U16V NBSRC_CLK# C806 SCD1U16V 2K2R2 FS0 R1492 DUMMY-R2 DY 2K2R2 FS1 R1542 DUMMY-R2 1 C804 SCD1U16V 2 VGA_CORE_S0 DY R169 2K2R2 DY FS2 Wistron Corporation R1602 DUMMY-R2 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C DY Title CLKGEN_IDTCV137 Size A3 Document Number Rev A B C D SA SNIPE Date: Thursday, November 18, 2004 Sheet E of 56 A B C D E C82 SCD22U16V3ZY C83 SCD22U16V3ZY C67 SCD22U16V3ZY 2 C81 SCD22U16V3ZY 1D2V_HT0A_S0 4 HTT for CPU sideB Receive power and NB sideA Transmit power HTT for CPU sideA Transmit power and NB sideA Receive power 1D2V_HT0A_S0 NB0CADOUT15 NB0CADOUTJ15 NB0CADOUT14 NB0CADOUTJ14 NB0CADOUT13 NB0CADOUTJ13 NB0CADOUT12 NB0CADOUTJ12 NB0CADOUT11 NB0CADOUTJ11 NB0CADOUT10 NB0CADOUTJ10 NB0CADOUT9 NB0CADOUTJ9 NB0CADOUT8 NB0CADOUTJ8 NB0CADOUT7 NB0CADOUTJ7 NB0CADOUT6 NB0CADOUTJ6 NB0CADOUT5 NB0CADOUTJ5 NB0CADOUT4 NB0CADOUTJ4 NB0CADOUT3 NB0CADOUTJ3 NB0CADOUT2 NB0CADOUTJ2 NB0CADOUT1 NB0CADOUTJ1 NB0CADOUT0 NB0CADOUTJ0 11 NB0CADOUT[15 0] 11 NB0CADOUTJ[15 0] Used SideB Power Plane 1D2V_HT0A_S0 11 11 11 11 NB0HTTCLKOUT1 NB0HTTCLKOUTJ1 NB0HTTCLKOUT0 NB0HTTCLKOUTJ0 R384 R393 1 49D9R3F 49D9R3F 11 NB0HTTCTLOUT 11 NB0HTTCTLOUTJ T25 R25 U27 U26 V25 U25 W27 W26 AA27 AA26 AB25 AA25 AC27 AC26 AD25 AC25 T27 T28 V29 U29 V27 V28 Y29 W29 AB29 AA29 AB27 AB28 AD29 AC29 AD27 AD28 L0_CADIN_H15 L0_CADIN_L15 L0_CADIN_H14 L0_CADIN_L14 L0_CADIN_H13 L0_CADIN_L13 L0_CADIN_H12 L0_CADIN_L12 L0_CADIN_H11 L0_CADIN_L11 L0_CADIN_H10 L0_CADIN_L10 L0_CADIN_H9 L0_CADIN_L9 L0_CADIN_H8 L0_CADIN_L8 L0_CADIN_H7 L0_CADIN_L7 L0_CADIN_H6 L0_CADIN_L6 L0_CADIN_H5 L0_CADIN_L5 L0_CADIN_H4 L0_CADIN_L4 L0_CADIN_H3 L0_CADIN_L3 L0_CADIN_H2 L0_CADIN_L2 L0_CADIN_H1 L0_CADIN_L1 L0_CADIN_H0 L0_CADIN_L0 VLDT0_B VLDT0_B VLDT0_B VLDT0_B VLDT0_B VLDT0_B VLDT0_B AH29 AH27 AG28 AG26 AF29 AE28 AF25 LAYOUT: Place bypass cap on topside of board near HTT power pins that are not connected directly to HTT device, but connected internally to other HTT power pins VLDT0_A VLDT0_A VLDT0_A VLDT0_A VLDT0_A VLDT0_A VLDT0_A D29 D27 D25 C28 C26 B29 B27 1D2V_HT0B_S0 U13A L0_CADOUT_H15 L0_CADOUT_L15 L0_CADOUT_H14 L0_CADOUT_L14 L0_CADOUT_H13 L0_CADOUT_L13 L0_CADOUT_H12 L0_CADOUT_L12 L0_CADOUT_H11 L0_CADOUT_L11 L0_CADOUT_H10 L0_CADOUT_L10 L0_CADOUT_H9 L0_CADOUT_L9 L0_CADOUT_H8 L0_CADOUT_L8 L0_CADOUT_H7 L0_CADOUT_L7 L0_CADOUT_H6 L0_CADOUT_L6 L0_CADOUT_H5 L0_CADOUT_L5 L0_CADOUT_H4 L0_CADOUT_L4 L0_CADOUT_H3 L0_CADOUT_L3 L0_CADOUT_H2 L0_CADOUT_L2 L0_CADOUT_H1 L0_CADOUT_L1 L0_CADOUT_H0 L0_CADOUT_L0 N26 N27 L25 M25 L26 L27 J25 K25 G25 H25 G26 G27 E25 F25 E26 E27 N29 P29 M28 M27 L29 M29 K28 K27 H28 H27 G29 H29 F28 F27 E29 F29 CPUCADOUT15 CPUCADOUTJ15 CPUCADOUT14 CPUCADOUTJ14 CPUCADOUT13 CPUCADOUTJ13 CPUCADOUT12 CPUCADOUTJ12 CPUCADOUT11 CPUCADOUTJ11 CPUCADOUT10 CPUCADOUTJ10 CPUCADOUT9 CPUCADOUTJ9 CPUCADOUT8 CPUCADOUTJ8 CPUCADOUT7 CPUCADOUTJ7 CPUCADOUT6 CPUCADOUTJ6 CPUCADOUT5 CPUCADOUTJ5 CPUCADOUT4 CPUCADOUTJ4 CPUCADOUT3 CPUCADOUTJ3 CPUCADOUT2 CPUCADOUTJ2 CPUCADOUT1 CPUCADOUTJ1 CPUCADOUT0 CPUCADOUTJ0 C536 downstream SC4D7U10V5ZY CPUCADOUT[15 0] 11 CPUCADOUTJ[15 0] 11 Used SideA Power Plane NB0HTTCLKOUT1 NB0HTTCLKOUTJ1 NB0HTTCLKOUT0 NB0HTTCLKOUTJ0 Y25 W25 Y27 Y28 L0_CLKIN_H1 L0_CLKIN_L1 L0_CLKIN_H0 L0_CLKIN_L0 L0_CLKOUT_H1 L0_CLKOUT_L1 L0_CLKOUT_H0 L0_CLKOUT_L0 J26 J27 J29 K29 CPUHTTCLKOUT1 CPUHTTCLKOUTJ1 CPUHTTCLKOUT0 CPUHTTCLKOUTJ0 CPUHTTCLKOUT1 CPUHTTCLKOUTJ1 CPUHTTCLKOUT0 CPUHTTCLKOUTJ0 CPUHTTCTLIN1 CPUHTTCTLINJ1 NB0HTTCTLOUT NB0HTTCTLOUTJ R27 R26 T29 R29 L0_CTLIN_H1 L0_CTLIN_L1 L0_CTLIN_H0 L0_CTLIN_L0 L0_CTLOUT_H1 L0_CTLOUT_L1 L0_CTLOUT_H0 L0_CTLOUT_L0 N25 P25 P28 P27 CPUHTTCTLOUT0 CPUHTTCTLOUTJ0 CPUHTTCTLOUT0 11 CPUHTTCTLOUTJ0 11 11 11 11 11 62.10030.041 By ME requset U11 P/N: Main 62.10030.041 Second 62.10053.191 Third 62.10053.201 BGA754-SKT-U Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title CPU(1/4)_HyperTransport I/F Size A3 Document Number Rev A B C D SA SNIPE Date: Thursday, November 18, 2004 Sheet E of 56 A B C D E 1D25V_S3 U13B 2D5V_S3 MEMVREF1 R480 R479 34D8R2F 34D8R2F MEMZN MEMZP D14 C14 MEMZN MEMZP VREF_DDR_MEM M_DATA[63 0] NOTE: Test with passive probes only C330 SCD1U VREF_DDR_MEM C422 SC1000P50V2KX 2 R234 100R3F C329 SCD1U R235 100R3F 2D5V_S3 NOTE: Install to bypass op-amp LAYOUT: Locate close to DIMMs NOTE: Remove to bypass op-amp VREF_DDR_CLAW C671 SCD1U VREF_DDR_CLAW C682 SCD1U R506 100R3 1 R500 100R3 2D5V_S3 C693 SC1000P50V2KX M_ADM[7 0] LAYOUT: Locate close to CPU M_DQS[7 0] M_DATA63 M_DATA62 M_DATA61 M_DATA60 M_DATA59 M_DATA58 M_DATA57 M_DATA56 M_DATA55 M_DATA54 M_DATA53 M_DATA52 M_DATA51 M_DATA50 M_DATA49 M_DATA48 M_DATA47 M_DATA46 M_DATA45 M_DATA44 M_DATA43 M_DATA42 M_DATA41 M_DATA40 M_DATA39 M_DATA38 M_DATA37 M_DATA36 M_DATA35 M_DATA34 M_DATA33 M_DATA32 M_DATA31 M_DATA30 M_DATA29 M_DATA28 M_DATA27 M_DATA26 M_DATA25 M_DATA24 M_DATA23 M_DATA22 M_DATA21 M_DATA20 M_DATA19 M_DATA18 M_DATA17 M_DATA16 M_DATA15 M_DATA14 M_DATA13 M_DATA12 M_DATA11 M_DATA10 M_DATA9 M_DATA8 M_DATA7 M_DATA6 M_DATA5 M_DATA4 M_DATA3 M_DATA2 M_DATA1 M_DATA0 A16 B15 A12 B11 A17 A15 C13 A11 A10 B9 C7 A6 C11 A9 A5 B5 C5 A4 E2 E1 A3 B3 E3 F1 G2 G1 L3 L1 G3 J2 L2 M1 W1 W3 AC1 AC3 W2 Y1 AC2 AD1 AE1 AE3 AG3 AJ4 AE2 AF1 AH3 AJ3 AJ5 AJ6 AJ7 AH9 AG5 AH5 AJ9 AJ10 AH11 AJ11 AH15 AJ15 AG11 AJ12 AJ14 AJ16 MEMDATA63 MEMDATA62 MEMDATA61 MEMDATA60 MEMDATA59 MEMDATA58 MEMDATA57 MEMDATA56 MEMDATA55 MEMDATA54 MEMDATA53 MEMDATA52 MEMDATA51 MEMDATA50 MEMDATA49 MEMDATA48 MEMDATA47 MEMDATA46 MEMDATA45 MEMDATA44 MEMDATA43 MEMDATA42 MEMDATA41 MEMDATA40 MEMDATA39 MEMDATA38 MEMDATA37 MEMDATA36 MEMDATA35 MEMDATA34 MEMDATA33 MEMDATA32 MEMDATA31 MEMDATA30 MEMDATA29 MEMDATA28 MEMDATA27 MEMDATA26 MEMDATA25 MEMDATA24 MEMDATA23 MEMDATA22 MEMDATA21 MEMDATA20 MEMDATA19 MEMDATA18 MEMDATA17 MEMDATA16 MEMDATA15 MEMDATA14 MEMDATA13 MEMDATA12 MEMDATA11 MEMDATA10 MEMDATA9 MEMDATA8 MEMDATA7 MEMDATA6 MEMDATA5 MEMDATA4 MEMDATA3 MEMDATA2 MEMDATA1 MEMDATA0 M_ADM8 M_ADM7 M_ADM6 M_ADM5 M_ADM4 M_ADM3 M_ADM2 M_ADM1 M_ADM0 M_DQS8 M_DQS7 M_DQS6 M_DQS5 M_DQS4 M_DQS3 M_DQS2 M_DQS1 M_DQS0 R1 A13 A7 C2 H1 AA1 AG1 AH7 AH13 T1 A14 A8 D1 J1 AB1 AJ2 AJ8 AJ13 MEMDQS17 MEMDQS16 MEMDQS15 MEMDQS14 MEMDQS13 MEMDQS12 MEMDQS11 MEMDQS10 MEMDQS9 MEMDQS8 MEMDQS7 MEMDQS6 MEMDQS5 MEMDQS4 MEMDQS3 MEMDQS2 MEMDQS1 MEMDQS0 D17 A18 B17 C17 AF16 AG16 AH16 AJ17 MEMRESET_L AG10 MEMRESET# AE8 AE7 M_CKE#0 M_CKE#1 M_CKE#0 8,9 M_CKE#1 8,9 D10 C10 E12 E11 AF8 AG8 AF10 AE10 V3 V4 K5 K4 R5 P5 P3 P4 M_CLK7 M_CLK#7 M_CLK6 M_CLK#6 M_CLK5 M_CLK#5 M_CLK4 M_CLK#4 M_CLK7 8,9 M_CLK#7 8,9 M_CLK6 8,9 M_CLK#6 8,9 M_CLK5 8,9 M_CLK#5 8,9 M_CLK4 8,9 M_CLK#4 8,9 MEMCS_L7 MEMCS_L6 MEMCS_L5 MEMCS_L4 MEMCS_L3 MEMCS_L2 MEMCS_L1 MEMCS_L0 D8 C8 E8 E7 D6 E6 C4 E5 M_CS#7 M_CS#6 M_CS#5 M_CS#4 M_CS#3 M_CS#2 M_CS#1 M_CS#0 M_CS#3 M_CS#2 M_CS#1 M_CS#0 MEMRASA_L MEMCASA_L MEMWEA_L H5 D4 G5 M_ARAS# M_ACAS# M_AWE# M_ARAS# 8,9 M_ACAS# 8,9 M_AWE# 8,9 MEMBANKA1 MEMBANKA0 K3 H3 M_ABS#1 M_ABS#0 M_ABS#1 8,9 M_ABS#0 8,9 NC_E13 NC_C12 MEMADDA13 MEMADDA12 MEMADDA11 MEMADDA10 MEMADDA9 MEMADDA8 MEMADDA7 MEMADDA6 MEMADDA5 MEMADDA4 MEMADDA3 MEMADDA2 MEMADDA1 MEMADDA0 E13 C12 E10 AE6 AF3 M5 AE5 AB5 AD3 Y5 AB4 Y3 V5 T5 T3 N5 RSVD_M_AA15 RSVD_M_AA14 M_AA13 M_AA12 M_AA11 M_AA10 M_AA9 M_AA8 M_AA7 M_AA6 M_AA5 M_AA4 M_AA3 M_AA2 M_AA1 M_AA0 MEMRASB_L MEMCASB_L MEMWEB_L H4 F5 F4 M_BRAS# M_BCAS# M_BWE# M_BRAS# 8,9 M_BCAS# 8,9 M_BWE# 8,9 MEMBANKB1 MEMBANKB0 L5 J5 M_BBS#1 M_BBS#0 M_BBS#1 8,9 M_BBS#0 8,9 NC_E14 NC_D12 MEMADDB13 MEMADDB12 MEMADDB11 MEMADDB10 MEMADDB9 MEMADDB8 MEMADDB7 MEMADDB6 MEMADDB5 MEMADDB4 MEMADDB3 MEMADDB2 MEMADDB1 MEMADDB0 E14 D12 E9 AF6 AF4 M4 AD5 AC5 AD4 AA5 AB3 Y4 W5 U5 T4 M3 RSVD_M_BA15 RSVD_M_BA14 M_BA13 M_BA12 M_BA11 M_BA10 M_BA9 M_BA8 M_BA7 M_BA6 M_BA5 M_BA4 M_BA3 M_BA2 M_BA1 M_BA0 MEMCHECK7 MEMCHECK6 MEMCHECK5 MEMCHECK4 MEMCHECK3 MEMCHECK2 MEMCHECK1 MEMCHECK0 N3 N1 U3 V1 N2 P1 U1 U2 MEMCKEA MEMCKEB MEMCLK_H7 MEMCLK_L7 MEMCLK_H6 MEMCLK_L6 MEMCLK_H5 MEMCLK_L5 MEMCLK_H4 MEMCLK_L4 MEMCLK_H3 MEMCLK_L3 MEMCLK_H2 MEMCLK_L2 MEMCLK_H1 MEMCLK_L1 MEMCLK_H0 MEMCLK_L0 AG12 VREF_DDR_CLAW VTT_A VTT_A VTT_A VTT_A VTT_B VTT_B VTT_B VTT_B C653 SCD1U C114 SC1000P50V2KX VTT_SENSE DDRVTT_SENSE AE13 TP75 For REGISTED DIMM Only UNBUFFER DIMM NC 2D5V_S3 RN72 M_CLK#1 M_CLK#0 M_CLK1 M_CLK0 M_CLK1 M_CLK#1 M_CLK0 M_CLK#0 SRN10K-2 8,9 8,9 8,9 8,9 M_AA[13 0] 8,9 AMD suggested M_AA13 connect to DIMM pin123 M_BA[13 0] 8,9 C MEMRESET# M_CS#7 M_CS#6 M_CS#5 M_CS#4 RSVD_M_AA15 RSVD_M_AA14 RSVD_M_BA15 RSVD_M_BA14 TP84 TP82 TP81 TP83 TP87 TP73 TP70 TP72 TP71 CB7 CB6 CB5 CB4 CB3 CB2 CB1 CB0 TP94 TP16 TP95 TP19 TP21 TP22 TP23 TP24 NOT SUPPORT ECC CHECK AMD suggested remove PULL-HI resistor Wistron Corporation Title CPU(2/4)_DDR Size A3 D 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Document Number Rev SA SNIPE Date: Thursday, November 18, 2004 B TP69 TP68 TP18 TP17 AMD suggested M_BA13 connect to DIMM pin123 BGA754-SKT-U A MEMZN MEMZP M_DQS8 M_ADM8 Sheet E of 56 A B C D E 2D5V_CPUA_S0 G913C-U C525 DY SC1U10V3KX C534 SC1000P50V2KX CPUCLK differentially impedance 100 41 41 COREFB COREFB# C584 SC3900P50V3KX CPUCLK# 820R3 820R3 C581 SC3900P50V3KX 1D25V_S3 AE12 AF12 AE11 VDDIOFB_H VDDIOFB_L VDDIO_SENSE CLKIN AJ21 AH21 CLKIN_H CLKIN_L AJ23 AH23 NC_AJ23 NC_AH23 AE24 AF24 NC_AE24 NC_AF24 C16 AG15 VTT_A VTT_B AH17 DBRDY 2D5V_S0 R89 2D5V_S0 DY DY R359 680R3 DY CHANGE FROM 1KR3 TO 680R2 FOR AMD CHECK LIST RN70 NC_AG17 NC_AJ18 NC_D18 SRN680-U RN3 NC_B19 NC_C19 NC_D20 NC_C21 SRN680-U 5 11 13 15 17 19 21 23 C15 NC_C15 TMS TCK TRST_L TDI E20 E17 B21 A21 TMS TCK TRST_L TDI 680R3 NC_C18 C18 NC_C18 NC_A19 A19 NC_A19 680R3 A28 AJ28 10 12 14 16 18 20 22 24 26 A20 THERMDA THERMDC A26 A27 THERMTRIP# THERMDP 23 THERMDN 23 VID[4 0] VID4 VID3 VID2 VID1 VID0 AG13 AF14 AG14 AF15 AE15 VID4 VID3 VID2 VID1 VID0 NC_AG18 NC_AH18 NC_AG17 NC_AJ18 AG18 AH18 AG17 AJ18 NC_AG18 NC_AH18 NC_AG17 NC_AJ18 41 TP62 TP63 LAYOUT: Route FBCLKOUT_H/L differentially impedance 80 KEY1 KEY0 NC_AE23 NC_AF23 NC_AF22 NC_AF21 AE23 AF23 AF22 AF21 NC_AE23 NC_AF23 NC_AF22 NC_AF21 RN67 C1 J3 R3 AA2 D3 AG2 B18 AH1 AE21 C20 AG4 C6 AG6 AE9 AG9 NC_C1 NC_J3 NC_R3 NC_AA2 NC_D3 NC_AG2 NC_B18 NC_AH1 NC_AE21 NC_C20 NC_AG4 NC_C6 NC_AG6 NC_AE9 NC_AG9 SRN680-U DY SMC-CONN26A-FP 20.F0357.025 DY Validation Test Points FBCLKOUT_H FBCLKOUT_L R452 80D6R3F-U AH19 AJ19 FBCLKOUTJ AE19 DBREQJ NC_D20 NC_C21 NC_D18 NC_C19 NC_B19 D20 C21 D18 C19 B19 NC_D20 NC_C21 NC_D18 NC_C19 NC_B19 TDO A22 TDO DBREQ_L NC_AF18 R4512 DUMMY-R3 DY AF18 2D5V_S3 Connect to VDDIO for AMD suggest NC_D22 NC_C22 2D5V_S0 NC_B13 NC_B7 NC_C3 NC_K1 NC_R2 NC_AA3 NC_F3 NC_C23 NC_AG7 NC_AE22 NC_C24 NC_A25 NC_C9 D22 C22 3D3V_S5 R427 680R3 B13 B7 C3 K1 R2 AA3 F3 C23 AG7 AE22 C24 A25 C9 THERMTRIP# R392 10KR2 CPU_THERMTRIP# 21,23 Q26 MMBT3904-U1 NS3 2D5V_S0 R414 1KR3 THERMTRIP#Level shift to SB400 BGA754-SKT-U LAYOUT: Place close to the CPU NC_C15 NC_AE23 NC_AF23 NC_AF22 NC_AF21 TP66 TP51 TP52 TP53 TP54 LDT_RST# CLKIN CLKIN# CORE_SENSE VDDIOFB VDDIOFBJ VDDIOSENSE NC_AE24 NC_AF24 TP60 TP58 TP59 TP56 TP76 TP77 TP74 TP55 TP57 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title CPU(3/4)_Control & Debug Size A3 Document Number Rev B C D SA SNIPE Date: Thursday, November 18, 2004 A FBCLKOUT DY R357 680R3 NC_C15 R358 680R3 DBREQJ DY DBRDY TCK TMS TDI TRST_L TDO 1 RN66 SRN680-U C518 SCD1U R88 C519 DYSCD1UCN5 THERMTRIP_L HDT Connectors 2D5V_S0 Add HDT connector for AMD suggested L0_REF1 L0_REF0 VDDIOFB VDDIOFBJ VDDIOSENSE DBRDY 2 680R3 680R3 680R3 AF27 AE26 COREFB_H COREFB_L CORE_SENSE 2D5V_S0 LDT_RST# SB_CPUPWRGDR441 LDT_STP# R440 R408 RESET_L PWROK LDTSTOP_L A23 A24 B23 CLKIN# NC_AJ23 NC_AH23 NC_AE24 NC_AF24 R428 1 R415 AF20 AE18 AJ27 COREFB COREFB# CORE_SENSE R431 169R3F 2D5V_S3 VDDA1 VDDA2 C535 SC1000P50V2KX L0_REF1 L0_REF0 AMD suggest voltege from 2D5V_S0 to 2D5V_S3 SANYO, NT$:6.1 Iripple=1.1A,ESR=70mohm 3.5/2.8/2.0 77.21071.031 C571 SCD22U16V3ZY13,18 LDT_RST# 18 SB_CPUPWRGD 13,18 LDT_STP# 1 C556 SC3300P50V2KX 44D2R3F R389 2 44D2R3F R388 64.44R25.551 C543 SC4D7U10V5ZY 78.47593.411 1D2V_HT0A_S0 2 TC9 ST100U4VBM-1 KEMET,NT:5.7, B2 size ST100U4VBM-1 (80.10716.321) Iripple=1.1A,ESR=70mohm U13C AH25 AJ25 1 LAYOUT: Route VDDA trace approx 50 mils wide (use 2x25 mil traces to exit ball field) and 500 mils long LAYOUT: Route trace 50 mils wide and 500 to 750 mils long between these caps AMD SUGGEST TO USE 2D5V_CPUA_S0 R2 2D5V_VDDA_S0 L19 0R5J R382 0R3-U DY 63.R0004.151 C524 SC1U10V3KX DY Change L270H 2D5V_CPUA_S0 2D5V_S3 R361 20KR3F C544 SC10U10V5ZY 2 Vout = 1.25*(1+ R1/R2) 1 22D5V_CPUR_S0 0R3-U SET OUT 2D5V_VDDA_VREF R1 SHDN# GND IN DY R360 20KR3F C520 SC22P50V2JN-1 2 R385 Iomax=120mA U51 AMD SUGGEST TO USE 100 ~ 300UH 3D3V_S0 2D5V_S0 2D5V_VDDA_S0 Sheet E of 56 A D E U13D 1 1 1 10u x 2 2 2 2 C100 C109 C101 C106 C108 C92 C93 C115 C116 SCD22U16V3ZY SC10U10V5ZY SC10U10V5ZY SCD22U16V3ZY SCD22U16V3ZY SCD22U16V3ZY SC10U10V5ZY SC10U10V5ZY SCD22U16V3ZY SCD22U16V3ZY 1 C107 LAYOUT: Place on backside of processor 1 2 VCC_CORE_S0 DY 0.22u x DY DY DY C607 C634 C608 C636 C600 C635 SCD22U16V3ZY SCD22U16V3ZY SC10U10V5ZY SCD22U16V3ZY SCD22U16V3ZY SC10U10V5ZY 10u x 2D5V_S3 78.47593.411 2 2 10u x 4.7u x 1D25V_S3 1D25V_S3 1 1 C160 C748 C606 C285 C283 C281 C282 SC10U10V5ZY SC4D7U10V5ZY SC4D7U10V5ZY SC4D7U10V5ZY SC4D7U10V5ZY SC4D7U10V5ZY SC4D7U10V5ZY 2 2 1 1 C164 C177 C176 C175 C174 C731 SCD22U16V3ZY SCD22U16V3ZY SCD22U16V3ZY SCD22U16V3ZY SCD22U16V3ZY SCD22U16V3ZY VCC_CORE_S0 2D5V_S3 C618 C105 C104 C609 SCD22U16V3ZY SCD22U16V3ZY SC4D7U10V5ZY SC4D7U10V5ZY N28 U28 AA28 AE27 R7 U7 W7 K8 M8 P8 T8 V8 Y8 J9 N9 R9 U9 W9 AA9 H10 K10 M10 P10 T10 Y10 AB10 G11 J11 AA11 AC11 H12 K12 Y12 AB12 J13 AA13 AC13 H14 AB26 E28 J28 0.22u x VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD LAYOUT: Place in uPGA socket cavity VCC_CORE_S0 E4 G4 J4 L4 N4 U4 W4 AA4 AC4 AE4 D5 AF5 F6 H6 K6 M6 P6 T6 V6 Y6 AB6 AD6 D7 G7 J7 AA7 AC7 AF7 F8 H8 AB8 AD8 D9 G9 AC9 AF9 F10 AD10 D11 AF11 F12 AD12 D13 AF13 F14 AD14 F16 AD16 D15 R4 VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD L7 AC15 H18 B20 E21 H22 J23 H24 F26 N7 L9 V10 G13 K14 Y14 AB14 G15 J15 AA15 H16 K16 Y16 AB16 G17 J17 AA17 AC17 AE17 F18 K18 Y18 AB18 AD18 AG19 E19 G19 AC19 AA19 J19 F20 H20 K20 M20 P20 T20 V20 Y20 AB20 AD20 G21 J21 L21 N21 R21 U21 W21 AA21 AC21 F22 K22 M22 P22 T22 V22 Y22 AB22 AD22 E23 G23 L23 N23 R23 U23 W23 AA23 AC23 B24 D24 F24 K24 M24 P24 T24 V24 Y24 AB24 AD24 AH24 AE25 K26 P26 V26 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS C 2D5V_S3 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS B VCC_CORE_S0 Y17 K17 H17 F17 E18 AJ26 AE29 AC16 AA16 J16 G16 E16 AH14 AD15 AB15 K15 E15 D16 AE14 AC14 AA14 J14 G14 AF17 AD13 AB13 Y13 K13 H13 F13 AH12 AC12 AA12 G12 B12 AD11 AB11 Y11 K11 H11 F11 AH10 AC10 W10 U10 R10 N10 L10 J10 G10 B10 AD9 Y9 V9 T9 P9 M9 K9 H9 F9 AH8 AC8 W8 U8 R8 N8 L8 J8 G8 B8 AD7 AB7 V7 T7 P7 M7 K7 H7 F7 AH6 AC6 AA6 U6 R6 N6 L6 J6 G6 B6 AH4 B4 AH2 AD2 AB2 Y2 V2 T2 P2 M2 K2 H2 F2 C29 AH28 AF28 AC28 W28 R28 L28 N20 L20 J20 AF19 AD19 AB19 Y19 K19 H19 F19 D19 AC18 AA18 G18 B16 AD17 AB17 H15 F15 G28 D28 B28 C27 AH26 AF26 AD26 Y26 T26 M26 H26 D26 B26 C25 B25 AJ24 AG24 AC24 AA24 W24 U24 R24 N24 J24 G24 E24 AG23 AD23 AB23 Y23 V23 T23 P23 K23 H23 F23 D23 AJ22 AH22 AG22 AC22 AA22 AG29 U22 R22 N22 L22 J22 G22 E22 B22 AG21 AD21 Y21 V21 T21 P21 M21 K21 H21 F21 D21 AJ20 AG20 AE20 AC20 AA20 W20 U20 R20 G20 J18 AE16 Y15 B14 J12 AA10 AB9 AA8 Y7 W6 AF2 D2 AG27 AG25 L24 M23 W22 AB21 AH20 B2 U13E 0.22u x 4.7u x BGA754-SKT-U Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title CPU(4/4)_Power Size A3 BGA754-SKT-U Document Number Rev A B C D SA SNIPE Date: Thursday, November 18, 2004 Sheet E of 56 A B C 13 17 14 18 19 23 29 31 20 24 30 32 41 43 49 53 42 44 50 54 55 59 65 67 56 60 66 68 127 129 135 139 128 130 136 140 141 145 151 153 142 146 152 154 163 165 171 175 164 166 172 176 177 181 187 189 178 182 188 190 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 5,9 M_ARAS# 5,9 M_ACAS# 5,9 M_AWE# VREF_DDR_MEM C304 SCD1U Layout trace 20 mil 3D3V_S0 DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 DM8 12 26 48 62 134 148 170 184 78 M_ADM_R0 M_ADM_R1 M_ADM_R2 M_ADM_R3 M_ADM_R4 M_ADM_R5 M_ADM_R6 M_ADM_R7 CK0 /CK0 CK1 /CK1 CK2 /CK2 35 37 160 158 89 91 DDR_CLK0 DDR_CLK#0 SCL SDA 195 193 SMBC_SB SMBD_SB SA0 SA1 SA2 194 196 198 VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD 10 21 22 33 34 36 45 46 57 58 69 70 81 82 92 93 94 113 114 131 132 143 144 155 156 157 167 168 179 180 191 192 15 16 27 28 38 39 40 51 52 63 64 75 76 87 88 90 103 104 125 126 137 138 149 150 159 161 162 173 174 185 186 202 118 120 119 /RAS /CAS /WE 197 199 VREF VREF VDDSPD VDDID 201 GND GND 85 DM1_RESET# 86 DM1_A13 97 DM1_BA2 98 M_AA13 123 124 200 M_DQS_R0 M_DQS_R1 M_DQS_R2 M_DQS_R3 M_DQS_R4 M_DQS_R5 M_DQS_R6 M_DQS_R7 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 71 73 79 83 72 74 80 84 TP111 TP33 TP110 DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS8 11 25 47 61 133 147 169 183 77 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 NC NC/(RESET#) NC/A13 NC/BA2 NC NC NC M_CKE#0 M_CKE#0 5,9 M_ADM#0 M_ADM#1 M_ADM#2 M_ADM#3 M_ADM#4 M_ADM#5 M_ADM#6 M_ADM#7 M_CLK5 5,9 M_CLK#5 5,9 M_CLK7 5,9 M_CLK#7 5,9 2D5V_S3 NOT SUPPORT ECC CHECK AMD suggested pull-low M_BA0 M_BA1 M_BA2 M_BA3 M_BA4 M_BA6 M_BA5 M_BA7 M_BA8 M_BA9 M_BA10 M_BA11 M_BA12 112 111 110 109 108 107 106 105 102 101 115 100 99 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 / AP A11 A12 M_BBS#0 M_BBS#1 117 116 BA0 BA1 M_DATA_R_0 M_DATA_R_1 M_DATA_R_2 M_DATA_R_3 M_DATA_R_4 M_DATA_R_5 M_DATA_R_6 M_DATA_R_7 M_DATA_R_8 M_DATA_R_9 M_DATA_R_10 M_DATA_R_11 M_DATA_R_12 M_DATA_R_13 M_DATA_R_14 M_DATA_R_15 M_DATA_R_16 M_DATA_R_17 M_DATA_R_18 M_DATA_R_19 M_DATA_R_20 M_DATA_R_21 M_DATA_R_22 M_DATA_R_23 M_DATA_R_24 M_DATA_R_25 M_DATA_R_26 M_DATA_R_27 M_DATA_R_28 M_DATA_R_29 M_DATA_R_30 M_DATA_R_31 M_DATA_R_32 M_DATA_R_33 M_DATA_R_34 M_DATA_R_35 M_DATA_R_36 M_DATA_R_37 M_DATA_R_38 M_DATA_R_39 M_DATA_R_40 M_DATA_R_41 M_DATA_R_42 M_DATA_R_43 M_DATA_R_44 M_DATA_R_45 M_DATA_R_46 M_DATA_R_47 M_DATA_R_48 M_DATA_R_49 M_DATA_R_50 M_DATA_R_51 M_DATA_R_52 M_DATA_R_53 M_DATA_R_54 M_DATA_R_55 M_DATA_R_56 M_DATA_R_57 M_DATA_R_58 M_DATA_R_59 M_DATA_R_60 M_DATA_R_61 M_DATA_R_62 M_DATA_R_63 13 17 14 18 19 23 29 31 20 24 30 32 41 43 49 53 42 44 50 54 55 59 65 67 56 60 66 68 127 129 135 139 128 130 136 140 141 145 151 153 142 146 152 154 163 165 171 175 164 166 172 176 177 181 187 189 178 182 188 190 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 M_BRAS# M_BCAS# M_BWE# VREF_DDR_MEM Layout trace 20 mil C381 SCD1U 3D3V_S0 CKE0 CKE1 DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS8 11 25 47 61 133 147 169 183 77 M_DQS_R0 M_DQS_R1 M_DQS_R2 M_DQS_R3 M_DQS_R4 M_DQS_R5 M_DQS_R6 M_DQS_R7 DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 DM8 12 26 48 62 134 148 170 184 78 M_ADM_R0 M_ADM_R1 M_ADM_R2 M_ADM_R3 M_ADM_R4 M_ADM_R5 M_ADM_R6 M_ADM_R7 CK0 /CK0 CK1 /CK1 CK2 /CK2 35 37 160 158 89 91 SCL SDA 195 193 SA0 SA1 SA2 194 196 198 VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD 10 21 22 33 34 36 45 46 57 58 69 70 81 82 92 93 94 113 114 131 132 143 144 155 156 157 167 168 179 180 191 192 15 16 27 28 38 39 40 51 52 63 64 75 76 87 88 90 103 104 125 126 137 138 149 150 159 161 162 173 174 185 186 201 118 120 119 /RAS /CAS /WE 197 199 VREF VREF VDDSPD VDDID 202 GND GND 85 DM2_RESET# 86 DM2_A13 97 DM2_BA2 98 M_BA13 123 124 200 5,9 M_BRAS# 5,9 M_BCAS# 5,9 M_BWE# 121 122 96 95 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 71 73 79 83 72 74 80 84 TP41 TP119 TP40 /CS0 /CS1 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 NC NC/(RESET#) NC/A13 NC/BA2 NC NC NC M_CS#2 5,9 M_CS#3 5,9 M_CKE#1 M_CKE#1 5,9 M_ADM_R[7 0] M_DATA_R_[63 0] M_ADM#0 M_ADM#1 M_ADM#2 M_ADM#3 M_ADM#4 M_ADM#5 M_ADM#6 M_ADM#7 M_DQS_R[7 0] M_ABS#[1 0] 5,9 M_BA[13 0] 5,9 M_BBS#[1 0] 5,9 DDR_CLK1 DDR_CLK#1 M_CLK4 5,9 M_CLK#4 5,9 M_CLK6 5,9 M_CLK#6 5,9 SMBC_SB 3,21 SMBD_SB 3,21 DM2_SA0 R233 4K7R3 DDR-SODIMM-N-U1 B C 3D3V_S0 2D5V_S3 DDR_CLK#1 DDR_CLK#0 DDR_CLK1 DDR_CLK0 RN41 SRN10K-2 DY AMD K8 ClawHummar MD63 SMA11 2D5V_S3 SMA10 SMA0 SMA14 MD0 SMA12 DDR SOCKET PLACEMENT TOP VIEW PERSPECTIVE DRAWING By ME requset DM1 P/N: Main 62.10017.191 Second 62.10017.381 DM1 Pin 199 Pin Pin 200 Pin DM2(Reverse) By ME requset DM2 P/N: Main 62.10017.201 Second 62.10017.371 Third 62.10017.701 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title DDR SO-DIMM SKT Size A3 DDR-SODIMM-R-U2 A M_AA[13 0] 5,9 Pin M_DATA_R_0 M_DATA_R_1 M_DATA_R_2 M_DATA_R_3 M_DATA_R_4 M_DATA_R_5 M_DATA_R_6 M_DATA_R_7 M_DATA_R_8 M_DATA_R_9 M_DATA_R_10 M_DATA_R_11 M_DATA_R_12 M_DATA_R_13 M_DATA_R_14 M_DATA_R_15 M_DATA_R_16 M_DATA_R_17 M_DATA_R_18 M_DATA_R_19 M_DATA_R_20 M_DATA_R_21 M_DATA_R_22 M_DATA_R_23 M_DATA_R_24 M_DATA_R_25 M_DATA_R_26 M_DATA_R_27 M_DATA_R_28 M_DATA_R_29 M_DATA_R_30 M_DATA_R_31 M_DATA_R_32 M_DATA_R_33 M_DATA_R_34 M_DATA_R_35 M_DATA_R_36 M_DATA_R_37 M_DATA_R_38 M_DATA_R_39 M_DATA_R_40 M_DATA_R_41 M_DATA_R_42 M_DATA_R_43 M_DATA_R_44 M_DATA_R_45 M_DATA_R_46 M_DATA_R_47 M_DATA_R_48 M_DATA_R_49 M_DATA_R_50 M_DATA_R_51 M_DATA_R_52 M_DATA_R_53 M_DATA_R_54 M_DATA_R_55 M_DATA_R_56 M_DATA_R_57 M_DATA_R_58 M_DATA_R_59 M_DATA_R_60 M_DATA_R_61 M_DATA_R_62 M_DATA_R_63 CKE0 CKE1 96 95 M_CS#0 5,9 M_CS#1 5,9 Pin BA0 BA1 121 122 Pin 200 117 116 E Pin 199 M_ABS#0 M_ABS#1 /CS0 /CS1 REVERSE TYPE A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 / AP A11 A12 112 111 110 109 108 107 106 105 102 101 115 100 99 M_AA0 M_AA1 M_AA2 M_AA3 M_AA4 M_AA6 M_AA5 M_AA7 M_AA8 M_AA9 M_AA10 M_AA11 M_AA12 D DM2 NORMAL TYPE DM1 Document Number Rev D SA SNIPE Date: Thursday, November 18, 2004 Sheet E of 56 A B C D SERIES DAMPING PARALLEL TERMINATION PLACE RNs CLOSE TO FIRST DM ( DM1 ), < 0.75" STRICT EQUAL LENGTH LIMITATION WITH DQS, CB PINS RN21 M_DATA4 M_DATA5 M_ADM0 M_DATA6 M_DATA7 M_DATA13 M_DATA12 M_ADM1 16 15 14 13 12 11 10 M_DATA_R_4 M_DATA_R_5 M_ADM_R0 M_DATA_R_6 M_DATA_R_7 M_DATA_R_13 M_DATA_R_12 M_ADM_R1 M_DATA34 M_DATA32 M_DQS4 M_DATA33 M_DATA36 M_DATA37 M_ADM4 M_DATA39 PULL HIGH STUBS < 0.8", PLACE RPs CLOSE TO SECOND DM ( DM2 ) NO EQUAL LENGTH LIMITATION 1D25V_S3 16 15 14 13 12 11 10 M_DATA_R_1 M_DATA_R_0 M_DQS_R0 M_DATA_R_2 M_DATA_R_3 M_DATA_R_8 M_DATA_R_9 M_DQS_R1 M_DATA35 M_DATA41 M_DATA40 M_DQS5 M_DATA42 M_DATA43 M_DATA49 M_DATA48 16 15 14 13 12 11 10 M_DATA_R_14 M_DATA_R_15 M_DATA_R_21 M_DATA_R_20 M_ADM_R2 M_DATA_R_23 M_DATA_R_22 M_DATA_R_25 M_DATA38 M_DATA45 M_DATA44 M_ADM5 M_DATA47 M_DATA46 M_DATA53 M_DATA52 16 15 14 13 12 11 10 M_DATA_R_11 M_DATA_R_10 M_DATA_R_17 M_DATA_R_16 M_DQS_R2 M_DATA_R_19 M_DATA_R_18 M_DATA_R_24 M_DQS6 M_DATA50 M_DATA51 M_DATA56 M_DATA57 M_DQS7 M_DATA58 M_DATA59 M_DATA_R_38 M_DATA_R_45 M_DATA_R_44 M_ADM_R5 M_DATA_R_47 M_DATA_R_46 M_DATA_R_53 M_DATA_R_52 M_DQS_R6 M_DATA_R_50 M_DATA_R_51 M_DATA_R_56 M_DATA_R_57 M_DQS_R7 M_DATA_R_58 M_DATA_R_59 16 15 14 13 12 11 10 SRN10J-3 RN19 16 15 14 13 12 11 10 RN27 SRN10J-3 M_DATA29 M_DATA28 M_DQS3 M_ADM3 M_DATA26 M_DATA27 M_DATA30 M_DATA31 16 15 14 13 12 11 10 M_DATA_R_29 M_DATA_R_28 M_DQS_R3 M_ADM_R3 M_DATA_R_26 M_DATA_R_27 M_DATA_R_30 M_DATA_R_31 SRN10J-3 M_ADM6 M_DATA54 M_DATA55 M_DATA61 M_DATA60 M_ADM7 M_DATA62 M_DATA63 RN16 RN38 16 15 14 13 12 11 10 M_DATA_R_1 M_DATA_R_0 M_DQS_R0 M_DATA_R_2 M_DATA_R_3 M_DATA_R_8 M_DATA_R_9 M_DQS_R1 M_ADM_R6 M_DATA_R_54 M_DATA_R_55 M_DATA_R_61 M_DATA_R_60 M_ADM_R7 M_DATA_R_62 M_DATA_R_63 16 15 14 13 12 11 10 M_DATA_R_25 M_DATA_R_22 M_DATA_R_23 M_ADM_R2 M_DATA_R_20 M_DATA_R_21 M_DATA_R_14 M_DATA_R_15 16 15 14 13 12 11 10 8 M_DATA_R_30 M_DATA_R_31 M_DATA_R_26 M_DATA_R_27 M_ADM_R3 M_DQS_R3 M_DATA_R_29 M_DATA_R_28 M_DATA_R_36 M_DATA_R_32 M_DATA_R_37 M_DATA_R_33 M_ADM_R4 M_DQS_R4 M_DATA_R_38 M_DATA_R_39 16 15 14 13 12 11 10 1 16 15 14 13 12 11 10 SRN68J-1 RN42 M_CKE#0 M_AA12 M_ADM[7 0] M_DATA[63 0] M_DATA_R_[63 0] M_DATA_R_48 M_DATA_R_49 M_DATA_R_43 M_DATA_R_42 M_DQS_R5 M_DATA_R_41 M_DATA_R_40 M_DATA_R_34 16 15 14 13 12 11 10 M_DATA_R_35 M_DATA_R_46 M_DATA_R_47 M_ADM_R5 M_DATA_R_44 M_DATA_R_45 M_DATA_R_53 M_DATA_R_52 16 15 14 13 12 11 10 M_DATA_R_59 M_DATA_R_58 M_DQS_R7 M_DATA_R_57 M_DATA_R_56 M_DATA_R_51 M_DATA_R_50 M_DQS_R6 16 15 14 13 12 11 10 M_DATA_R_55 M_DATA_R_54 M_ADM_R6 M_DATA_R_60 M_DATA_R_61 M_ADM_R7 M_DATA_R_63 M_DATA_R_62 SRN68J-1 16 15 14 13 12 11 10 M_CS#3 M_BA13 M_CS#2 M_BRAS# M_BBS#1 M_BCAS# M_BA0 M_BA2 SRN47J-1-U RN39 16 15 14 13 12 11 10 M_AA1 M_AA10 M_AA2 M_AA0 M_ABS#1 M_ARAS# M_AWE# M_ABS#0 SRN47J-1-U RN30 16 15 14 13 12 11 10 M_BA7 M_BA3 M_BA6 M_BA9 M_BA10 M_BA1 M_BBS#0 M_BWE# SRN47J-1-U RN49 16 15 14 13 12 11 10 M_BA5 M_BA8 M_BA11 M_BA4 SRN10J-3 M_DQS_R[7 0] RN31 M_AA11 M_AA9 M_AA7 M_AA5 M_AA4 M_AA8 M_AA6 M_AA3 4 M_DQS[7 0] SRN47J 16 15 14 13 12 11 10 SRN68J-1 RN36 SRN68J-1 SRN47J RN32 SRN68J-1 RN47 16 15 14 13 12 11 10 M_ADM_R[7 0] RN50 M_CKE#1 M_BA12 SRN68J-1 RN37 SRN68J-1 RN51 M_DATA_R_11 M_DATA_R_10 M_DATA_R_16 M_DATA_R_17 M_DQS_R2 M_DATA_R_19 M_DATA_R_18 M_DATA_R_24 16 15 14 13 12 11 10 SRN68J-1 RN48 SRN68J-1 RN43 SRN10J-3 RN33 M_DATA11 M_DATA10 M_DATA17 M_DATA16 M_DQS2 M_DATA19 M_DATA18 M_DATA24 M_DATA_R_35 M_DATA_R_41 M_DATA_R_40 M_DQS_R5 M_DATA_R_42 M_DATA_R_43 M_DATA_R_49 M_DATA_R_48 RN17 SRN10J-3 16 15 14 13 12 11 10 SRN10J-3 RN20 M_ADM_R1 M_DATA_R_13 M_DATA_R_12 M_DATA_R_6 M_DATA_R_7 M_ADM_R0 M_DATA_R_5 M_DATA_R_4 SRN68J-1 RN52 RN28 SRN10J-3 M_DATA14 M_DATA15 M_DATA21 M_DATA20 M_ADM2 M_DATA23 M_DATA22 M_DATA25 M_DATA_R_34 M_DATA_R_32 M_DQS_R4 M_DATA_R_33 M_DATA_R_36 M_DATA_R_37 M_ADM_R4 M_DATA_R_39 16 15 14 13 12 11 10 SRN10J-3 RN34 1D25V_S3 RN44 RN18 SRN10J-3 M_DATA1 M_DATA0 M_DQS0 M_DATA2 M_DATA3 M_DATA8 M_DATA9 M_DQS1 E M_AA[13 0] 5,8 M_ABS#[1 0] 5,8 M_BA[13 0] 5,8 M_BBS#[1 0] 5,8 M_AWE# 5,8 M_ACAS# 5,8 M_ARAS# 5,8 M_BWE# 5,8 M_BCAS# 5,8 M_BRAS# 5,8 M_CS#0 M_CS#1 M_CS#2 M_CS#3 5,8 5,8 5,8 5,8 SRN47J-1-U RN40 SRN47-1 2 M_AA13 M_CS#0 M_CS#1 M_ACAS# RN29 SRN47-1 Place it near CPU 5,8 M_CKE#0 M_CKE#0 5,8 M_CKE#1 M_CKE#1 05/10 Remove the damping resistor for AMD suggest R498 121R3F M_CLK7 M_CLK#7 M_CLK7 5,8 M_CLK#7 5,8 R481 121R3F M_CLK6 M_CLK#6 M_CLK6 5,8 M_CLK#6 5,8 R499 121R3F M_CLK5 M_CLK#5 M_CLK5 5,8 M_CLK#5 5,8 R486 121R3F M_CLK4 M_CLK#4 M_CLK4 5,8 M_CLK#4 5,8 1 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title DDR DAMPING & TERMINATION Size A3 Document Number Date: Thursday, November 18, 2004 A B C D Rev SA SNIPE Sheet E of 56 A B DY DY E DY DY SCD1U SCD1U 2 C452 C454 SCD1U C451 DY C325 C378 SCD1U SCD1U SCD1U DY SCD1U C416 DY C324 C379 SCD1U 2 SCD1U SCD1U C415 C449 C414 SCD1U SCD1U SCD1U C447 DY C450 C448 SCD1U 2 SCD1U SCD1U C413 C445 C328 SCD1U SCD1U SCD1U C443 DY C446 2 C327 SCD1U SCD1U SCD1U C441 C444 2 SCD1U C409 SCD1U SCD1U C439 DY C442 C410 SCD1U 1 SCD1U SCD1U C440 C437 SCD1U 1 C435 SCD1U SCD1U C291 DY C438 C436 SCD1U SCD1U C290 2 D LAYOUT:Place altemating caps to GND and 2D5_S3 2D5V_S3 1D25V_S3 C C453 SCD1U DY 3 2D5V_S3 SCD1U C284 SCD1U DY DY DY DY C268 SCD1U C280 DY SCD1U C207 SCD1U DY DY C248 SCD1U C263 SCD1U C390 SCD1U C430 SCD1U C434 SCD1U C165 SCD1U 2 SCD1U 1 C460 C423 SCD1U 1 C269 SCD1U C275 SCD1U C245 DY 2 C288 SCD1U SCD1U SCD1U C319 C376 SCD1U SCD1U C399 SCD1U C407 DY C235 2 2 C310 SCD1U SCD1U SCD1U C208 C254 SCD1U SCD1U C355 SCD1U C293 DY C408 2 C228 SCD1U SCD1U SCD1U C356 C249 2 SCD1U C459 SCD1U SCD1U C420 DY C292 C345 SCD1U 1 SCD1U SCD1U C421 C457 SCD1U 1 C418 SCD1U SCD1U C455 DY C458 C419 SCD1U SCD1U C456 2 1D25V_S3 1D25V_S3 DY DY DY DY DY DY DY 2 LAYOUT:Place close to Power Pin of DDR socket 2D5V_S3 LAYOUT:Place at end of the DIMMs C917 C302 SCD22U16V3ZY C323 SCD22U16V3ZY C303 SCD22U16V3ZY SC22U10V6ZY-U C925 SC22U10V6ZY-U C880 SC22U10V6ZY-U C872 TC28 ST100U4VBM-1 SC22U10V6ZY-U TC27 ST100U4VBM-U 2D5V_S3 C301 SCD22U16V3ZY 2 1D25V_S3 DY C380 SCD22U16V3ZY C377 DY SCD22U16V3ZY DY C326 SCD22U16V3ZY C411 DY SCD22U16V3ZY C412 SCD22U16V3ZY C417 SCD22U16V3ZY 0.22u x 10 1 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title DDR DECOUPLING Size A3 Document Number Rev A B C D SA SNIPE Date: Thursday, November 18, 2004 Sheet E 10 of 56 A B C D E C789 SC10U35V0ZY-U DY DCBATOUT_ISL 4 C229 2 C788 ISL6559_UG3 ISL6559_PHASE_3 U70 L7 Power-PAK Id=7A Qg=10~15nC Rdson=13~16.5mohm NC2 NC1 U69 SI7392DP 84.07392.037 VCC_CORE_S0 L-D48UH-U 4 2 C236 SC1U10V3KX 1 D29 SSM54-U DY Power-PAK Id=13A Qg=32~50nC Rdson=4~4.8mohm R564 2KR3F 2 2 U22 SI7636DP 84.07636.037 S S S G C785 S S S G R556 DUMMY-R3 SCD01U50V3KX U67 SI7636DP 84.07636.037 R560 0R3-U ISL6207CB-U 74.06207.071 ISL6559_LG_3 ISL6207_EN3 PHASE EN VCC LGATE UGATE BOOT PWM GND D D D D R579 499KR3F D D D D ISL6559_PWM2 4 SCD22U16V3KX-1 41 ISL6559_PWM2 8 1 BOOT_3# S S S G S S S G 2D2R3 D D D D D D D D R566 U24 SI7392DP 84.07392.037 C166 C761 SCD1U50V3ZY DY SCD1U50V3ZY 5V_S0 DCR=1.3mohm+-10% / Imax=40A / Panasonic / ETQP2H0R7BF / 0.48uH / 13.4*13.3*4.9 DUMMY-C3 Follow MOSFET rise time spec BOOT_3 2 1 SB Version: Change U68 from ISL6209CB (74.06209.071) to ISL6207CB-U (74.06207.071) ISEN2 ISEN2 41 2 1 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title CPU Vcore Power_2 Size A3 Document Number Rev A B C D SA SNIPE Date: Thursday, November 18, 2004 Sheet E 42 of 56 5V_DC_S5 GAP-OPEN-PWR GAP-OPEN-PWR G75 GAP-OPEN-PWR G76 GAP-OPEN-PWR G71 GAP-OPEN-PWR GAP-OPEN-PWR DCBATOUT_MAX1999_1 MAX1999_LDO5 4D7R5 OUT5 21 MAX1999_SD_3 MAX1999_ON5 MAX1999_SHDN# FB3 ON3 ON5 SHDN# FB5 R273 10 PRO# NC MAX1999_PRO#1 100KR3 MAX1999_ILIM5 ILIM3 MAX1999_ILIM3 MAX1999_PGD C357 SC1U25V5ZY C401 30mA MAX SC1U25V5ZY 2 MAX1999_VCC MAX1999_SHDN# SC: 3.3V R186=>20KR3F OCP: Main Source Adapter=10.6A Battery=10.4A Second Source Adapter=9.4A Battery=9.2A C382 SC: 5V R214=>40K2R3F OCP: Main Source Adapter=12.6A Battery=11.6A Second Source Adapter=16.4A Battery=14.4A SCD1U MAX1999_ILIM5 G S5PWR_ENABLE 23,44 R648 100KR3 R282 10KR3F R244 10KR3F 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title 5V_UP_S5/3D3V_S5/5V_S5 2N7002 Wistron Corporation D C346 SC4D7U10V5ZY DY Q40 PM_SLP_S3# 18,21,34,38,39,44,55 Size A3 Adjust 3V/5V current limit Document Number Date: Thursday, November 18, 2004 B 100KR3 MAX1999_ILIM3 S A R248 TPAD30 0R3-U Q32_D MAX1999_SD_3 TP112 0R3-U R240 2 MAX1999_SKIP# 1 R272 MAX1999_ILIM5_3 R241 MAX1999_ON5 Open Drian GAP-CLOSE-PWR R647 100KR3 2 U93 2N7002DW R301 9K76R3F 20KR3F 1 30mA MAX MAX1999_LDO5 R274 MAX1999_LDO5 2 R243 10KR3 OCP Setting 3D3V_AUX_S5 R281 100KR3 8K66R3F MAX1999EEI R673 25 R687 DUMMY-R3 23 GND LDO5 SKIP# 18 12 LDO3 PGOOD C424 SC100P50V2JN 15KR3F MAX1999_FB5 DY REF MAX1999_LDO5 R271 100KR3 R300 KEMET, NT:8.5 ESR=25mohm Iripple=2.2A 7.3/4.3/1.9 11 MAX1999_SKIP# MAX1999_ILIM5_3 MAX1999_VCC R260 NC,SO-8 2MR3 Id=9.6A DY Rdson=13.5~16.5mohm TC26 ST220U6D3VDM-4 80.22715.191 ILIM5 DUMMY-R3 Ton = VCC : 200KHz/300KHz Ton = GND : 400KHz/500KHz (5V/3D3V) MAX1999_VCC C875 DUMMY-C3 R283 13 TON MAX1999_TON 10KR3 R284 MAX1999_VCC R236 10K2R3F C391 SC47P50V2JN U95 MAX1999_LX5_1 AO4406 84.04406.037 MAX1999_FB3 C881 SCD22U16V3ZY MAX1999_SKIP G S S S MAX1999_FB5 OUT3 22 IND-6D8UH-14 68.6R810.10A MAX1999_DL5 19 5V_DC_S5 15 DL5 Imax=6.0A, DCR=25mohm 12*12*3.9 LX5 DL3 L30 Iomax=6A OCP:12~14A LX3 24 NC,SO-8 Id=9.3A Rdson=19.6~24mohm MAX1999_LX5 27 MAX1999_DL3 GAP-OPEN-PWR U89 AO4422 84.04422.037 MAX1999_DH5 1 D D D D 16 VCC DH5 MAX1999_LX3 2 BST5 DH3 MAX1999_BST5_1 14 26 MAX1999_REF C892 SCD1U C895 SCD1U C894 SC10U35V0ZY-U S S S G KEMET, NT=6.6 ST150U6D3VDM-9 80.15715.191 ESR=40mohm Iripple=1.7A 7.3/4.3/1.9 1 MAX1999_BST3_1 28 BST3 R261 2MR3 DY R242 6K65R3F GAP-CLOSE-PWR C893 SC4D7U25V6KX DY 1 MAX1999_LX3_1 2 1 1 DUMMY-C3 ST150U6D3VDM-9 80.15715.191 C392 SC47P50V2JN U39 R699 GAP-CLOSE-PWR D D D D Imax=6.0A, DCR=25mohm 12*12*3.9 C347 SC100P50V2JN MAX1999_BST5 R661 MAX1999_DH3 TC24 78.47522.521 V+ NC,SO-8 Id=9.3A Rdson=19.6~24mohm C874 SCD1U 300KR3 L27 C876 DCBATOUT_MAX1999 D38 BAW56 G S S S U82 AO4422 84.04422.037 3D3V_DC_S5 IND-6D8UH-14 68.6R810.10A C882 SC1U10V3KX SCD1U 20 D D D D Iomax=4.0A OCP:8A~9.5A MAX1999_BST3 R672 10R3 NC,SO-8 Id=9.3A Rdson=19.6~24mohm SC1U25V5ZY U88 AO4422 84.04422.037 C393 G S S S GAP-OPEN-PWR 1 C400 C855 C854 DY SCD1U50V5ZY SC10U35V0ZY-U GAP-OPEN-PWR D D D D MAX1999_VCC R688 GAP-OPEN-PWR G1142 DCBATOUT_MAX1999 R249 DCBATOUT_MAX1999 GAP-OPEN-PWR G1202 GAP-OPEN-PWR G1152 1 3D3V_S5 GAP-OPEN-PWR G60 2 GAP-OPEN-PWR G1122 5V_S5 GAP-OPEN-PWR G1182 17 3D3V_DC_S5 DCBATOUT_MAX1999 G1112 G1172 GAP-OPEN-PWR G1192 GAP-OPEN-PWR G66 GAP-OPEN-PWR G1132 G116 E GAP-OPEN-PWR G65 DCBATOUT D G67 G104 C SYSTEM DC/DC 3D3V_S5/5V_S5 G70 B A C D Rev SA SNIPE Sheet E 43 of 56 1 5130_FB2 1 5130_TRIP2 5130_TRIP2 R704 5130_OUT1U 45 5130_OUT1D 45 R307 100KR2 R308 2N7002DW C465 84.27002.03F SC4700P50V3KX PM_SLP_S3# 5130_FB1 5130_SS_STBY1 5130_INV2 5130_FB2 5130_SS_STBY2 5130_PWMSEL 5130_CT DUMMY-R2 ZZ.DUMMY.X02 R731 DCBATOUT_5130 5130_REF STBY_REF 5130_STBY_LDO 100KR2 C879 5130_LH2 FB1 SS_STBY1 INV2 FB2 SS_STBY2 PWM_SEL CT GND REF STBY_VREF5 STBY_VREF3.3 STBY_LDO LL2 OUT2_U LH2 VIN VREF3.3 VREF5 REG5V_IN LDO_IN LDO_CUR LDO_GATE LDO_OUT INV_LDO TPS5130 5V_AUX_S5 TPS5130_1D5V_EN# 100KR2 S5PWR_ENABLE 5130_SS_STBY3 C927 SCD1U 5130_5V_LDO 5130_3D3V_LDO 5130_REGIN R685 0R5J-1 5130_3D3V_LDO 5V_S5 C394 SC4D7U10V5ZY 78.47593.411 C406 SC4D7U10V5ZY 78.47593.411 SS_STBY3 FB3 INV3 PGOUT PG_DELAY TRIP3 VIN_SENSE3 LH3 OUT3_U LL3 OUT3_D OUTGND3 5V_S0 5130_OUT3D 45 5130_OUT3U 45 5130_LL3 45 C885 SCD1U50V3KX 5130_5V_LDO D37 BAT54-1 83.00054.L03 PWM_SEL * Condition Voltage H : Auto PWM/SKIP 2.2V(Min)~ L : PWM fixed (300KHz) ~0.3V(Max) DCBATOUT_5130 5130_TRIP3 A R299 0R2-0 5130_PG_DELAY R298 10KR2 C922 SC4700P50V3KX 78.47224.2B1 TPS5130PT-U 5130_LH3 1 2N7002DW 84.27002.03F R306 0R2-0 63.R0034.1D1 5130_STBY_LDO C428 DY Wistron Corporation DUMMY-C3 ZZ.DUMMY.XC3 R305 0R2-0 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C PM_SLP_S3# PM_SLP_S3# Title TI TPS5130 2D5V/1D2V/1D8V (1/2) ,34,38,39,43,55 DCBATOUT_5130 C395 5130_OUT2U 45 SCD1U50V3KX 5130_OUT3D 5130_LL3 5130_OUT3U 5130_REF A close to IC 5130_OUT2U 5130_SS_STBY3 5130_FB3 5130_INV3 5130_LL2 45 B 13 14 15 16 17 18 19 20 21 22 23 24 C924 SC47P50V2JN 78.47034.1F1 U44 R320 5130_LL2 LDO SETTING S5PWR_ENABLE 5130_CT 36 35 34 33 32 31 30 29 28 27 26 25 1D2V_S0_EN 23,43 S5PWR_ENABLE C SCD1U50V3KX B 10 11 12 GAP-CLOSE ZZ.CON2C.XX1 5130_OUT2D 45 1D2V_S0_EN G121 U94 INV1 FLT LH1 OUT1_U LL1 OUT1_D OUTGND1 TRIP1 VIN_SENSE12 TRIP2 OUTGND2 OUT2_D 1 5130_SS_STBY1 OCP 8.4A=>R229=12.65K 10A=>R229=22K 2 R309 100KR2 5130_SS_STBY2 1 ,34,38 PM_SLP_S5# 5130_OUT2D 48 47 46 45 44 43 42 41 40 39 38 37 SC4700P50V3KX 5130_3D3V_LDO close to IC U45 39 1D2V_S0_EN C889 22K1R3F SCD1U T(soft)=1.736ms DCBATOUT_5130 5130_FLT 5130_FLT 5130_INV1 GAP-OPEN-PWR DCBATOUT_5130 5130_FB1 C916 SCD01U16V2KX GAP-OPEN-PWR G68 OCP 8.4A=>R226=13K 10A=>R226=22K 1D8V_OCP 5130_TRIP3 C466 2 close to IC 5130_LL1 45 5130_TRIP1 5130_INV1 GAP-OPEN-PWR G69 SCD1U 5130_LL1 SCD1U50V3KX 5130_OUT1U 5130_OUT1D C DCBATOUT_5130 D GAP-OPEN-PWR G62 C886 22K1R3F D36 BAT54-1 83.00054.L03 C907 close to IC C930 SC3900P50V3KX R698 5130_LH1 R734 2KR3 63.20234.151 GAP-OPEN-PWR G61 1D2V_OCP 5130_INV2 C931 5130_5V_LDO D39 BAT54-1 83.00054.L03 close to IC 330R2F SC5600P50V3KX 78.56224.2B1 R312 19K6R3F 10KR2F-U OCP 12A=>R225=18K 18A=>R225=28K R314 2 close to IC 1 2D5V_PWR R735 C890 28K7R3F SCD1U GAP-OPEN-PWR G56 5130_5V_LDO 2KR3 63.20234.151 C928 SC3900P50V3KX R732 5130_FB3 For 2.5V SETTING=2.516V 10KR2F-U 5130_INV3 C923 SC3900P50V3KX close to IC 5130_TRIP1 2KR3 63.20234.151 C929 330R2F SC5600P50V3KX 78.56224.2B1 R310 4K32R3F DCBATOUT_5130 G57 DCBATOUT_5130 1D2V_PWR R733 R311 R705 For 1.2V SETTING=1.2172V R727 D DCBATOUT 2D5V_OCP (2D5V=>CH1 , 1D2V=>CH2 , 1D8V =>CH3) 680R3F SC5600P50V3KX 78.56224.2B1 R303 11K5R3F 10KR2F-U Vo=(R1*0.85)/R2+0.85 C906 R304 R726 TI TPS5130 for 2.5V, 1.2V, 1.8V 1D8V_PWR For 1.8V SETTING=1.8275V Size A3 Document Number Rev SNIPE Date: Thursday, November 18, 2004 SA Sheet 44 of 56 TI TPS5130 for 2D5V, 1D2V, 1D8V 2D5V_PWR (2D5V=>CH1 , 1D2V=>CH2 , 1D8V =>CH3) 2 2D5V_PWR L32 5130_OUT1U 5130_LL1 S S S G 5130_OUT1D D D D D C 44 5130_OUT1D Imax=9A DCR=12mOhm 12*12*4.0 GAP-OPEN-PWR G78 2D5V Iomax=9A OCP>18A GAP-OPEN-PWR G81 GAP-OPEN-PWR G80 IND-2D2UH-16 U46 AO4406 GAP-OPEN-PWR G77 D D D D G S S S 44 5130_OUT1U 44 5130_LL1 C396 SC10U35V0ZY-U Imax=9.3A Rdson=19.6~24mohm TC25 ST220U4VDM-L3 D GAP-OPEN-PWR G74 1 D U43 AO4422 GAP-OPEN-PWR G73 DCBATOUT_5130 C429 SCD1U 2D5V_S3 G72 TC29 ST330U6D3VDM-7 GAP-OPEN-PWR G79 G83 KEMET, NTD:10.5 (Q1) ESR=25mohm Iripple=2.2A 7.3*4.3*1.9 Imax=9.6A Rdson=13.5~16.5mohm KEMET, NTD:6.5 (Q1) ESR=40mohm Iripple=1.7A 7.3*4.3*1.2 DCBATOUT_5130 GAP-OPEN-PWR 1 G82 C GAP-OPEN-PWR 1 GAP-OPEN-PWR 44 5130_OUT2U 44 5130_LL2 C860 SC10U35V0ZY-U 1D2V_PWR 1D2V_PWR GAP-OPEN-PWR G53 1D2V Iomax=5A OCP>10A GAP-OPEN-PWR G52 G51 2 Imax=9.3A Rdson=19.6~24mohm 44 5130_OUT2D GAP-OPEN-PWR TC5 ST220U4VDM-10 KEMET, NTD:7.8 (Q1) ESR=25mohm Iripple=2.2A 7.3*4.3*1.9 G S S S B D D D D IND-3D3UH-18 Imax=6A DCR=13mOhm 10*10*4.0 GAP-OPEN-PWR G43 Imax=9.3A Rdson=19.6~24mohm L26 5130_OUT2U 5130_LL2 U81 AO4422 1D2V_S0 G42 D D D D C853 SCD1U G S S S U86 AO4422 5130_OUT2D G55 GAP-OPEN-PWR G54 GAP-OPEN-PWR GAP-OPEN-PWR DCBATOUT_5130 G S S S 44 5130_OUT3U 44 5130_LL3 C374 SCD1U Imax=9.3A Rdson=19.6~24mohm L25 5130_OUT3U 5130_LL3 1D8V_PWR G S S S Imax=6A DCR=25mOhm 10*10*4.0 44 5130_OUT3D 5130_OUT3D Imax=9.3A Rdson=19.6~24mohm 1D8V Iomax=5A OCP>10A D D D D U36 AO4422 C354 SC10U35V0ZY-U GAP-OPEN-PWR G45 GAP-OPEN-PWR G46 IND-4D7UH-25 A 1D8V_S5 G44 D D D D 1D8V_PWR U37 AO4422 B TC23 ST220U4VDM-10 KEMET, NTD:7.8 (Q1) ESR=25mohm Iripple=2.2A 7.3*4.3*1.9 GAP-OPEN-PWR G47 GAP-OPEN-PWR G48 A GAP-OPEN-PWR G49 GAP-OPEN-PWR G50 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title TI TPS5130 2D5V/1D2V/1D8V (2/2) GAP-OPEN-PWR Size A3 Document Number Rev SA SNIPE Date: Thursday, November 18, 2004 Sheet 45 of 56 A B C D E 5V_AUX_S5 5/17 power team change 5V_AUX_S5 C870 LP2951ACM_FB SC330P50V2KX C858 SC10U10V5ZY DY OUT INPUT SENSE FB SD 5V/TAP GND 100mA ERROR DCBATOUT 1 2 C867 SCD1U 1 U35 LP2951ACM C427 C427 SC1U50V5ZY 78.10594.411 DY 3 G63 5V_S5 C375 SCD1U C389 SCD1U VIN VREF VCNTL GND GND VOUT NC NC NC 1 TC6 ST100U4VBM-1 GAP-OPEN-PWR C344 SC22U10V6ZY-U 78.22693.421 APL5331KAC-TR SO-8-P 1D25V_S3 GAP-OPEN-PWR G64 2 R258 1KR3F 1D25V_LDO APL5331_1D25V_VREF GAP-OPEN-PWR G59 Vo(cal.)=1.250V U38 R259 1KR3F 2 GAP-OPEN-PWR G58 1D25V_S3 Iomax=1.5A 2D5V_S3 C397 SC10U10V5ZY 78.10693.411 DY C398 SC10U10V5ZY 78.10693.411 2 2D5V_S3 KEMET 100uF / 4V / B2 Size / NTD:5.615 Iripple=1.1A / ESR=70mohm Trace Length=1cm (500mils) Trace Width=8mils Trace Resistance>25mohm 1 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title 1D2V_LDO/5V_AUX Size A3 Document Number Date: Thursday, November 18, 2004 A B C D Rev SA SNIPE Sheet E 46 of 56 BT+ DCBATOUT MAX1909_ACIN G103 GAP-CLOSE-PWR D D D D AO4407 U91 S S S G D D D D R247 DLOV 21 MAX1909_DLOV DHI 23 MAX1909_DHI DLO 20 MAX1909_DLO PGND 19 PGND 29 CSIP 18 CSIN BATT GND 17 16 15 Near MAX1909 Pin 21 SCD01U50V3KX MAX1909ETI NC Id=5.0A Rdson=23~30mohm GAP-CLOSE-PWR C933 C932 C891 SC10U25V0KX SC10U25V0KX SC10U25V0KXDY G100 G101 2 GAP-CLOSE-PWR D35 B220LFA DY GAP-CLOSE-PWR BAT+SENSE 48 From Battery Connector C831 3D3V_AUX V_REF :4.2235V ( 2.089V > AC DETECT C873 SCD1U25V3KX DY C850 SC1U50V5ZY 2 AO4407 For EMI DY R635 D01R2512F-1 AD+_TO_SYS S S S G U79 R612 100KR3F D D D D 1 DY C844 C845 SC1000P50V2KX SC1000P50V2KX 2 AD+ Wistron Corporation R211 49K9R3F 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title CHARGER MAX1909 Size Custom Document Number Rev SNIPE Date: Thursday, November 18, 2004 SA Sheet 47 of 56 A B C D D25 Adaptor in to generate DCBATOUT AD+ 100KR3 E Q5 2N7002 C527 SCD1U50V5ZY 1 C521 SCD1U50V3ZY ID = -10A/70deg Rds(ON) = 24mohm SO-8 PDTA124EU R362 56KR3F D C526 SCD1U50V5ZY 3 S R18 1KR3 Q3 C G AD_OFF B AD_OFF#_JK MH1 2 34 D D D D AO4407 R354 DC-JACK81 U52 S S S G C6 SCD1U50V3ZY AD+_2 C3 SCD1U50V3ZY 2 AD_JK 1 PZM24NB1 DY DCIN1 E 3 5V_AUX_S5 2 BATTERY CONNECTOR DY D13 BAV99-2 83.00099.L01 3 DY D14 BAV99-2 83.00099.L01 BAT1 34 BT_SCL_5 BT+34 BT_SDA_5 34,47 BT_TH 47 BAT+SENSE BT_SCL_5 BT_SDA_5 R730 R729 27R3F 27R3F BT_TH 10 12 14 16 BTSMCLK BTSMDATA BT+ C918 SC1000P50V2KX C461 SCD1U50V3ZY C463 SCD1U50V3ZY DY 2 11 13 15 SPD-CONN16D-7 20.D0091.208 C934 SC1000P50V2KX 1 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title DC/DC (1/2) 5V / 3.3V / 2.5V Size A3 Document Number Rev A B C D SA SNIPE Date: Thursday, November 18, 2004 Sheet E 48 of 56 U17A 1 R136 DUMMY-R2 R132 10KR2 AF27 AE27 GFX_CLK GFX_CLK# DVPCNTL_0 DVPCNTL_1 DVPCNTL_2 DVPCNTL_3 VREFG PCIE_REFCLKP PCIE_REFCLKN AC23 AB24 AB23 PCIE_CALRP PCIE_CALRN PCIE_CALI PCIE_TESTIN AE25 PCIE_TESTIN The PERSTB must deplay 4ms from M24 13,34 bug.AG_RST# PWRGD_MASK R521 715R3 R118 75R2F R110 75R2F 2 R111 75R2F 1 54 ATI_TV_LUMA 54 ATI_TV_CRMA 54 ATI_TV_COMP VGA_SMB_CLK VGA_SMB_DAT 13,54 VGA_SMB_CLK 13,54 VGA_SMB_DAT 1 R119 10KR2 R525 10KR2 VGA_SSIN VGA_SSOUT XTALIN_M24 Place them near to chip A 1 R538 1KR2 R483 1KR2 R474 1KR2 TP15 TPAD30 TP97 TPAD30 TESTEN STERE0SYNC AD25 AD24 PERSTb PERSTb_MASK AH21 R2SET AK21 AJ22 AK22 Y_G C_R_PR COMP_B_PB AJ24 AK24 H2SYNC V2SYNC AG22 AG23 DDC3CLK DDC3DATA AJ23 AH24 SSIN SSOUT AH28 XTALIN AJ29 XTALOUT AH27 E8 B6 AF25 TESTEN TEST_YCLK TEST_MCLK PLLTEST AH25 STEREOSYNC TMDS PCIE_CALP_VGA PCIE_CALN_VGA PCIE_CALI_VGA DAC1 R539 R541 150R2F 100R2 R540 10KR2F-U 10KR2 THERM R137 0R2-0 1 DAC2 R131 DUMMY-R2 R140 CLK SS 1D2V_VGA_S0 PWRGD_MASK 2 B STERE0SYNC 1, 64MB 64MB 64MB 64MB 128MB 128MB 128MB 128MB Hynix Samsung X brand Y brand Hynix Samsung X brand Y brand 1 1 2 2 1D8V_S0 0R2-0 0R2-0 0R2-0 0R2-0 M26-P-1 GPIO0 GPIO1 PCIE_MODE(1:0) GPIO(3:2) 00 CAL_OFF GPIO4 BYPASS_PLL GPIO5 ICOMP GPIO6 GPIO8 ROMIDCFG(3:0) GPIO(9,13:11) 0000 MULTIFUNC(1:0) LCDDATA(17:16) 00 VIP_DEVICE LCDDATA(20) DWNGR0 LCDDATA(21) (internal pull-down) R83 100R3 C ATI Ref Datasheets(page 3-32) DOC.NO.:CHS-216M24-03 GPIO[0 13] are internal pull-down TXOUT_L0N TXOUT_L0P TXOUT_L1N TXOUT_L1P TXOUT_L2N TXOUT_L2P TXOUT_L3N TXOUT_L3P TXCLK_LN TXCLK_LP TXOUT_U0N TXOUT_U0P TXOUT_U1N TXOUT_U1P TXOUT_U2N TXOUT_U2P TXOUT_U3N TXOUT_U3P TXCLK_UN TXCLK_UP AH15 AH16 AJ16 AJ17 AJ18 AK18 AJ20 AJ21 AK19 AJ19 AG16 AG17 AF16 AF17 AE18 AE19 AF19 AF20 AG19 AG20 DIGON BLON AE12 AG12 TX0M TX0P TX1M TX1P TX2M TX2P TXCM TXCP AK13 AJ13 AJ14 AJ15 AK15 AK16 AJ12 AK12 DDC2CLK DDC2DATA AE13 AE14 HPD1 AF12 R G B AK27 AJ27 AJ26 HSYNC VSYNC AJ25 AK25 RSET AH26 DDC1DATA DDC1CLK AG25 AF24 GPIO_AUXWIN AG24 DPLUS DMINUS AF11 AE11 ATI_TXAOUT3ATI_TXAOUT3+ ATI_TXAOUT0ATI_TXAOUT0+ ATI_TXAOUT1ATI_TXAOUT1+ ATI_TXAOUT2ATI_TXAOUT2+ TP5 TP4 R79 100R3 TMDS_TX0- R491 TMDS_TX0+ 330R2 TMDS_TX1- TMDS_TX2- TMDS_TXC- R489 TMDS_TX1+ 330R2 R490 TMDS_TX2+ 330R2 R472 TMDS_TXC+ 330R2 3D3V_S0 VGA_GPIO0 VGA_GPIO4 TPAD30ATI_TXBCLK- 54 TPAD30ATI_TXBCLK+ 54 VGA_GPIO2 VGA_GPIO3 ATI_LCDVDD_ON 54 BL_ON 13,34 VGA_GPIO5 TP89 TP92 TMDS_TX0TMDS_TX0+ TMDS_TX1TMDS_TX1+ TMDS_TX2TMDS_TX2+ TMDS_TXCTMDS_TXC+ C86 SCD1U16V ATI_TXACLK- 54 ATI_TXACLK+ 54 ATI_TXBOUT0- 54 ATI_TXBOUT0+ 54 ATI_TXBOUT1- 54 ATI_TXBOUT1+ 54 ATI_TXBOUT2- 54 ATI_TXBOUT2+ 54 TPAD30 TPAD30 ATI_TXBOUT3ATI_TXBOUT3+ 54 54 54 54 54 54 TMDS_TX0TMDS_TX0+ TMDS_TX1TMDS_TX1+ TMDS_TX2TMDS_TX2+ TMDS_TXCTMDS_TXC+ 15 15 15 15 15 15 15 15 R93 10KR2 R434 10KR2 B R92 DUMMY-R2 R84 DUMMY-R2 R4352 DUMMY-R2 R537 75R2F R530 75R2F R529 75R2F DVI_SCL 15 DVI_SDA 15 RN69 VGA_GPIO15 VGA_GPIO14 VGA_GPIO11 VGA_GPIO10 DVI_HPD 15 ATI_HSYNC ATI_VSYNC 54 54 54 VGA_LOCAL_DP VGA_LOCAL_DN RN68 VGA_GPIO9 VGA_GPIO6 VGA_GPIO7 54 54 R531 499R2F SRN10K-2 ATI_DDCDATA 54 ATI_DDCCLK 54 AUXWIN SRN10K-2 ATI_RED ATI_GREEN ATI_BLUE R526 10KR2 51 VGA_LOCAL_DP 54 VGA_LOCAL_DN 54 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title VGA M26 (1/2) PCIE LVDS Size A3 A Wistron Corporation 3D3V_S0 Document Number Rev SA SNIPE Date: Thursday, November 18, 2004 CAL_BG_BACKUP VGA_VREFG AG4 DEFAULT PLL_CAL_FORCE_EN DEBUG_ACCESS 3D3V_S0 AJ10 DVPCNTL0_VGAR96 AK10 DVPCNTL1_VGAR97 AJ11 DVPCNTL2_VGAR99 AH11 DVPCNTL3_VGAR100 PIN PCIE_TX0P PCIE_TX0N PCIE_TX1P PCIE_TX1N PCIE_TX2P PCIE_TX2N PCIE_TX3P PCIE_TX3N PCIE_TX4P PCIE_TX4N PCIE_TX5P PCIE_TX5N PCIE_TX6P PCIE_TX6N PCIE_TX7P PCIE_TX7N PCIE_TX8P PCIE_TX8N PCIE_TX9P PCIE_TX9N PCIE_TX10P PCIE_TX10N PCIE_TX11P PCIE_TX11N PCIE_TX12P PCIE_TX12N PCIE_TX13P PCIE_TX13N PCIE_TX14P PCIE_TX14N PCIE_TX15P PCIE_TX15N DVPDATA_0, 0 0 1 0 1 0 1 1 1 STRAPS PEG_TXP0_VGA AF26 PEG_TXN0_VGAAE26 PEG_TXP1_VGA AC25 PEG_TXN1_VGAAB25 PEG_TXP2_VGA AC27 PEG_TXN2_VGAAB27 PEG_TXP3_VGA AC26 PEG_TXN3_VGAAB26 PEG_TXP4_VGA Y25 PEG_TXN4_VGA W25 PEG_TXP5_VGA Y27 PEG_TXN5_VGA W27 PEG_TXP6_VGA Y26 PEG_TXN6_VGA W26 PEG_TXP7_VGA U25 PEG_TXN7_VGA T25 PEG_TXP8_VGA U27 PEG_TXN8_VGA T27 PEG_TXP9_VGA U26 PEG_TXN9_VGA T26 PEG_TXP10_VGA P25 PEG_TXN10_VGAN25 PEG_TXP11_VGA P27 PEG_TXN11_VGAN27 PEG_TXP12_VGA P26 PEG_TXN12_VGAN26 PEG_TXP13_VGA L25 PEG_TXN13_VGAK25 PEG_TXP14_VGA L27 PEG_TXN14_VGAK27 PEG_TXP15_VGA L26 PEG_TXN15_VGAK26 1D8V_S0 DUMMY-R2 DUMMY-R2 DUMMY-R2 SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V R737 R736 R738 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 VGA_DVOMODE D NO USE DVPDATA 3D3V_S0 3D3V_S0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 DVOMODE=GND TP64 TP1 TPAD30 TPAD30 R482 0R2-0 C C182 C183 C209 C210 C184 C185 C211 C212 C186 C187 C213 C214 C188 C189 C215 C216 C190 C191 C217 C218 C192 C193 C219 C220 C194 C195 C196 C197 C198 C199 C200 C201 12 PEG_RXN[15 0] PEG_TXP0 PEG_TXN0 PEG_TXP1 PEG_TXN1 PEG_TXP2 PEG_TXN2 PEG_TXP3 PEG_TXN3 PEG_TXP4 PEG_TXN4 PEG_TXP5 PEG_TXN5 PEG_TXP6 PEG_TXN6 PEG_TXP7 PEG_TXN7 PEG_TXP8 PEG_TXN8 PEG_TXP9 PEG_TXN9 PEG_TXP10 PEG_TXN10 PEG_TXP11 PEG_TXN11 PEG_TXP12 PEG_TXN12 PEG_TXP13 PEG_TXN13 PEG_TXP14 PEG_TXN14 PEG_TXP15 PEG_TXN15 adjust SWING at 1.2v 12 PEG_RXP[15 0] MUST TO CHECK DVOMODE=VSS 3.3V MODE TP2 TPAD30 DVOMODE=VDDC to 1.8V 1.8V MODE R66 105R3F 12 PEG_TXN[15 0] 2 C62 SC270P50V AE10 AH6 AJ6 AK6 AH7 AK7 AJ7 AH8 AJ8 AH9 AJ9 AK9 AH10 AE6 AG6 AF6 AE7 AF7 AE8 AG8 AF8 AE9 AF9 AG10 AF10 12 PEG_TXP[15 0] TP3 TPAD30 C70 SCD01U16V2KX XTALIN_M24 DVOMODE DVPDATA_0 DVPDATA_1 DVPDATA_2 DVPDATA_3 DVPDATA_4 DVPDATA_5 DVPDATA_6 DVPDATA_7 DVPDATA_8 DVPDATA_9 DVPDATA_10 DVPDATA_11 DVPDATA_12 DVPDATA_13 DVPDATA_14 DPVDATA_15 DVPDATA_16 DVPDATA_17 DVPDATA_18 DVPDATA_19 DVPDATA_20 DVPDATA_21 DVPDATA_22 DVPDATA_23 VGA_GPIO0 VGA_GPIO1 VGA_GPIO2 VGA_GPIO3 VGA_GPIO4 VGA_GPIO5 VGA_GPIO6 VGA_GPIO7 VGA_GPIO8 VGA_GPIO9 VGA_GPIO10 VGA_GPIO11 VGA_GPIO12 VGA_GPIO13 VGA_GPIO14 VGA_GPIO15 VGA_GPIO16 R67 140R3F ORIGNAL P2779A-08TT USE W180-01 GEOMETRY R50 620R2F C74 SCD1U AJ5 AH5 AJ4 AK4 AH4 AF4 AJ3 AK3 AH3 AJ2 AH2 AH1 AG3 AG1 AG2 AF3 AF2 VGA_GPIO16 VDD REF MODOUT VSS 3D3V_SS_S0 P2779A-08ST 71.02779.00A C51 SC6P50V3DN XIN/CLKIN XOUT PD# LF GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO_PWRCNTL GPIO_MEMSSIN Part of DVO / EXT TMDS / GPIO 1 X1 X-27MHZ-7-U 12 D R46 1MR2 C52 SC6P50V3DN 1 U11 PCIE_RX0P PCIE_RX0N PCIE_RX1P PCIE_RX1N PCIE_RX2P PCIE_RX2N PCIE_RX3P PCIE_RX3N PCIE_RX4P PCIE_RX4N PCIE_RX5P PCIE_RX5N PCIE_RX6P PCIE_RX6N PCIE_RX7P PCIE_RX7N PCIE_RX8P PCIE_RX8N PCIE_RX9P PCIE_RX9N PCIE_RX10P PCIE_RX10N PCIE_RX11P PCIE_RX11N PCIE_RX12P PCIE_RX12N PCIE_RX13P PCIE_RX13N PCIE_RX14P PCIE_RX14N PCIE_RX15P PCIE_RX15N LVDS R54 0R5J-1 AH30 AG30 AG29 AF29 AE29 AE30 AD30 AD29 AC29 AB29 AB30 AA30 AA29 Y29 W29 W30 V30 V29 U29 T29 T30 R30 R29 P29 N29 N30 M30 M29 L29 K29 K30 J30 PCI EXPRESS 3D3V_S0 PEG_RXP0 PEG_RXN0 PEG_RXP1 PEG_RXN1 PEG_RXP2 PEG_RXN2 PEG_RXP3 PEG_RXN3 PEG_RXP4 PEG_RXN4 PEG_RXP5 PEG_RXN5 PEG_RXP6 PEG_RXN6 PEG_RXP7 PEG_RXN7 PEG_RXP8 PEG_RXN8 PEG_RXP9 PEG_RXN9 PEG_RXP10 PEG_RXN10 PEG_RXP11 PEG_RXN11 PEG_RXP12 PEG_RXN12 PEG_RXP13 PEG_RXN13 PEG_RXP14 PEG_RXN14 PEG_RXP15 PEG_RXN15 Sheet 49 of 56 C 1D8V_S0 R108 0R3-U 1D8V_TVDD_S0 1D8V_S0 1D2V_VGA_S0 C181 SC1U10V3KX A2VDD#AF21 A2VDD#AE20 AF23 A2VDDQ AH23 AVDD 1D8V_S0 C148 C149 SC10U10V5ZY SC1U10V3KX R130 0R3-U 2 1D8V_S0 VDDRH0 VDDRH1 AF21 AE20 1D8V_DDQ AE23 AE22 AK28 1D8V_S0 LVSSR#AF18 LVSSR#AH17 LVSSR#AG15 LVSSR#AG18 AF18 AH17 AG15 AG18 LPVSS TPVSS AH18 AH12 TXVSSR#AH12 TXVSSR#AG13 TXVSSR#AG14 AH14 AG13 AG14 PVDD_12V PVDD MPVDD 1 T1 < 1mS 3D3_VDDR4 C712 C736 C763 SCD01U16V2KX SCD01U16V2KX SCD01U16V2KX T2 < 1mS 2D5_VDDR1 VSSRH0 VSSRH1 AH20 AG21 A2VSSQ AF22 AVSSN AH22 VSS1DI VSS2DI AE24 AE21 PVSS 1 C710 SCD01U16V2KX 2 C709 SC10U10V5ZY C711 SCD01U16V2KX T4 < 100nS PCIE_VDDR_12 T5 < 100nS PCIE_PVDD_12 T6 < 1uS VDD_15 T7 < 100nS PCIE_PVDD_18 F19 M6 A2VSSN#AH20 A2VSSN#AG21 MPVSS T3 < 1uS 1D2_VDDC ADD ASIC DECOUPLING FOR ALL POWER AS REQUIRED PLACED CLOSE TO THE POWER/GND PINS WITH AS MANY AS POSSIBLE PLACED UNDER THE ASIC 1D2V_VGA_S0 AJ28 1D2V_VGA_VDDR R139 0R3-U A6 C700 SC330P50V2KX PVDD_12V M26-P-1 1D8V_S0 C139 C734 SC10U10V5ZY SC1U10V3KX 1D8V_DDQ 1D8V_VGA_PVDD R522 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C 1 0R3-U 2 C750 SC10U10V5ZY AD22 3D3_VDDR3 AVSSQ A7 VDD1DI VDD2DI DIODE SUPPLIES POWER TO VDDC RAIL WHILE VDDC REGULATOR STABALIZES DURING POWER ON C764 C765 C735 SCD01U16V2KX SCD01U16V2KX SCD01U16V2KX F18 N6 I/O POWER VGA_MEM_S0 C65 C72 SC10U10V5ZY SC1U10V3KX 1D8V_S0 VDDR_12V TXVDDR#AF13 TXVDDR#AF14 C231 SC330P50V2KX VDDR_12V AF13 AF14 0R3-U M22 Power UP Squence 2D5V_S0 2 LPVDD TPVDD 2 1 1D2V_VGA_VDDR R144 AH19 AH13 C663 C686 SC1U10V3KX SC1U10V3KX C639 C624 SC10U10V5ZY SC1U10V3KX LVDDR_25#AE16 LVDDR_25#AE17 LVDDR_18#AF15 LVDDR_18#AE15 1 1 1 2 2 C643 C701 C626 C644 SC1U10V3KX SC1U10V3KX SC1U10V3KX SC1U10V3KX 3D3V_VDDR4 AE16 AE17 AF15 AE15 2 1 1 2 3D3V_S0 R492 0R3-U VGA_CORE_S0 PVDD_18V C120 C672 SC1U10V3KX SC100P50V2JN 2 1D5V_VGA_S0 C697 C625 SC1U10V3KX SC1U10V3KX D9 D13 D19 D25 E4 T4 AB4 3D3V_S0 R508 0R3-U 1 NC#D9 NC#D13 NC#D19 NC#D25 NC#E4 NC#T4 NC#AB4 C641 C640 C675 C664 C662 C685 C687 C665 SCD01U16V2KX SCD01U16V2KX SCD01U16V2KX SCD01U16V2KX SCD01U16V2KX SCD01U16V2KX SCD01U16V2KX SCD01U16V2KX U23 T23 V23 W23 PCIE_PVDD_18#U23 PCIE_PVDD_18#T23 PCIE_PVDD_18#V23 PCIE_PVDD_18#W23 3D3V_VDDR3 1D5V_VGA_S0 N24 N23 P23 SSM5818SL PCIE_PVDD_12#N24 PCIE_PVDD_12#N23 PCIE_PVDD_12#P23 VGA_CORE_S0 AG26 AK29 AJ30 AG28 AG27 R104 1D8V_LVDDR_S1 0R3-U 1 PCIE_VDDR_12#AG26 PCIE_VDDR_12#AK29 PCIE_VDDR_12#AJ30 PCIE_VDDR_12#AG29 PCIE_VDDR_12#AH29 C696 SC100P50V2JN Delete SC1U10V3ZY*2 AG7 AD9 AC9 AC10 AD10 D30 1 VDDR4#AG7 VDDR4#AD9 VDDR4#AC9 VDDR4#AC10 VDDR4#AD10 D4 SSM5818SL C673 SCD1U16V AD7 AD19 AD21 AC22 AC8 AC21 AC19 3D3V_S0 3D3V_S0 Delete SC10U6D3V5MX*1 VDDR3#AD7 VDDR3#AD19 VDDR3#AD21 VDDR3#AC22 VDDR3#AC8 VDDR3#AC21 VDDR3#AC19 C688 C699 C661 C674 SCD01U16V2KX SCD01U16V2KX SCD01U16V2KX SCD01U16V2KX 2D5V_S0 DIODE SUPPLIES POWER TO VDDC RAIL WHILE VDDC REGULATOR STABALIZES DURING POWER ON 2 2 VDD15#P8 VDD15#Y8 VDD15#AC11 VDD15#AC20 VDD15#H20 VDD15#H11 VDD15#M23 VDD15#Y23 P8 Y8 AC11 AC20 H20 H11 M23 Y23 C230 SC10U10V5ZY 1 1 2 C690 C590 SC10U10V5ZY SC10U10V5ZY AC13 AD13 AD15 AC15 AC17 MVDDQ= 1.8v/ 2.5v VDDC#AC13 VDDC#AD13 VDDC#AD15 VDDC#AC15 VDDC#AC17 VGA_MEM_S0 VGA_MEM_S0 Part of 2 2 2 VDDR1#T7 VDDR1#R4 VDDR1#R1 VDDR1#N8 VDDR1#N7 VDDR1#M4 VDDR1#L8 VDDR1#K23 VDDR1#K24 VDDR1#N4 VDDR1#J8 VDDR1#J7 VDDR1#J4 VDDR1#J1 VDDR1#H10 VDDR1#H13 VDDR1#H15 VDDR1#H17 VDDR1#T8 VDDR1#V4 VDDR1#V7 VDDR1#V8 VDDR1#AA1 VDDR1#AA4 VDDR1#AA7 VDDR1#AA8 VDDR1#A3 VDDR1#A9 VDDR1#A15 VDDR1#A21 VDDR1#A28 VDDR1#B1 VDDR1#B30 VDDR1#D26 VDDR1#D23 VDDR1#D20 VDDR1#D17 VDDR1#D14 VDDR1#D11 VDDR1#D8 VDDR1#D5 VDDR1#E27 VDDR1#F4 VDDR1#G7 VDDR1#G10 VDDR1#G13 VDDR1#G15 VDDR1#G19 VDDR1#G22 VDDR1#G27 VDDR1#H22 VDDR1#H19 VDDR1#AD4 VDDR1#L23 1 1 1 2 C629 C676 C666 C627 C628 C714 C630 C689 SCD01U16V2KX SCD01U16V2KX SCD01U16V2KX SCD01U16V2KX SCD01U16V2KX SCD01U16V2KX SCD01U16V2KX SCD01U16V2KX T7 R4 R1 N8 N7 M4 L8 K23 K24 N4 J8 J7 J4 J1 H10 H13 H15 H17 T8 V4 V7 V8 AA1 AA4 AA7 AA8 A3 A9 A15 A21 A28 B1 B30 D26 D23 D20 D17 D14 D11 D8 D5 E27 F4 G7 G10 G13 G15 G19 G22 G27 H22 H19 AD4 L23 E VGA_CORE_S0 U17D VGA_MEM_S0 C766 C713 C591 SC1U10V3KX SC1U10V3KX SC1U10V3KX D B A C698 SC330P50V2KX Title ATI(2/3) PVDD_18V Size A3 Document Number Rev SA SNIPE Date: Thursday, November 18, 2004 Sheet 50 of 56 C D E A19 CASA# E18 CASA# 52 WEA# E19 WEA# 52 CSA0# E20 CSA1# F20 CKEA B19 CLKA0 CLKA0# B21 C20 CLKA0 CLKA#0 VGA_MEM_S0 52 52 CLKA1 CLKA1# C18 A18 CLKA1 CLKA#1 52 52 MVREFS B8 CKEB R443 10KR2 52 CSA#1 52 CKEA 52 CSA#0 ATI_MVREFD ATI_MVREFS R459 100R2 D30 DIMA_0 B13 DIMA_1 R457 100R2 DIMA_0 DIMA_1 R509 10KR2 VGA_MEM_S0 C614 SCD1U16V B7 CSA#1 52 MVREFD RASA# CKEA TP20 TP6 TPAD30 TPAD30 DQMB#0 DQMB#1 DQMB#2 DQMB#3 DQMB#4 DQMB#5 DQMB#6 DQMB#7 QSB0 QSB1 QSB2 QSB3 QSB4 QSB5 QSB6 QSB7 F6 B3 K6 G1 V5 W1 AC5 AD1 QSB0 QSB1 QSB2 QSB3 QSB4 QSB5 QSB6 QSB7 R475 100R2 C631 SCD1U16V U17F DQMB#[7 0] 53 QSB[7 0] 53 RASB# R2 RASB# 53 CASB# T5 CASB# 53 WEB# T6 WEB# 53 CSB0# R5 CSB#0 53 CSB1# R6 CSB#1 53 CSB#1 CKEB R3 CKEB 53 CLKB0 CLKB0# N1 N2 CLKB0 CLKB#0 53 53 CLKB1 CLKB1# T2 T3 CLKB1 CLKB#1 53 53 DIMB_0 DIMB_1 E3 AA3 ROMCS# AF5 MEMVMODE_0 MEMVMODE_1 C6 C7 MEMTEST C8 M26-P-1 MEMORY CHANNEL B TP61 TP65 TPAD30 TPAD30 VGA_CORE_S0 R458 0R2-0 47R2 W16 M15 R19 T12 VGA_CORE_VDDCI R501 M22,24,26P :Not connected C642 SC330P50V2KX 1D8V_S0 When use M22/24P R436 4K7R2 1 R473 M16 N16 N15 P15 P16 R18 R17 R16 R15 R14 R13 R12 T13 T14 T15 W15 V16 V15 U15 U16 T19 T18 T17 T16 VDDC#P17Part of VSS#M16 VDDC#P18 VSS#N16 VDDC#P19 VSS#N15 VDDC#U12 VSS#P15 VDDC#U13 VSS#P16 VDDC#U14 VSS#R18 VDDC#U17 VSS#R17 VDDC#U18 VSS#R16 VDDC#U19 VSS#R15 VDDC#V19 VSS#R14 VDDC#V18 VSS#R13 VDDC#V17 VSS#R12 VDDC#V14 VSS#T13 VDDC#V13 VSS#T14 VDDC#V12 VSS#T15 VDDC#N18 VSS#W15 VDDC#N17 VSS#V16 VDDC#N14 VSS#V15 VDDC#W17 VSS#U15 VDDC#W18 VSS#U16 VDDC#W12 VSS#T19 VDDC#W13 VSS#T18 VDDC#W14 VSS#T17 VDDC#N13 VSS#T16 VDDC#N19 VDDC#M19 VDDC#M18 VDDC#M12 VDDC#N12 VDDC#M13 VDDC#M14 VDDC1#W16 VDDC#P12 VDDC1#M15 VDDC#P13 VDDC1#R19 VDDC#P14 VDDC1#T12 VDDC#M17 VDDC#W19 M26-P-1 TP67 TPAD30 R445 10KR2 When select M24 use 45ohm 1% When select M26 use 240ohm 1% As close to CHIP as possible P17 P18 P19 U12 U13 U14 U17 U18 U19 V19 V18 V17 V14 V13 V12 N18 N17 N14 W17 W18 W12 W13 W14 N13 N19 M19 M18 M12 N12 M13 M14 P12 P13 P14 M17 W19 0R3-U 2 E6 B2 J5 G3 W6 W2 AC6 AD2 53 VGA_CORE_S0 R4442 DUMMY-R2 PIN C6 C7 1.8V = PD PU 2.5V = PU PD R437 DUMMY-R2 When use M26P, pls remove this M22,24,26P :Not connected M26-P-1 R466 100R2 DQMB#0 DQMB#1 DQMB#2 DQMB#3 DQMB#4 DQMB#5 DQMB#6 DQMB#7 MAB[13 0] RASA# 52 MAB0 MAB1 MAB2 MAB3 MAB4 MAB5 MAB6 MAB7 MAB8 MAB9 MAB10 MAB11 MAB12 MAB13 J27 F30 F24 B27 E16 B16 B11 F10 QSA[7 0] 52 N5 M1 M3 L3 L2 M2 M5 P6 N3 K2 K3 J2 P5 P3 P2 MAB0 MAB1 MAB2 MAB3 MAB4 MAB5 MAB6 MAB7 MAB8 MAB9 MAB10 MAB11 MAB12 MAB13 MAB14 Part of QSA0 QSA1 QSA2 QSA3 QSA4 QSA5 QSA6 QSA7 QSA0 QSA1 QSA2 QSA3 QSA4 QSA5 QSA6 QSA7 DQMA#[7 0] DQB0 DQB1 DQB2 DQB3 DQB4 DQB5 DQB6 DQB7 DQB8 DQB9 DQB10 DQB11 DQB12 DQB13 DQB14 DQB15 DQB16 DQB17 DQB18 DQB19 DQB20 DQB21 DQB22 DQB23 DQB24 DQB25 DQB26 DQB27 DQB28 DQB29 DQB30 DQB31 DQB32 DQB33 DQB34 DQB35 DQB36 DQB37 DQB38 DQB39 DQB40 DQB41 DQB42 DQB43 DQB44 DQB45 DQB46 DQB47 DQB48 DQB49 DQB50 DQB51 DQB52 DQB53 DQB54 DQB55 DQB56 DQB57 DQB58 DQB59 DQB60 DQB61 DQB62 DQB63 DQMA#0 DQMA#1 DQMA#2 DQMA#3 DQMA#4 DQMA#5 DQMA#6 DQMA#7 D7 F7 E7 G6 G5 F5 E5 C4 B5 C5 A4 B4 C2 D3 D1 D2 G4 H6 H5 J6 K5 K4 L6 L5 G2 F3 H2 E2 F2 J3 F1 H3 U6 U5 U3 V6 W5 W4 Y6 Y5 U2 V2 V1 V3 W3 Y2 Y3 AA2 AA6 AA5 AB6 AB5 AD6 AD5 AE5 AE4 AB2 AB3 AC2 AC3 AD3 AE1 AE2 AE3 DQMA#0 DQMA#1 DQMA#2 DQMA#3 DQMA#4 DQMA#5 DQMA#6 DQMA#7 J25 F29 E25 A27 F15 C15 C11 E11 MDB0 MDB1 MDB2 MDB3 MDB4 MDB5 MDB6 MDB7 MDB8 MDB9 MDB10 MDB11 MDB12 MDB13 MDB14 MDB15 MDB16 MDB17 MDB18 MDB19 MDB20 MDB21 MDB22 MDB23 MDB24 MDB25 MDB26 MDB27 MDB28 MDB29 MDB30 MDB31 MDB32 MDB33 MDB34 MDB35 MDB36 MDB37 MDB38 MDB39 MDB40 MDB41 MDB42 MDB43 MDB44 MDB45 MDB46 MDB47 MDB48 MDB49 MDB50 MDB51 MDB52 MDB53 MDB54 MDB55 MDB56 MDB57 MDB58 MDB59 MDB60 MDB61 MDB62 MDB63 MAA0 MAA1 MAA2 MAA3 MAA4 MAA5 MAA6 MAA7 MAA8 MAA9 MAA10 MAA11 MAA12 MAA13 52 E22 B22 B23 B24 C23 C22 F22 F21 C21 A24 C24 A25 E21 B20 C19 MEMORY CHANNEL A MAA[13 0] MAA0 MAA1 MAA2 MAA3 MAA4 MAA5 MAA6 MAA7 MAA8 MAA9 MAA10 MAA11 MAA12 MAA13 MAA14 Part of DQA0 DQA1 DQA2 DQA3 DQA4 DQA5 DQA6 DQA7 DQA8 DQA9 DQA10 DQA11 DQA12 DQA13 DQA14 DQA15 DQA16 DQA17 DQA18 DQA19 DQA20 DQA21 DQA22 DQA23 DQA24 DQA25 DQA26 DQA27 DQA28 DQA29 DQA30 DQA31 DQA32 DQA33 DQA34 DQA35 DQA36 DQA37 DQA38 DQA39 DQA40 DQA41 DQA42 DQA43 DQA44 DQA45 DQA46 DQA47 DQA48 DQA49 DQA50 DQA51 DQA52 DQA53 DQA54 DQA55 DQA56 DQA57 DQA58 DQA59 DQA60 DQA61 DQA62 DQA63 H28 H29 J28 J29 J26 H25 H26 G26 G30 D29 D28 E28 E29 G29 G28 F28 G25 F26 E26 F25 E24 F23 E23 D22 B29 C29 C25 C27 B28 B25 C26 B26 F17 E17 D16 F16 E15 F14 E14 F13 C17 B18 B17 B15 C13 B14 C14 C16 A13 A12 C12 B12 C10 C9 B9 B10 E13 E12 E10 F12 F11 E9 F9 F8 MEMORY INTERFACE B U17B MDA0 MDA1 MDA2 MDA3 MDA4 MDA5 MDA6 MDA7 MDA8 MDA9 MDA10 MDA11 MDA12 MDA13 MDA14 MDA15 MDA16 MDA17 MDA18 MDA19 MDA20 MDA21 MDA22 MDA23 MDA24 MDA25 MDA26 MDA27 MDA28 MDA29 MDA30 MDA31 MDA32 MDA33 MDA34 MDA35 MDA36 MDA37 MDA38 MDA39 MDA40 MDA41 MDA42 MDA43 MDA44 MDA45 MDA46 MDA47 MDA48 MDA49 MDA50 MDA51 MDA52 MDA53 MDA54 MDA55 MDA56 MDA57 MDA58 MDA59 MDA60 MDA61 MDA62 MDA63 MDA[63 0] CENTER ARRAY MDB[63 0] 53 U17C MEMORY INTERFACE A 52 B A K28 L28 M27 M26 M24 M25 M28 P28 N28 R25 R23 R24 R26 R27 R28 T28 T24 U28 V24 V26 V27 V25 V28 Y28 W24 W28 AA26 AA27 AA23 AA24 AA25 AA28 AB28 AC28 AD28 AD26 AD27 AE28 AF28 AH29 VDDR1 1.8V AUXWIN MEMVMODE_0 GND 2.5V +VDDC_CT 2.8V +VDDC_CT MEMVMODE_1 +VDDC_CT GND +VDDC_CT VSS#R7 VSS#P4 VSS#M7 VSS#M8 VSS#L4 VSS#K1 VSS#K7 VSS#K8 VSS#R8 VSS#T1 MVDDQ= 1.8v/ 2.5v AUXWIN Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C R7 P4 M7 M8 L4 K1 K7 K8 R8 T1 VSS#AD12 VSS#AG5 VSS#AG9 VSS#AG11 AD12 AG5 AG9 AG11 VSS#F27 VSS#G9 VSS#G12 VSS#G16 VSS#G18 VSS#G21 VSS#G24 VSS#H27 VSS#H23 VSS#H21 VSS#H18 VSS#H16 VSS#H14 VSS#H12 VSS#H9 VSS#H8 VSS#H4 VSS#J23 VSS#J24 F27 G9 G12 G16 G18 G21 G24 H27 H23 H21 H18 H16 H14 H12 H9 H8 H4 J23 J24 VSS#A2 VSS#A10 VSS#A16 VSS#A22 VSS#A29 VSS#C1 VSS#C3 VSS#C28 VSS#C30 VSS#D27 VSS#D24 VSS#D21 VSS#D18 VSS#D15 VSS#D12 VSS#D10 VSS#D6 VSS#D4 A2 A10 A16 A22 A29 C1 C3 C28 C30 D27 D24 D21 D18 D15 D12 D10 D6 D4 CORE GND Part of VSS#U4 VSS#U8 VSS#W7 VSS#W8 VSS#Y4 VSS#AB8 VSS#AB7 VSS#AB1 VSS#AC4 VSS#AC12 VSS#AC14 VSS#AD16 VSS#AC16 VSS#AC18 VSS#AD18 VSS#AK2 VSS#AJ1 U17E PCIE_VSS#K28 PCIE_VSS#L28 PCIE_VSS#M27 PCIE_VSS#M26 PCIE_VSS#M24 PCIE_VSS#M25 PCIE_VSS#M28 PCIE_VSS#P28 PCIE_VSS#N28 PCIE_VSS#R25 PCIE_VSS#R23 PCIE_VSS#R24 PCIE_VSS#R26 PCIE_VSS#R27 PCIE_VSS#R28 PCIE_VSS#T28 PCIE_VSS#T24 PCIE_VSS#U28 PCIE_VSS#V24 PCIE_VSS#V26 PCIE_VSS#V27 PCIE_VSS#V25 PCIE_VSS#V28 PCIE_VSS#Y28 PCIE_VSS#W23 PCIE_VSS#W28 PCIE_VSS#AA26 PCIE_VSS#AA27 PCIE_VSS#AA23 PCIE_VSS#AA24 PCIE_VSS#AA25 PCIE_VSS#AA28 PCIE_VSS#AB28 PCIE_VSS#AC28 PCIE_VSS#AD28 PCIE_VSS#AD26 PCIE_VSS#AD27 PCIE_VSS#AE28 PCIE_VSS#AF28 PCIE_VSS#AH29 U4 U8 W7 W8 Y4 AB8 AB7 AB1 AC4 AC12 AC14 AD16 AC16 AC18 AD18 AK2 AJ1 449 Title ATI(3 of 3) Size A3 Document Number Rev SA SNIPE Date: Thursday, November 18, 2004 Sheet 51 of 56 VGA_MEM_S0 M13 MCL/DSF DM1 DQS1 of MDA6 MDA2 MDA0 MDA7 MDA1 MDA4 MDA5 MDA3 G3 K3 J3 F3 J2 G2 F2 K2 MEMA_DM0 MEMA_DQS0 H3 H2 2 of U14D MDA37 MDA35 MDA34 MDA39 MDA33 MDA36 MDA38 MDA32 DQ18 DQ23 DQ20 DQ16 DQ21 DQ19 DQ17 DQ22 G3 K3 J3 F3 J2 G2 F2 K2 MEMA_DM4 MEMA_DQS4 DM2 DQS2 H3 H2 HY5DS573222F-U U23E of MDA26 MDA31 MDA30 MDA24 MDA27 MDA25 MDA29 MDA28 VGA_MEM_S0 MEMA_DM3 MEMA_DQS3 D12 D13 E13 C9 B10 B8 C13 B9 B12 B13 DQ18 DQ23 DQ20 DQ16 DQ21 DQ19 DQ17 DQ22 F6 F7 F8 F9 G6 G7 G8 G9 H6 H7 H8 H9 J6 J7 J8 J9 M13 VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL MCL/DSF VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS E5 E7 E8 E10 K6 K7 K8 K9 L5 L10 VREF N13 DQ26 DQ25 DQ24 DQ30 DQ28 DQ31 DQ27 DQ29 SC22U10V6ZY-U VGA_MEM_S0 HY5DS573222F-U R68 1KR3F C78 SCD1U16V B VDDR_VREF2 DM2 DQS2 HY5DS573222F-U DM3 DQS3 D12 D13 E13 C9 B10 B8 C13 B9 DQ26 DQ25 DQ24 DQ30 DQ28 DQ31 DQ27 DQ29 MEMA_DM7 B12 MEMA_DQS7B13 DM3 DQS3 MEMA_DM4 MEMA_DM6R484 MEMA_DM7R462 R461 1 15R2J 15R2J 15R2J MEMA_DQS4 MEMA_DQS6 R495 MEMA_DQS7 R463 R460 1 15R2J 15R2J 15R2J DQMA#4 DQMA#6 DQMA#7 R69 1KR3F Layout trace 20 mil QSA4 QSA6 QSA7 HY5DS573222F-U DQMA#2 QSA2 15R2J 15R2J MEMA_DM2 MEMA_DQS2 QSA1 R128 1KR3F C140 SCD1U16V R534 R527 MEMA_DQS5 R494 MEMA_DM5 R493 DQMA#1 1 15R2J MEMA_DQS1 R545 15R2J MEMA_DM1 R546 A Wistron Corporation QSA5 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C 15R2J DQMA#5 DQMA#0 15R2J DQMA#3 QSA3 15R2J 15R2J R532 R533 MEMA_DM3 MEMA_DQS3 QSA0 15R2J 15R2J R547 MEMA_DM0 R548 MEMA_DQS0 Title VGA VRAM (DDR) (1/2) Size A3 Document Number Rev SA SNIPE Date: Thursday, November 18, 2004 C79 SCD1U16V U14E of MDA58 MDA63 MDA61 MDA56 MDA59 MDA57 MDA62 MDA60 Layout trace 20 mil C HY5DS573222F-U 2 R127 1KR3F C153 SCD1U16V CLOSE TO MEM 1 HY5DS573222F-U HY5DS573222F-U VDDR_VREF1 A MEMA_DM6 H12 MEMA_DQS6H13 DM1 DQS1 C598 SCD1U16V SC22U10V6ZY-U MEMA_DM2 H12 MEMA_DQS2 H13 U23D HY5DS573222F-U C4 C11 H4 H11 L12 L13 M3 N3 DQ8 DQ12 DQ13 DQ10 DQ14 DQ9 DQ15 DQ11 DQ8 DQ12 DQ13 DQ10 DQ14 DQ9 DQ15 DQ11 R446 60D4R3F 60D4R3F B4 B11 D4 D5 D6 D9 D10 D11 E6 E9 F5 F10 G5 G10 H5 H10 J5 J10 K5 K10 N13 K13 G13 G12 J13 F13 K12 F12 J12 of K13 G13 G12 J13 F13 K12 F12 J12 R449 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ C593 VREF MDA21 MDA18 MDA17 MDA22 MDA19 MDA23 MDA16 MDA20 MDA49 MDA53 MDA54 MDA50 MDA52 MDA48 MDA55 MDA51 CKE CLK CLK# C645 E5 E7 E8 E10 K6 K7 K8 K9 L5 L10 HY5DS573222F-U U14C CKEA N12 VDDRA_CLK1+ M11 0R3-U VDDRA_CLK1M12 0R3-U R447 R448 D VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS DM0 DQS0 51 CLKA1 CLKA#1 C3 C5 C7 C8 C10 C12 E3 E12 F4 F11 G4 G11 J4 J11 K4 K11 VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL B3 B2 of U23C BA0 BA1 NC#M10 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VGA_MEM_S0 F6 F7 F8 F9 G6 G7 G8 G9 H6 H7 H8 H9 J6 J7 J8 J9 NC#C4 NC#C11 NC#H4 NC#H11 NC#L12 NC#L13 NC#M3 NC#N3 C691 SCD1U16V C780 N4 M5 M10 MAA12 MAA13 D7 D8 E4 E11 L4 L7 L8 L11 1 60D4R3F DQ3 DQ1 DQ2 DQ0 DQ6 DQ551 DQ451 DQ7 MEMA_DM5 MEMA_DQS5 A0 A1 A2 A3 A4 A5 A6 A7 A8/AP A9 A10 A11 NC#L9 NC#C4 NC#C11 NC#H4 NC#H11 NC#L12 NC#L13 NC#M3 NC#N3 R513 60D4R3F B4 B11 D4 D5 D6 D9 D10 D11 E6 E9 F5 F10 G5 G10 H5 H10 J5 J10 K5 K10 DM0 DQS0 N5 N6 M6 N7 N8 M9 N9 N10 N11 M8 L6 M7 L9 VDD VDD VDD VDD VDD VDD VDD VDD C4 C11 H4 H11 L12 L13 M3 N3 R510 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ B3 B2 B5 C6 B6 B7 D2 D3 C2 E2 HY5DS573222F-U C737 2 CKE CLK CLK# MEMA_DM1 MEMA_DQS1 DQ3 DQ1 DQ2 DQ0 DQ6 DQ5 DQ4 DQ7 MAA0 MAA1 MAA2 MAA3 MAA4 MAA5 MAA6 MAA7 MAA8 MAA9 MAA10 MAA11 of U14B MDA45 MDA46 MDA43 MDA44 MDA42 MDA40 MDA47 MDA41 BA0 BA1 NC#M10 VGA_MEM_S0 N4 M5 M10 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ C3 C5 C7 C8 C10 C12 E3 E12 F4 F11 G4 G11 J4 J11 K4 K11 MAA12 MAA13 D7 D8 E4 E11 L4 L7 L8 L11 A0 A1 A2 A3 A4 A5 A6 A7 A8/AP A9 A10 A11 NC#L9 CKEA N12 VDDRA_CLK0+M11 VDDRA_CLK0- M12 10R3-U 0R3-U CLOSE TO MEM !! N5 N6 M6 N7 N8 M9 N9 N10 N11 M8 L6 M7 L9 BC751_1 B MAA0 MAA1 MAA2 MAA3 MAA4 MAA5 MAA6 MAA7 MAA8 MAA9 MAA10 MAA11 VDD VDD VDD VDD VDD VDD VDD VDD B5 C6 B6 B7 D2 D3 C2 E2 RAS# CAS# WE# CS# NC#M4 BC752_1 51 R512 R511 RAS# CAS# WE# CS# NC#M4 SC22U10V6ZY-U C CLKA0 CLKA#0 M2 L2 L3 N2 M4 RASA# CASA# WEA# CSA#0 CSA#1 51 51 51 51 51 MDA12 MDA11 MDA9 MDA10 MDA13 MDA8 MDA15 MDA14 CLOSE TO MEM !! of U23B of C155 C154 SC330P50V2KX SCD01U16V2KX 2 2 2 2 C615 SCD01U16V2KX 1 1 1 1 1 C71 C603 C648 C647 C616 C633 C632 C646 SC330P50V2KX SC330P50V2KX SC330P50V2KX SC330P50V2KX SC330P50V2KX SC330P50V2KX SC330P50V2KX SC330P50V2KX 2 D M2 L2 L3 N2 M4 QSA[7 0] RASA# CASA# WEA# CSA#0 CSA#1 C677 SCD1U16V SC22U10V6ZY-U C64 SCD1U16V 1 MAA[13 0] C739 51 DQMA#[7 0] SCD01U16V2KX 51 MDA[63 0] C741 SCD1U16V 2 C751 SCD1U16V 1 C738 SCD1U16V of U14A 51 51 U23A VGA_MEM_S0 C726 SCD1U16V C753 SCD1U16V 2 C740 SCD1U16V C752 SCD1U16V 1 1 C152 SCD1U16V 2 All dampings in this page must near the VRAM Sheet 52 of 56 51 51 51 51 51 C26 SCD01U16V2KX RASB# CASB# WEB# CSB#0 CSB#1 MAB0 MAB1 MAB2 MAB3 MAB4 MAB5 MAB6 MAB7 MAB8 MAB9 MAB10 MAB11 M13 VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL MCL/DSF VREF MEMB_DM7 MEMB_DQS7 DQ8 DQ12 DQ13 DQ10 DQ14 DQ9 DQ15 DQ11 H12 H13 DM1 DQS1 MEMB_DM1 MEMB_DQS1 G3 K3 J3 F3 J2 G2 F2 K2 DQ18 DQ23 DQ20 DQ16 DQ21 DQ19 DQ17 DQ22 H3 H2 DM2 DQS2 2 R397 60D4R3F C551 SCD1U16V HY5DS573222F-U of U8D MDB14 MDB9 MDB11 MDB13 MDB10 MDB15 MDB12 MDB8 of U7D MDB43 MDB47 MDB45 MDB42 MDB44 MDB40 MDB41 MDB46 MEMB_DM5 MEMB_DQS5 F6 F7 F8 F9 G6 G7 G8 G9 H6 H7 H8 H9 J6 J7 J8 J9 M13 G3 K3 J3 F3 J2 G2 F2 K2 DQ18 DQ23 DQ20 DQ16 DQ21 DQ19 DQ17 DQ22 H3 H2 DM2 DQS2 CKE CLK CLK# 60D4R3F DM1 DQS1 K13 G13 G12 J13 F13 K12 F12 J12 R387 H12 H13 of U7C MDB63 MDB59 MDB58 MDB60 MDB56 MDB62 MDB57 MDB61 N12 VDDRC_CLK1+M11 VDDRC_CLK1- M12 CKEB 10R3-U 0R3-U VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL MCL/DSF VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ B4 B11 D4 D5 D6 D9 D10 D11 E6 E9 F5 F10 G5 G10 H5 H10 J5 J10 K5 K10 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS E5 E7 E8 E10 K6 K7 K8 K9 L5 L10 VREF N13 C577 C589 C VGA_MEM_S0 HY5DS573222F-U R20 1KR3F C22 SCD1U16V B VDDR_VREF4 CLOSE TO MEM HY5DS573222F-U D MEMB_DM3 MEMB_DQS3 DQ8 DQ12 DQ13 DQ10 DQ14 DQ9 DQ15 DQ11 2R390 R386 BA0 BA1 NC#M10 1 C592 K13 G13 G12 J13 F13 K12 F12 J12 HY5DS573222F-U C23 SCD1U16V R21 1KR3F HY5DS573222F-U U7E of MDB53 MDB54 MDB52 MDB51 MDB50 MDB49 MDB55 MDB48 VGA_MEM_S0 C25 SCD1U16V 1 R22 1KR3F 2 C24 SCD1U16V Layout trace 20 mil U8E of R23 1KR3F 2 C4 C11 H4 H11 L12 L13 M3 N3 MDB28 MDB29 MDB31 MDB25 MDB26 MDB27 MDB24 MDB30 VDDR_VREF3 2 1 C580 HY5DS573222F-U CLOSE TO MEM HY5DS573222F-U of U8C N13 A 51 CLOSE TO MEM !! E5 E7 E8 E10 K6 K7 K8 K9 L5 L10 HY5DS573222F-U SC22U10V6ZY-U VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS DM0 DQS0 CLKB1 CLKB#1 N4 M5 M10 C3 C5 C7 C8 C10 C12 E3 E12 F4 F11 G4 G11 J4 J11 K4 K11 F6 F7 F8 F9 G6 G7 G8 G9 H6 H7 H8 H9 J6 J7 J8 J9 NC#C4 NC#C11 NC#H4 NC#H11 NC#L12 NC#L13 NC#M3 NC#N3 C567 SCD1U16V B3 B2 MEMB_DM4 MEMB_DQS4 MAB12 MAB13 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VGA_MEM_S0 1 60D4R3F B4 B11 D4 D5 D6 D9 D10 D11 E6 E9 F5 F10 G5 G10 H5 H10 J5 J10 K5 K10 DM0 DQS0 DQ3 DQ1 DQ2 DQ0 DQ6 DQ5 DQ4 DQ751 51 A0 A1 A2 A3 A4 A5 A6 A7 A8/AP A9 A10 A11 NC#L9 D7 D8 E4 E11 L4 L7 L8 L11 R412 60D4R3F VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ B3 B2 B5 C6 B6 B7 D2 D3 C2 E2 N5 N6 M6 N7 N8 M9 N9 N10 N11 M8 L6 M7 L9 VDD VDD VDD VDD VDD VDD VDD VDD C4 C11 H4 H11 L12 L13 M3 N3 2 R391 CLOSE TO MEM !! CKE CLK CLK# DQ3 DQ1 DQ2 DQ0 DQ6 DQ5 DQ4 DQ7 RAS# CAS# WE# CS# NC#M4 Layout trace 20 mil D12 D13 E13 C9 B10 B8 C13 B9 DQ26 DQ25 DQ24 DQ30 DQ28 DQ31 DQ27 DQ29 B12 B13 DM3 DQS3 MEMB_DM4 MEMB_DM7R420 MEMB_DM5R398 MEMB_DM6R400 R418 MEMB_DQS4 MEMB_DQS7 R421 MEMB_DQS5 R399 MEMB_DQS6 R401 R419 CKEB N12 VDDRC_CLK0+M11 VDDRC_CLK0- M12 10R3-U 0R3-U BC753_1 B R403 R402 C3 C5 C7 C8 C10 C12 E3 E12 F4 F11 G4 G11 J4 J11 K4 K11 MDB32 MDB33 MDB34 MDB35 MDB36 MDB38 MDB37 MDB39 B5 C6 B6 B7 D2 D3 C2 E2 of U7B VGA_MEM_S0 BA0 BA1 NC#M10 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ MEMB_DM0 MEMB_DQS0 N4 M5 M10 D7 D8 E4 E11 L4 L7 L8 L11 MAB12 MAB13 C VDD VDD VDD VDD VDD VDD VDD VDD A0 A1 A2 A3 A4 A5 A6 A7 A8/AP A9 A10 A11 NC#L9 RAS# CAS# WE# CS# NC#M4 SC22U10V6ZY-U N5 N6 M6 N7 N8 M9 N9 N10 N11 M8 L6 M7 L9 MDB7 MDB6 MDB5 MDB4 MDB1 MDB0 MDB2 MDB3 MAB0 MAB1 MAB2 MAB3 MAB4 MAB5 MAB6 MAB7 MAB8 MAB9 MAB10 MAB11 2 2 M2 L2 L3 N2 M4 of U8B BC754_1 RASB# CASB# WEB# CSB#0 CSB#1 C77 C63 SC330P50V2KX SCD01U16V2KX C21 SCD01U16V2KX of U8A CLKB0 CLKB#0 1 1 1 C566 C565 C552 C564 C539 C540 C575 C576 SC330P50V2KX SC330P50V2KX SC330P50V2KX SC330P50V2KX SC330P50V2KX SC330P50V2KX SC330P50V2KX SC330P50V2KX 2 1 D M2 L2 L3 N2 M4 QSB[7 0] DQMB#[7 0] 51 51 of U7A SC22U10V6ZY-U MAB[13 0] C76 SCD1U16V MDB[63 0] 51 2 C75 SCD1U16V C542 SCD1U16V C579 SCD1U16V 2 C541 SCD1U16V 1 C570 SCD1U16V C569 SCD1U16V C578 SCD1U16V 2 C568 SCD1U16V 1 C553 SCD1U16V 2 1 VGA_MEM_S0 51 SC22U10V6ZY-U All dampings in this page must near the VRAM VGA_MEM_S0 NC#C4 NC#C11 NC#H4 NC#H11 NC#L12 NC#L13 NC#M3 NC#N3 MDB20 MDB23 MDB22 MDB16 MDB19 MDB17 MDB21 MDB18 MEMB_DM2 MEMB_DQS2 D12 D13 E13 C9 B10 B8 C13 B9 DQ26 DQ25 DQ24 DQ30 DQ28 DQ31 DQ27 DQ29 B12 B13 DM3 DQS3 MEMB_DM6 MEMB_DQS6 DQMB#4 DQMB#7 DQMB#5 DQMB#6 1 15R2J 15R2J 15R2J 15R2J 1 15R2J 15R2J 115R2J 15R2J QSB4 QSB7 QSB5 QSB6 HY5DS573222F-U HY5DS573222F-U MEMB_DM0 MEMB_DM3R424 MEMB_DM1R404 MEMB_DM2R407 R423 MEMB_DQS0 MEMB_DQS3 R425 MEMB_DQS1 R4052 MEMB_DQS2 R406 R422 A 115R2J 115R2J 115R2J 15R2J 115R2J 115R2J 115R2J 15R2J DQMB#0 DQMB#3 DQMB#1 DQMB#2 QSB0 QSB3 QSB1 QSB2 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title VGA VRAM (DDR) (2/2) Size A3 Document Number Rev SA SNIPE Date: Thursday, November 18, 2004 Sheet 53 of 56 G16 1D8V_S0 G14 VGA_MEM_S0 2D5V_S0 RN58 D GAP-OPEN-PWR GAP-OPEN-PWR G20 449 449 449 449 ATI_TXBCLK+ ATI_TXBCLKATI_TXBOUT2+ ATI_TXBOUT2- 449 449 449 449 ATI_TXBOUT1+ ATI_TXBOUT1ATI_TXBOUT0+ ATI_TXBOUT0- GAP-OPEN-PWR 449 449 449 449 ATI_TXACLK+ ATI_TXACLKATI_TXAOUT2+ ATI_TXAOUT2- ATI_TXAOUT1+ ATI_TXAOUT1ATI_TXAOUT0+ ATI_TXAOUT0- 17 17 17 17 LCD_TXACLK+ LCD_TXACLKLCD_TXAOUT2+ LCD_TXAOUT2- LCD_TXBOUT1+ LCD_TXBOUT1LCD_TXBOUT0+ LCD_TXBOUT0- 17 17 17 17 17 17 17 17 LCD_TXAOUT1+ LCD_TXAOUT1LCD_TXAOUT0+ LCD_TXAOUT0- LCD_TXACLK+ 17 LCD_TXACLK- 17 LCD_TXAOUT2+ 17 LCD_TXAOUT2- 17 17 17 17 17 LCD_TXBOUT1+ LCD_TXBOUT1LCD_TXBOUT0+ LCD_TXBOUT0- G6 LCD_TXAOUT1+ LCD_TXAOUT1LCD_TXAOUT0+ LCD_TXAOUT0- LCD_TXBCLK+ LCD_TXBCLKLCD_TXBOUT2+ LCD_TXBOUT2- GAP-OPEN-PWR 449 449 449 449 GAP-OPEN-PWR TXACLK+ 13 TXACLK- 13 TXAOUT2+ 13 TXAOUT2- 13 TXAOUT1+ TXAOUT1TXAOUT0+ TXAOUT0- 13 13 13 13 TXBOUT1+ TXBOUT1TXBOUT0+ TXBOUT0- 13 13 13 13 TXBCLK+ 13 TXBCLK- 13 TXBOUT2+ 13 TXBOUT2- 13 D SRN0-1-U RN63 SRN0-1-U RN61 SRN0-1-U RN65 SRN0-1-U RN60 GAP-OPEN-PWR G17 LCD_TXBCLK+ 17 LCD_TXBCLK- 17 LCD_TXBOUT2+ 17 LCD_TXBOUT2- 17 SRN0-1-U RN59 G10 RN64 SRN0-1-U RN62 17 17 17 17 17 17 17 17 SRN0-1-U SRN0-1-U C C G19 G9 GAP-OPEN-PWR 449 449 449 449 GAP-OPEN-PWR G18 449 ATI_RED 449 ATI_GREEN 449 ATI_BLUE G7 GAP-OPEN-PWR R372 R377 R375 R373 ATI_LCDVDD_ON ATI_TV_COMP ATI_TV_LUMA ATI_TV_CRMA 449 449 449 449 GAP-OPEN-PWR ATI_HSYNC ATI_VSYNC ATI_DDCDATA ATI_DDCCLK 1 1 2 2 0R2-0 0R2-0 0R2-0 0R2-0 LCD_VDD_ON TVCOMP 16 TVLUMA 16 TVCRMA 16 R332 R333 R334 2 0R2-0 0R2-0 0R2-0 R369 R368 R367 R356 2 2 0R2-0 0R2-0 0R2-0 0R2-0 1 1 17 16 16 16 16 CRT_VSYNC CRT_HSYNC CRT_BLUE CRT_GREEN CRT_RED 16 CRT_GREEN 16 CRT_BLUE 16 16 16 16 16 CRT_RED TVLUMA TVCRMA TVCOMP CRT_HSYNC 16 CRT_VSYNC 16 CRT_DAT_DDC_3 16 CRT_CLK_DDC_3 16 17 LCD_VDD_ON R371 R370 R366 R365 1 1 2 2 0R2-0 0R2-0 0R2-0 0R2-0 MAIN_JVGA_VS 13 MAIN_JVGA_HS 13 MAIN_CRT_B 13 MAIN_CRT_G 13 R364 R376 R374 R378 1 1 2 2 0R2-0 0R2-0 0R2-0 0R2-0 MAIN_CRT_R 13 RS480_TV_LUMA 13 RS480_TV_CRMA 13 RS480_TV_COMP 13 RN71 16 CRT_DAT_DDC_3 16 CRT_CLK_DDC_3 LCDVDD_ON 13 VGA_DAT_DDC_3 13 VGA_CLK_DDC_3 13 SRN0-1-U B B G26 G23 1D2V_VGA_S0 G25 GAP-OPEN-PWR 2 GAP-OPEN-PWR 3D3V_S0 GAP-OPEN-PWR U25 VGA_LOCAL_DP 449 VGA_LOCAL_DP GAP-OPEN-PWR G24 449 VGA_LOCAL_DN C179 SC2200P50V2KX VGA_LOCAL_DN VCC DXP DXN THERM# SMBCLK SMBDATA ALERT# GND VGA_ALERT#1 R141 2K2R2 VGA_SMB_CLK 13,449 VGA_SMB_DAT 13,449 3D3V_S0 1 VGA_CORE_S0 1D2V_S0 C180 SCD1U G781 R143 place near GPU 0R2-0 R142 23 VGA_THERM_DN A A 23 VGA_REMOTE_DP 0R2-0 Wistron Corporation Q31 S2N3904-U2 C725 SC470P50V2KX 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C 23 VGA_THERM_DP Title VGA SELECTOR 23 VGA_REMOTE_DN Size A3 Document Number Rev SA SNIPE Date: Thursday, November 18, 2004 Sheet 54 of 56 A B C D E VGA_CORE_S0 VGA_CORE_PWR G96 FAN5234 FOR VGA_Core DCBATOUT DCBATOUT_5234 GAP-OPEN-PWR G92 GAP-OPEN-PWR G39 GAP-OPEN-PWR G109 GAP-OPEN-PWR G35 GAP-OPEN-PWR G36 GAP-OPEN-PWR G34 GAP-OPEN-PWR G94 GAP-OPEN-PWR G95 GAP-OPEN-PWR G37 GAP-OPEN-PWR GAP-OPEN-PWR G97 2 DCBATOUT_5234 S SCD1U25V3KX PGOOD 10R5 FAN5234MTCX 2 C294 SCD01U16V2KX G C287 SCD1U25V3KX U76 APM3011NU TPAD30 R214 40K2R3F 5V_S0 D TP30 S 300KHz Id=60A,Qg=22~28nC Rdson=14~18mohm USD:0.15 R228 10KR3 R213 C286 698R3F SCD01U16V2KX R229 DUMMY-R3 R212 2KR2F 2 PWM Mode: FPWM (High)=>Fixed PWM Mode FPWM (Low)=>Hysteretic Mode C818 SCD1U 5234_HDRV 5234_LDRV TC20 ST220U2D5VBM 77.C2271.031 14 10 HDRV LDRV VSEN VOUT VIN VCC 5234_VIN VGA_CORE_PWR L45 IND-2D2UH-4 R217 1 5234_VSEN DCBATOUT_5234 2 11 10KR2 1 5234_ISEN 5234_SW 12 13 ISNS SW Vishay IHCP-5050 Imax=16A, DCR=8mohm 12.9*13.58*3.5, NTD:11.05 R227 1K2R3F PM_SLP_S3# 5234_SS 5234_ILIM 5234_EN 1D2V or 1D15V Iomax=11 or 5.2A OCP>20A DY IND-2D2UH-18 PGND AGND 2 18,21,34,38,39,43,44 R215 FPWM BOOT SS ILIM EN GAP-OPEN-PWR L61 U34 16 15 GAP-OPEN-PWR G93 TC21 ST330U3VDM GAP-OPEN-PWR G40 1 5234_BOOT SSM5818SL G D34 C833 SC10U25V6MX Id=30A,Qg=15~20nC Rdson=22~28mohm USD:0.12 C835 SCD1U U78 APM3023NUCTR C312 R216 DUMMY-R2 C834 SC10U25V6MX GAP-OPEN-PWR 2 D C311 SCD1U16V GAP-OPEN-PWR G110 GAP-OPEN-PWR G107 5V_S0 GAP-OPEN-PWR G106 GAP-OPEN-PWR G108 C847 SC4D7U10V5ZY GAP-OPEN-PWR G91 G105 5V_S0 GAP-OPEN-PWR G98 VGA_CORE_S0 G38 NEC B2 Size 220uF 2.5V ESR=35mohm Iripple=1.558A NTD:6.37 KEMET V Size 330uF 3V ESR=15mohm, Iripple=2.9A NTD:9.5 2 Vo=1.20V, R1775=0.698Kohm(R3F) =>Vo(cal.)=1.2141V Rilim=(11.2/Iilim)*((100+Rsense)/Rdson) for M26 & M22 3D3V_S0 G21 C777 SC10U10V5ZY G22 GAP-OPEN-PWR TC3 ST100U6D3VBM GAP-OPEN-PWR R558 10KR3F Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C C779 SCD1U 1 APL5332KAC U26 1 R557 8K66R3F VIN BS FB VOUT NC#8 NC#7 GND NC#5 GND 1D5V_VGA_S0 C778 SC10U10V5ZY 2 EPCI_PWR Title FAN5234_VGA_CORE_1D20V or 1D15V Size A3 Document Number Date: Thursday, November 18, 2004 A B C D Rev SA SNIPE Sheet E 55 of 56 HOLE6 HOLE HOLE13 HOLE HOLE14 HOLE HOLE12 HOLE HOLE24 HOLE HOLE1 HOLE HOLE15 HOLE HOLE17 HOLE HOLE4 HOLE HOLE29 HOLE HOLE30 HOLE HOLE10 HOLE D HOLE26 HOLE 1 TSAHCT125 TSAHCT125 TSLCX14MTC-L-U TSLCX14MTC-L-U C 3D3V_S0 3D3V_S0 U73E VPP_ASKT_S0 VPP_BSKT_S0 3D3V_S5 10 13 TSLCX14MTC-L-U EC6 SCD1U HOLE28 HOLE7 HOLE3 HOLE9 HOLE18 HOLE11 HOLE16 HOLE25 HOLE20 B 1 1 1 1 EC17 SCD1U B 1 HOLE27 12 TSLCX14MTC-L-U EC5 SCD1U 1 11 EC9 SCD1U U73F 14 14 2D5V_S3 1 14 14 11 U73D 12 1 1 13 14 U73C U47D 3D3V_S0 EC7 SCD1U EC10 SCD1U 1 U47C DVI_VCC 3D3V_S0 5V_S0 10 14 2D5V_S0 HOLE19 HOLE 1 1 1 HOLE23 HOLE 5V_S0 EC15 SCD1U 2 EC19 SCD1U HOLE22 HOLE EC14 SCD1U 1D8V_S5 5V_S5 C HOLE5 HOLE 1 EC13 SCD1U EC3 SCD1U EC20 SCD1U EC4 SCD1U 2 HOLE21 HOLE 1D8V_S0 EC12 SCD1U 1 EC2 SCD1U D 5V_S0 HOLE8 HOLE EC16 SCD1U EC1 SCD1U 1 EC8 SCD1U EC18 SCD1U 2 EC11 SCD1U HOLE2 HOLE 3D3V_S3 3D3V_S0 DY DY DY GND15 GND13 DY 1 GND9 DY DY GND16 SPRING-23 DY DY 1 GND19 GND7 SPRING-24 1 GND3 SPRING-1 DY GND20 GNDPAD GND18 GNDPAD GND4 SPRING-1 GND1 SPRING-1 1 GND11 GNDPAD DY DY DY A A GND6 GNDPAD DY DY 1 DY GND14 GNDPAD DY GND5 GNDPAD DY GND12 GNDPAD DY GND10 GNDPAD GND8 GNDPAD GND2 DY 1 GND21 GND22 GND24 GND25 GNDPAD GNDPAD GNDPAD GNDPAD DY DY DY DY Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title EMI COMPONENTS Size A3 Document Number Rev SA SNIPE Date: Thursday, November 18, 2004 Sheet 56 of 56 ... from 0R2 to 10Kr2 C C B B A A Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title CHANGE HISTORY Size A3 Document Number SNIPE Date: Thursday, November... 2K2R2 DY FS2 Wistron Corporation R1602 DUMMY-R2 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C DY Title CLKGEN_IDTCV137 Size A3 Document Number Rev A B C D SA SNIPE Date:... BGA754-SKT-U Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title CPU(1/4)_HyperTransport I/F Size A3 Document Number Rev A B C D SA SNIPE Date: