Acer aspire e1 v1 v3 531 571 COMPAL LA 7912p REV 02

A B C D E Compal Confidential Model Name :Q5WV1/Q5WS1 Compal Project Name : File Name : LA-7912P Compal Confidential 2 Q5WV1 M/B Schematics Document Intel Sandy/Ivy Bridge Processor with DDRIII + Panther Point PCH Nvidia N13P GS/GL 2011-12-24 REV:0.2 ZZZ2 1G@ ZZZ3 2G@ MB PCB Part Number Description DA60000SV00 PCB 0N4 LA-7912P REV0 M/B X76344BOL01 X76344BOL02 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2011/06/02 2012/06/02 Deciphered Date Title SCHEMATIC,MB A7912 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C D Rev B 4019ID Sheet Friday, January 06, 2012 E of 60 A B C D E Fan Control page 42 1 100MHz PEG(DIS) PCI-E 2.0x16 5GT/s PER LANE Nvidia N13P GS/GL Memory BUS(DDRIII) 204pin DDRIII-SO-DIMM X2 Dual Channel Intel Sandy/Ivy Bridge 133MHz page 11,12 BANK 0, 1, 2, 1.5V DDRIII 1066/1333 Processor page22~30 eDP rPGA989 page31 page 4~10 FDI x8 HDMI Conn page 33 CRT Conn LVDS Conn page 32 page 31 DMI x4 100MHz 100MHz 2.7GT/s 1GB/s x4 LVDS(UMA/OPTIMUS) CRT(UMA/OPTIMUS) TMDS(UMA/OPTIMUS) Intel Panther Point-M USB 2.0 conn x2 Bluetooth Conn CMOS Camera USB port 0,1 on USB/B page 38 USB port 13 USB port 10 page 38 USBx14 3.3V 48MHz HD Audio 3.3V 24MHz page 31 PCH port port USB 3.0 conn x1 Fresco FL1009 with USB3.0 Conn MINI Card x1 WLAN USB port 11 page 37 page 45 port SATA x (GEN1 1.5GT/S ,GEN2 3GT/S) port LAN(GbE) & Card Reader BCM57785 page 35,36 port Card Reader Conn page 35,36 RJ45 USB port page 34 page 36 port ALC271X/281X 989pin BGA 100MHz SATA HDD Conn page 34 MSATA(WWAN) HDA Codec 100MHz PCI-Express x (ARD PCIE2.0 2.5GT/s) page 41 SPI page 13~21 port SPI ROM x1 Int Speaker page 13 SATA CDROM Conn page 34 page 41 Phone Jack x page 41 LPC BUS 33MHz ENE KB930/KB9012 page 39 RTC CKT page 13 Int.KBD Touch Pad page 40 Power On/Off CKT page 40 DC/DC Interface CKT page 40 Sub-board LS-7911P USB 2.0/B 2Port USB Port0,1 BIOS ROM page 39 page 40 page 43,44 LS-7912P Power Circuit DC/DC page 46~59 PWR/B page 41 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2011/06/02 2012/06/02 Deciphered Date Title SCHEMATIC,MB A7912 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C D Rev B 4019ID Sheet Friday, January 06, 2012 E of 60 A B C D Voltage Rails Power Plane Description S1 S3 S5 VIN Adapter power supply (19V) N/A N/A N/A BATT+ Battery power supply (12.6V) N/A N/A N/A B+ AC or battery power rail for power circuit N/A N/A N/A +CPU_CORE Core voltage for CPU ON OFF OFF +VGA_CORE Core voltage for GPU ON OFF OFF +VGFX_CORE Core voltage for UMA graphic ON OFF OFF +0.75VS +0.75VP to +0.75VS switched power rail for DDR terminator ON OFF OFF +1.05VSDGPU +1.0VSPDGPU to +1.0VSDGPU switched power rail for GPU ON OFF OFF +1.05VS_VTT +1.05VS_VCCPP to +1.05VS_VCCP switched power rail for CPU ON OFF OFF +1.05VS_PCH +1.05VS_VCCP to +1.05VS_PCH power for PCH ON OFF OFF +1.5V +1.5VP to +1.5V power rail for DDRIII ON ON OFF +1.5VS +1.5V to +1.5VS switched power rail ON OFF OFF Vcc Ra/Rc/Re +1.5VSDGPU +1.5VS to +1.5VSDGPU switched power rail for GPU ON OFF OFF Board ID +1.8VS (+5VALW or +3VALW) to 1.8V switched power rail to PCH & GPU ON OFF OFF +1.8VSDGPU +1.8VS to +1.8VSDGPU switched power rail for GPU ON OFF OFF +3VALW +3VALW always on power rail ON ON ON* +3VALW_EC +3VALW always to KBC ON ON ON* +3V_LAN +3VALW to +3V_LAN power rail for LAN ON ON ON* +3VALW_PCH +3VALW to +3VALW_PCH power rail for PCH (Short Jumper) ON ON ON* +3VS +3VALW to +3VS power rail ON OFF OFF +5VALW +5VALWP to +5VALW power rail ON ON ON* +5VALW_PCH +5VALW to +5VALW_PCH power rail for PCH (Short resister) ON ON ON* +5VS +5VALW to +5VS switched power rail ON OFF OFF +VSB +VSBP to +VSB always on power rail for sequence control ON ON ON* +RTCVCC RTC power ON ON ON Full ON Device Address Smart Battery 0001 011X b Address Clock Generator (9LVS3199AKLFT, RTM890N-631-VB-GRT) 1101 0010b DDR DIMM0 1001 000Xb DDR DIMM2 1001 010Xb +V +VS Clock HIGH HIGH HIGH ON ON ON ON S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF 3.3V +/- 5% 100K +/- 5% Rb / Rd / Rf 8.2K +/- 5% 18K +/- 5% 33K +/- 5% 56K +/- 5% 100K +/- 5% 200K +/- 5% NC Board ID Address PCH SM Bus address Device +VALW HIGH V AD_BID V 0.216 V 0.436 V 0.712 V 1.036 V 1.453 V 1.935 V 2.500 V V AD_BID typ V 0.250 V 0.503 V 0.819 V 1.185 V 1.650 V 2.200 V 3.300 V BOARD ID Table EC SM Bus2 address Device SLP_S1# SLP_S3# SLP_S4# SLP_S5# PCB Revision 0.1 0.2 0.3 0.4 USB Port Table USB 2.0 USB 1.1 Port UHCI0 UHCI1 EHCI1 UHCI2 UHCI3 UHCI4 EHCI2 UHCI5 UHCI6 10 11 12 13 2011/06/02 External USB Port USB3.0 colay USB2.0 Conn USB/B (Right Side) USB/B (Right Side) BTO Item UMA Only Dis with OPTIMUS Blue Tooth Internal USB 3.0 eDP VRAM Connector Unpop N13P-GS N13P-GL Win8 Audio ALC271X Audio ALC281X PCH HM65 PCH HM76 BOM Structure UMAO@ DIS@ BT@ PUSB@ eDP@ X76@ CONN@ @ GS@ GL@ Win8@ 271X@ 281X@ HM65@ HM76@ Camera BlueTooth Compal Electronics, Inc 2012/06/02 Deciphered Date Title SCHEMATIC,MB A7912 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C Mini Card 1(WLAN) Compal Secret Data Security Classification Issued Date V AD_BID max V 0.289 V 0.538 V 0.875 V 1.264 V 1.759 V 2.341 V 3.300 V BTO Option Table BT & USB30 & USB20 Config N13P-GF108_ES4:GF108@ OPTMIUS SKU:DIS@ N13P-GL:GL@ N13P-GS:GS@ BT SKU:BT@ internal USB SKU: PUSB@ DIS USB30 SKU:DUSB@ eDP SKU: EDP@ LVDS SKU: LVDS@ EC 930 SKU: 930@ EC 9012 SKU: 9012@ PCH HM65: HM65@ PCH HM76: HM76@ Win8: WIN8@ Board ID / SKU ID Table for AD channel Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF EC SM Bus1 address SIGNAL STATE E D Rev B 4019ID Sheet Friday, January 06, 2012 E of 60 +1.05VS_VTT D R517 24.9_0402_1% B27 B25 A25 B24 DMI_RX#[0] DMI_RX#[1] DMI_RX#[2] DMI_RX#[3] DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3 B28 B26 A24 B23 DMI_RX[0] DMI_RX[1] DMI_RX[2] DMI_RX[3] DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3 G21 E22 F21 D21 DMI_TX#[0] DMI_TX#[1] DMI_TX#[2] DMI_TX#[3] DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3 G22 D22 F20 C21 DMI_TX[0] DMI_TX[1] DMI_TX[2] DMI_TX[3] FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7 A21 H19 E19 F18 B21 C20 D18 E17 FDI0_TX#[0] FDI0_TX#[1] FDI0_TX#[2] FDI0_TX#[3] FDI1_TX#[0] FDI1_TX#[1] FDI1_TX#[2] FDI1_TX#[3] FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7 A22 G19 E20 G18 B20 C19 D19 F17 FDI0_TX[0] FDI0_TX[1] FDI0_TX[2] FDI0_TX[3] FDI1_TX[0] FDI1_TX[1] FDI1_TX[2] FDI1_TX[3] FDI_FSYNC0 FDI_FSYNC1 J18 J17 FDI0_FSYNC FDI1_FSYNC FDI_INT H20 FDI_INT FDI_LSYNC0 FDI_LSYNC1 J19 H17 FDI0_LSYNC FDI1_LSYNC A18 A17 B16 eDP_COMPIO eDP_ICOMPO eDP_HPD# EDP_AUXP EDP_AUXN C15 D15 eDP_AUX eDP_AUX# EDP_TXP0 EDP_TXP1 C17 F16 C16 G15 eDP_TX[0] eDP_TX[1] eDP_TX[2] eDP_TX[3] EDP_TXN0 EDP_TXN1 C18 E16 D16 F15 eDP_TX#[0] eDP_TX#[1] eDP_TX#[2] eDP_TX#[3] PCI EXPRESS* - GRAPHICS DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 DMI_CRX_PTX_N3 DMI +1.05VS_VTT R145 24.9_0402_1% EDP_COMP B EDP_HPD# Add eDP circuit +1.05VS_VTT PEG_COMP D PEG_ICOMPI and PEG_RCOMPO signals should be shorted and routed, max length = 500 mils,trace width=4mils PEG_ICOMPO signals should be routed with - max length = 500 mils,trace width=12mils spacing =15mils PEG_ICOMPI PEG_ICOMPO PEG_RCOMPO J22 J21 H22 PEG_RX#[0] PEG_RX#[1] PEG_RX#[2] PEG_RX#[3] PEG_RX#[4] PEG_RX#[5] PEG_RX#[6] PEG_RX#[7] PEG_RX#[8] PEG_RX#[9] PEG_RX#[10] PEG_RX#[11] PEG_RX#[12] PEG_RX#[13] PEG_RX#[14] PEG_RX#[15] K33 M35 L34 J35 J32 H34 H31 G33 G30 F35 E34 E32 D33 D31 B33 C32 PEG_GTX_C_HRX_N15 PEG_GTX_C_HRX_N14 PEG_GTX_C_HRX_N13 PEG_GTX_C_HRX_N12 PEG_GTX_C_HRX_N11 PEG_GTX_C_HRX_N10 PEG_GTX_C_HRX_N9 PEG_GTX_C_HRX_N8 PEG_GTX_C_HRX_N7 PEG_GTX_C_HRX_N6 PEG_GTX_C_HRX_N5 PEG_GTX_C_HRX_N4 PEG_GTX_C_HRX_N3 PEG_GTX_C_HRX_N2 PEG_GTX_C_HRX_N1 PEG_GTX_C_HRX_N0 C46 C49 C51 C53 C60 C71 C75 C82 C92 C93 C102 C111 C113 C125 C129 C144 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 GSGL@ GSGL@ GSGL@ GSGL@ GSGL@ GSGL@ GSGL@ GSGL@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K PEG_GTX_HRX_N15 PEG_GTX_HRX_N14 PEG_GTX_HRX_N13 PEG_GTX_HRX_N12 PEG_GTX_HRX_N11 PEG_GTX_HRX_N10 PEG_GTX_HRX_N9 PEG_GTX_HRX_N8 PEG_GTX_HRX_N7 PEG_GTX_HRX_N6 PEG_GTX_HRX_N5 PEG_GTX_HRX_N4 PEG_GTX_HRX_N3 PEG_GTX_HRX_N2 PEG_GTX_HRX_N1 PEG_GTX_HRX_N0 PEG_RX[0] PEG_RX[1] PEG_RX[2] PEG_RX[3] PEG_RX[4] PEG_RX[5] PEG_RX[6] PEG_RX[7] PEG_RX[8] PEG_RX[9] PEG_RX[10] PEG_RX[11] PEG_RX[12] PEG_RX[13] PEG_RX[14] PEG_RX[15] J33 L35 K34 H35 H32 G34 G31 F33 F30 E35 E33 F32 D34 E31 C33 B32 PEG_GTX_C_HRX_P15 PEG_GTX_C_HRX_P14 PEG_GTX_C_HRX_P13 PEG_GTX_C_HRX_P12 PEG_GTX_C_HRX_P11 PEG_GTX_C_HRX_P10 PEG_GTX_C_HRX_P9 PEG_GTX_C_HRX_P8 PEG_GTX_C_HRX_P7 PEG_GTX_C_HRX_P6 PEG_GTX_C_HRX_P5 PEG_GTX_C_HRX_P4 PEG_GTX_C_HRX_P3 PEG_GTX_C_HRX_P2 PEG_GTX_C_HRX_P1 PEG_GTX_C_HRX_P0 C47 C50 C52 C56 C66 C68 C81 C86 C89 C100 C105 C106 C117 C119 C135 C138 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 GSGL@ GSGL@ GSGL@ GSGL@ GSGL@ GSGL@ GSGL@ GSGL@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K PEG_GTX_HRX_P15 PEG_GTX_HRX_P14 PEG_GTX_HRX_P13 PEG_GTX_HRX_P12 PEG_GTX_HRX_P11 PEG_GTX_HRX_P10 PEG_GTX_HRX_P9 PEG_GTX_HRX_P8 PEG_GTX_HRX_P7 PEG_GTX_HRX_P6 PEG_GTX_HRX_P5 PEG_GTX_HRX_P4 PEG_GTX_HRX_P3 PEG_GTX_HRX_P2 PEG_GTX_HRX_P1 PEG_GTX_HRX_P0 PEG_TX#[0] PEG_TX#[1] PEG_TX#[2] PEG_TX#[3] PEG_TX#[4] PEG_TX#[5] PEG_TX#[6] PEG_TX#[7] PEG_TX#[8] PEG_TX#[9] PEG_TX#[10] PEG_TX#[11] PEG_TX#[12] PEG_TX#[13] PEG_TX#[14] PEG_TX#[15] M29 M32 M31 L32 L29 K31 K28 J30 J28 H29 G27 E29 F27 D28 F26 E25 PEG_HTX_GRX_N15 PEG_HTX_GRX_N14 PEG_HTX_GRX_N13 PEG_HTX_GRX_N12 PEG_HTX_GRX_N11 PEG_HTX_GRX_N10 PEG_HTX_GRX_N9 PEG_HTX_GRX_N8 PEG_HTX_GRX_N7 PEG_HTX_GRX_N6 PEG_HTX_GRX_N5 PEG_HTX_GRX_N4 PEG_HTX_GRX_N3 PEG_HTX_GRX_N2 PEG_HTX_GRX_N1 PEG_HTX_GRX_N0 C516 C520 C529 C534 C538 C540 C542 C544 C546 C548 C550 C552 C554 C556 C558 C560 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 GSGL@ GSGL@ GSGL@ GSGL@ GSGL@ GSGL@ GSGL@ GSGL@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ 0.22U_0402_10V6KPEG_HTX_C_GRX_N15 0.22U_0402_10V6KPEG_HTX_C_GRX_N14 0.22U_0402_10V6KPEG_HTX_C_GRX_N13 0.22U_0402_10V6KPEG_HTX_C_GRX_N12 0.22U_0402_10V6KPEG_HTX_C_GRX_N11 0.22U_0402_10V6KPEG_HTX_C_GRX_N10 0.22U_0402_10V6K PEG_HTX_C_GRX_N9 0.22U_0402_10V6K PEG_HTX_C_GRX_N8 0.22U_0402_10V6K PEG_HTX_C_GRX_N7 0.22U_0402_10V6K PEG_HTX_C_GRX_N6 0.22U_0402_10V6K PEG_HTX_C_GRX_N5 0.22U_0402_10V6K PEG_HTX_C_GRX_N4 0.22U_0402_10V6K PEG_HTX_C_GRX_N3 0.22U_0402_10V6K PEG_HTX_C_GRX_N2 0.22U_0402_10V6K PEG_HTX_C_GRX_N1 0.22U_0402_10V6K PEG_HTX_C_GRX_N0 PEG_TX[0] PEG_TX[1] PEG_TX[2] PEG_TX[3] PEG_TX[4] PEG_TX[5] PEG_TX[6] PEG_TX[7] PEG_TX[8] PEG_TX[9] PEG_TX[10] PEG_TX[11] PEG_TX[12] PEG_TX[13] PEG_TX[14] PEG_TX[15] M28 M33 M30 L31 L28 K30 K27 J29 J27 H28 G28 E28 F28 D27 E26 D25 PEG_HTX_GRX_P15 PEG_HTX_GRX_P14 PEG_HTX_GRX_P13 PEG_HTX_GRX_P12 PEG_HTX_GRX_P11 PEG_HTX_GRX_P10 PEG_HTX_GRX_P9 PEG_HTX_GRX_P8 PEG_HTX_GRX_P7 PEG_HTX_GRX_P6 PEG_HTX_GRX_P5 PEG_HTX_GRX_P4 PEG_HTX_GRX_P3 PEG_HTX_GRX_P2 PEG_HTX_GRX_P1 PEG_HTX_GRX_P0 C515 C528 C533 C536 C539 C541 C543 C545 C547 C549 C551 C553 C555 C557 C559 C561 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 GSGL@ GSGL@ GSGL@ GSGL@ GSGL@ GSGL@ GSGL@ GSGL@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ 0.22U_0402_10V6KPEG_HTX_C_GRX_P15 0.22U_0402_10V6KPEG_HTX_C_GRX_P14 0.22U_0402_10V6KPEG_HTX_C_GRX_P13 0.22U_0402_10V6KPEG_HTX_C_GRX_P12 0.22U_0402_10V6KPEG_HTX_C_GRX_P11 0.22U_0402_10V6KPEG_HTX_C_GRX_P10 0.22U_0402_10V6K PEG_HTX_C_GRX_P9 0.22U_0402_10V6K PEG_HTX_C_GRX_P8 0.22U_0402_10V6K PEG_HTX_C_GRX_P7 0.22U_0402_10V6K PEG_HTX_C_GRX_P6 0.22U_0402_10V6K PEG_HTX_C_GRX_P5 0.22U_0402_10V6K PEG_HTX_C_GRX_P4 0.22U_0402_10V6K PEG_HTX_C_GRX_P3 0.22U_0402_10V6K PEG_HTX_C_GRX_P2 0.22U_0402_10V6K PEG_HTX_C_GRX_P1 0.22U_0402_10V6K PEG_HTX_C_GRX_P0 PEG_GTX_HRX_N[0 15] PEG_GTX_HRX_P[0 15] PEG_HTX_C_GRX_N[0 15] PEG_HTX_C_GRX_P[0 15] C B TYCO_2013620-2_IVY BRIDGE CONN@ EDP@ R809 1K_0402_5% eDP eDP_COMPIO and ICOMPO signals should be shorted near balls, Trace Width for EDP_COMPIO=4mils, EDP_ICOMPO=12mils, and both length less than 500 mils should not be left floating ,even if disable eDP function Intel(R) FDI C JCPU1A Typ- suggest 220nF The change in AC capacitor value from 100nF to 220nF is to enable compatibility with future platforms having PCIE Gen3 (8GT/s) EDP_HPD# A A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2011/06/02 2012/06/02 Deciphered Date Title SCHEMATIC,MB A7912 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: Rev B 4019ID Sheet Friday, January 06, 2012 of 60 D D AL33 CATERR# Processor Pullups +1.05VS_VTT C H_PECI R91 62_0402_5% R92 56_0402_5% H_PECI AN33 PECI H_PROCHOT# H_PROCHOT# H_THRMTRIP# H_THRMTRIP# H_PM_SYNC H_PM_SYNC R84 H_PROCHOT#_R AL32 PROCHOT# AN32 THERMTRIP# AM34 PM_SYNC AP33 UNCOREPWRGOOD 10K_0402_5% H_CPUPWRGD H_CPUPWRGD UNCOREPWRGOOD: CORE OK PM_DRAM_PWRGD_R V8 SM_DRAMPWROK SM_DRAMPWROK:DRAM power ok BUF_CPU_RST# AR33 RESET# A28 A27 CLK_CPU_DMI CLK_CPU_DMI# DPLL_REF_CLK DPLL_REF_CLK# A16 A15 CLK_CPU_DPLL CLK_CPU_DPLL# SM_DRAMRST# SM_RCOMP[0] SM_RCOMP[1] SM_RCOMP[2] R8 SM_DRAMRST# AK1 A5 A4 SM_RCOMP0 SM_RCOMP1 SM_RCOMP2 CLK_CPU_DMI CLK_CPU_DMI# For LVDS CLK_CPU_DPLL For CLK_CPU_DPLL# eDP CLK_CPU_DPLL CLK_CPU_DPLL# R231 R566 R571 R516 R518 LVDS@ 1K_0402_5% LVDS@ 1K_0402_5% +1.05VS_VTT If use External Graphic or use integrated without eDP DPLL_REF_SSCLK PD 1K_5% to GND DPLL_REF_SSCLK# PH 1K_5% to +1.05VS_VTT SM_DRAMRST# 140_0402_1% 25.5_0402_1% 200_0402_1% 2 C DDR3 Compensation Signals PRDY# PREQ# AP29 AP27 TCK TMS TRST# AR26 AR27 AP30 TCK TMS TRST# PAD PAD PAD T66 T67 T68 TDI TDO AR28 AP26 TDI TDO PAD PAD T69 T70 @ @ @ +3VS @ @ H_CATERR# @ BCLK BCLK# R40 1K_0402_5% PAD THERMAL T6 SKTOCC# CLOCKS AN34 DDR3 MISC PROC_SELECT# JTAG & BPM C26 H_SNB_IVB# MISC JCPU1B PWR MANAGEMENT SNB_IVB# had changed the name to PROC_SELCT#,function for future platform, connect to the DF_TVS strap on the PCH DBR# AL35 BPM#[0] BPM#[1] BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7] AT28 AR29 AR30 AT30 AP32 AR31 AT31 AR32 XDP_DBRESET# XDP_DBRESET# B B TYCO_2013620-2_IVY BRIDGE CONN@ Buffered reset to CPU +3VALW +3VS +1.5VS O PM_SYS_PWRGD_BUF R204 130_0402_5% PM_DRAM_PWRGD_R A B @ R88 0_0402_5% R203 39_0402_1% @ C? 0.1U_0402_16V4Z SN74LVC1G07DCKR_SC70-5 PM_DRAM_PWRGD BUF_CPU_RST# 200_0402_1% P SYS_PWROK R87 43_0402_1% G BUFO_CPU_RST# U11 74AHC1G09GW_TSSOP5 P A 1 G PLT_RST# Y PLT_RST# R90 75_0402_1% U7 NC R205 2 1 +1.05VS_VTT C162 0.1U_0402_16V4Z 1 C307 0.1U_0402_16V4Z RESET#: A ok CPU reset A R04 modify Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2011/06/02 2012/06/02 Deciphered Date Title SCHEMATIC,MB A7912 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: Rev B 4019ID Sheet Friday, January 06, 2012 of 60 JCPU1D DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63 D C DDR_A_BS0 DDR_A_BS1 DDR_A_BS2 B C5 D5 D3 D2 D6 C6 C2 C3 F10 F8 G10 G9 F9 F7 G8 G7 K4 K5 K1 J1 J5 J4 J2 K2 M8 N10 N8 N7 M10 M9 N9 M7 AG6 AG5 AK6 AK5 AH5 AH6 AJ5 AJ6 AJ8 AK8 AJ9 AK9 AH8 AH9 AL9 AL8 AP11 AN11 AL12 AM12 AM11 AL11 AP12 AN12 AJ14 AH14 AL15 AK15 AL14 AK14 AJ15 AH15 SA_DQ[0] SA_DQ[1] SA_DQ[2] SA_DQ[3] SA_DQ[4] SA_DQ[5] SA_DQ[6] SA_DQ[7] SA_DQ[8] SA_DQ[9] SA_DQ[10] SA_DQ[11] SA_DQ[12] SA_DQ[13] SA_DQ[14] SA_DQ[15] SA_DQ[16] SA_DQ[17] SA_DQ[18] SA_DQ[19] SA_DQ[20] SA_DQ[21] SA_DQ[22] SA_DQ[23] SA_DQ[24] SA_DQ[25] SA_DQ[26] SA_DQ[27] SA_DQ[28] SA_DQ[29] SA_DQ[30] SA_DQ[31] SA_DQ[32] SA_DQ[33] SA_DQ[34] SA_DQ[35] SA_DQ[36] SA_DQ[37] SA_DQ[38] SA_DQ[39] SA_DQ[40] SA_DQ[41] SA_DQ[42] SA_DQ[43] SA_DQ[44] SA_DQ[45] SA_DQ[46] SA_DQ[47] SA_DQ[48] SA_DQ[49] SA_DQ[50] SA_DQ[51] SA_DQ[52] SA_DQ[53] SA_DQ[54] SA_DQ[55] SA_DQ[56] SA_DQ[57] SA_DQ[58] SA_DQ[59] SA_DQ[60] SA_DQ[61] SA_DQ[62] SA_DQ[63] AE10 AF10 V6 SA_BS[0] SA_BS[1] SA_BS[2] AE8 AD9 AF9 SA_CAS# SA_RAS# SA_WE# DDR_A_CAS# DDR_A_RAS# DDR_A_WE# DDR SYSTEM MEMORY A DDR_A_D[0 63] SA_CLK[0] SA_CLK#[0] SA_CKE[0] AB6 AA6 V9 SA_CLK_DDR0 DDR_B_D[0 63] SA_CLK_DDR#0 DDRA_CKE0_DIMMA SA_CLK[1] SA_CLK#[1] SA_CKE[1] AA5 AB5 V10 SA_CLK_DDR1 SA_CLK_DDR#1 DDRA_CKE1_DIMMA RSVD_TP[1] RSVD_TP[2] RSVD_TP[3] AB4 AA4 W9 RSVD_TP[4] RSVD_TP[5] RSVD_TP[6] AB3 AA3 W10 SA_CS#[0] SA_CS#[1] RSVD_TP[7] RSVD_TP[8] AK3 AL3 AG1 AH1 DDRA_CS0_DIMMA# DDRA_CS1_DIMMA# SA_ODT[0] SA_ODT[1] RSVD_TP[9] RSVD_TP[10] AH3 AG3 AG2 AH2 SA_ODT0 SA_ODT1 SA_DQS#[0] SA_DQS#[1] SA_DQS#[2] SA_DQS#[3] SA_DQS#[4] SA_DQS#[5] SA_DQS#[6] SA_DQS#[7] C4 G6 J3 M6 AL6 AM8 AR12 AM15 DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7 SA_DQS[0] SA_DQS[1] SA_DQS[2] SA_DQS[3] SA_DQS[4] SA_DQS[5] SA_DQS[6] SA_DQS[7] D4 F6 K3 N6 AL5 AM9 AR11 AM14 DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7 SA_MA[0] SA_MA[1] SA_MA[2] SA_MA[3] SA_MA[4] SA_MA[5] SA_MA[6] SA_MA[7] SA_MA[8] SA_MA[9] SA_MA[10] SA_MA[11] SA_MA[12] SA_MA[13] SA_MA[14] SA_MA[15] AD10 W1 W2 W7 V3 V2 W3 W6 V1 W5 AD8 V4 W4 AF8 V5 V7 DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15 DDR_A_DQS#[0 7] DDR_A_DQS[0 7] DDR_A_MA[0 15] DDR_B_BS0 DDR_B_BS1 DDR_B_BS2 DDR_B_CAS# DDR_B_RAS# DDR_B_WE# TYCO_2013620-2_IVY BRIDGE CONN@ A R186 4.99K_0402_1% G C2065 0.1U_0402_16V4Z for ESD DIMM_DRAMRST#_R Q12 S TR SSM3K7002F 1N SC59-3 RST_GATE AA9 AA7 R6 SB_BS[0] SB_BS[1] SB_BS[2] AA10 AB8 AB9 SB_CAS# SB_RAS# SB_WE# SB_CLK[0] SB_CLK#[0] SB_CKE[0] AE2 AD2 R9 SB_CLK_DDR0 SB_CLK_DDR#0 DDRB_CKE0_DIMMB SB_CLK[1] SB_CLK#[1] SB_CKE[1] AE1 AD1 R10 SB_CLK_DDR1 SB_CLK_DDR#1 DDRB_CKE1_DIMMB RSVD_TP[11] RSVD_TP[12] RSVD_TP[13] AB2 AA2 T9 RSVD_TP[14] RSVD_TP[15] RSVD_TP[16] AA1 AB1 T10 SB_CS#[0] SB_CS#[1] RSVD_TP[17] RSVD_TP[18] AD3 AE3 AD6 AE6 DDRB_CS0_DIMMB# DDRB_CS1_DIMMB# SB_ODT[0] SB_ODT[1] RSVD_TP[19] RSVD_TP[20] AE4 AD4 AD5 AE5 SB_ODT0 SB_ODT1 SB_DQS#[0] SB_DQS#[1] SB_DQS#[2] SB_DQS#[3] SB_DQS#[4] SB_DQS#[5] SB_DQS#[6] SB_DQS#[7] D7 F3 K6 N3 AN5 AP9 AK12 AP15 DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7 SB_DQS[0] SB_DQS[1] SB_DQS[2] SB_DQS[3] SB_DQS[4] SB_DQS[5] SB_DQS[6] SB_DQS[7] C7 G3 J6 M3 AN6 AP8 AK11 AP14 DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7 SB_MA[0] SB_MA[1] SB_MA[2] SB_MA[3] SB_MA[4] SB_MA[5] SB_MA[6] SB_MA[7] SB_MA[8] SB_MA[9] SB_MA[10] SB_MA[11] SB_MA[12] SB_MA[13] SB_MA[14] SB_MA[15] AA8 T7 R7 T6 T2 T4 T3 R2 T5 R3 AB7 R1 T1 AB10 R5 R4 DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15 DDR_B_DQS[0 7] DDR_B_MA[0 15] C B TYCO_2013620-2_IVY BRIDGE CONN@ C293 0.047U_0402_16V7K R155 1K_0402_5% DIMM_DRAMRST# S0 RST_GATE hgih ,MOS ON SM_DRAMRST# HIGH,DIMM_DRAMRST# HIGH Dimm not reset S3 RST_GATE Low ,MOS OFF SM_DRAMRST# lo,DIMM_DRAMRST# HIGH Dimm not reset S4,5 RST_GATE Low ,MOS OFF SM_DRAMRST# lo,DIMM_DRAMRST# low Dimm reset A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2011/06/02 2012/06/02 Deciphered Date Title SCHEMATIC,MB A7912 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: DDR_B_DQS#[0 7] D R217 1K_0402_5% D R02 modify S SM_DRAMRST# SM_DRAMRST# SB_DQ[0] SB_DQ[1] SB_DQ[2] SB_DQ[3] SB_DQ[4] SB_DQ[5] SB_DQ[6] SB_DQ[7] SB_DQ[8] SB_DQ[9] SB_DQ[10] SB_DQ[11] SB_DQ[12] SB_DQ[13] SB_DQ[14] SB_DQ[15] SB_DQ[16] SB_DQ[17] SB_DQ[18] SB_DQ[19] SB_DQ[20] SB_DQ[21] SB_DQ[22] SB_DQ[23] SB_DQ[24] SB_DQ[25] SB_DQ[26] SB_DQ[27] SB_DQ[28] SB_DQ[29] SB_DQ[30] SB_DQ[31] SB_DQ[32] SB_DQ[33] SB_DQ[34] SB_DQ[35] SB_DQ[36] SB_DQ[37] SB_DQ[38] SB_DQ[39] SB_DQ[40] SB_DQ[41] SB_DQ[42] SB_DQ[43] SB_DQ[44] SB_DQ[45] SB_DQ[46] SB_DQ[47] SB_DQ[48] SB_DQ[49] SB_DQ[50] SB_DQ[51] SB_DQ[52] SB_DQ[53] SB_DQ[54] SB_DQ[55] SB_DQ[56] SB_DQ[57] SB_DQ[58] SB_DQ[59] SB_DQ[60] SB_DQ[61] SB_DQ[62] SB_DQ[63] @R184 @ R184 0_0402_5% reset DIMM C9 A7 D10 C8 A9 A8 D9 D8 G4 F4 F1 G1 G5 F5 F2 G2 J7 J8 K10 K9 J9 J10 K8 K7 M5 N4 N2 N1 M4 N5 M2 M1 AM5 AM6 AR3 AP3 AN3 AN2 AN1 AP2 AP5 AN9 AT5 AT6 AP6 AN8 AR6 AR5 AR9 AJ11 AT8 AT9 AH11 AR8 AJ12 AH12 AT11 AN14 AR14 AT14 AT12 AN15 AR15 AT15 +1.5V Follow CRB1.0 CPU DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63 DDR SYSTEM MEMORY B JCPU1C Rev B 4019ID Sheet Friday, January 06, 2012 of 60 CFG Straps for Processor CFG2 Ivy VSS_DIE_SENSE GND JCPU1E VAXG_VAL_SENSE VSSAXG_VAL_SENSE VCC_VAL_SENSE VSS_VAL_SENSE L7 AG7 AE7 AK2 RSVD32 W8 RSVD33 RSVD34 RSVD35 AT26 AM33 AJ27 RSVD37 RSVD38 RSVD39 RSVD40 T8 J16 H16 G16 PAD PAD 1: Normal Operation; Lane # socket pin map definition CFG2 T7 T74 CFG4 R813 @ 49.9_0402_1% R109 1K_0402_5% CFG4 B RSVD8 RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14 RSVD15 RSVD16 RSVD17 RSVD18 RSVD19 RSVD20 RSVD21 RSVD22 RSVD23 J20 B18 RSVD24 RSVD25 J15 RSVD27 C : Disabled; No Physical Display Port attached to Embedded Display Port * : Enabled; An external Display Port device is connected to the Embedded Display Port RSVD5 F25 F24 F23 D24 G25 G24 E23 D23 C30 A31 B30 B29 D30 B31 A30 C29 EDP@ RSVD_NCTF1 RSVD_NCTF2 RSVD_NCTF3 RSVD_NCTF4 RSVD_NCTF5 AR35 AT34 AT33 AP35 AR34 CFG6 CFG5 GM@ R107 1K_0402_5% RSVD_NCTF6 RSVD_NCTF7 RSVD_NCTF8 RSVD_NCTF9 RSVD_NCTF10 B34 A33 A34 B35 C35 @ AJ26 definition matches 0:Lane Reversed * RSVD28 RSVD29 RSVD30 RSVD31 @ @ Display Port Presence Strap VAXG_VAL_SENSE VSSAXG_VAL_SENSE VCC_VAL_SENSE VSS_VAL_SENSE R812 @ 49.9_0402_1% AJ31 AH31 AJ33 AH33 AH27 AH26 2 R811 @ 49.9_0402_1% R810 @ 49.9_0402_1% C RESERVED +CPU_CORE +VGFX_CORE VCC_DIE_SENSE VSS_DIE_SENSE CFG4 CFG5 CFG6 CFG7 CFG[0] CFG[1] CFG[2] CFG[3] CFG[4] CFG[5] CFG[6] CFG[7] CFG[8] CFG[9] CFG[10] CFG[11] CFG[12] CFG[13] CFG[14] CFG[15] CFG[16] CFG[17] CFG2 AK28 AK29 AL26 AL27 AK26 AL29 AL30 AM31 AM32 AM30 AM28 AM26 AN28 AN31 AN26 AM27 AK31 AN29 CFG0 R108 1K_0402_5% PAD @ D PEG Static Lane Reversal - CFG2 is for the 16x AH27 change to VCC_DIE_SENSE CFG T8 R112 1K_0402_5% Sandy AH26 D PCIE Port Bifurcation Straps RSVD51 RSVD52 AJ32 AK32 11: (Default) x16 - Device functions and disabled CFG[6:5] BCLK_ITP BCLK_ITP# RSVD_NCTF11 RSVD_NCTF12 RSVD_NCTF13 B disabled 01: Reserved - (Device function disabled ; function enabled) 00: x8,x4,x4 - Device functions and enabled AN35 AM35 RSVD54 and RSVD55 had changed to BCLK_ITP and BCLK_ITP# AT2 AT1 AR1 CFG7 B1 KEY *10: x8, x8 - Device function enabled ; function R102 1K_0402_5% @ TYCO_2013620-2_IVY BRIDGE CONN@ PEG DEFER TRAINING CFG7 1: (Default) PEG Train immediately following xxRESETB de assertion A A 0: PEG Wait for BIOS for training Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2011/06/02 2012/06/02 Deciphered Date Title SCHEMATIC,MB A7912 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: Rev B 4019ID Sheet Friday, January 06, 2012 of 60 JCPU1F QC 53A DC 53A PEG AND DDR AH13 AH10 AG10 AC10 Y10 U10 P10 L10 J14 J13 J12 J11 H14 H12 H11 G14 G13 G12 F14 F13 F12 F11 E14 E12 VCCIO25 VCCIO26 VCCIO27 VCCIO28 VCCIO29 VCCIO30 VCCIO31 VCCIO32 VCCIO33 VCCIO34 VCCIO35 VCCIO36 VCCIO37 VCCIO38 VCCIO39 E11 D14 D13 D12 D11 C14 C13 C12 C11 B14 B12 A14 A13 A12 A11 VCCIO40 J23 D C +1.05VS_VTT 1 +1.05VS_VTT VIDALERT# VIDSCLK VIDSOUT AJ29 AJ30 AJ28 H_CPU_SVIDALRT# H_CPU_SVIDCLK H_CPU_SVIDDAT R447 75_0402_5% R450 130_0402_1% R448 43_0402_1% R446 0_0402_5% R449 0_0402_5% VR_SVID_ALRT# VR_SVID_CLK VR_SVID_DAT B Place the PU resistors close to CPU +CPU_CORE R445 100_0402_1% A TYCO_2013620-2_IVY BRIDGE VCC_SENSE VSS_SENSE AJ35 VCCSENSE_R AJ34 VSSSENSE_R R444 R443 1 R910 VCCIO_SENSE VSS_SENSE_VCCIO CONN@ B10 A10 0_0402_5% 0_0402_5% VCCSENSE VSSSENSE R442 100_0402_1% VCCIO_SENSE VSSIO_SENSE VSSIO_SENSE VSSIO_SENSE change to VSS_SENSE_VCCIO 2 +1.05VS_VTT 10_0402_5% B VCCIO1 VCCIO2 VCCIO3 VCCIO4 VCCIO5 VCCIO6 VCCIO7 VCCIO8 VCCIO9 VCCIO10 VCCIO11 VCCIO12 VCCIO13 VCCIO14 VCCIO15 VCCIO16 VCCIO17 VCCIO18 VCCIO19 VCCIO20 VCCIO21 VCCIO22 VCCIO23 VCCIO24 C SVID D +1.05VS_VTT 8.5A VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 VCC20 VCC21 VCC22 VCC23 VCC24 VCC25 VCC26 VCC27 VCC28 VCC29 VCC30 VCC31 VCC32 VCC33 VCC34 VCC35 VCC36 VCC37 VCC38 VCC39 VCC40 VCC41 VCC42 VCC43 VCC44 VCC45 VCC46 VCC47 VCC48 VCC49 VCC50 VCC51 VCC52 VCC53 VCC54 VCC55 VCC56 VCC57 VCC58 VCC59 VCC60 VCC61 VCC62 VCC63 VCC64 VCC65 VCC66 VCC67 VCC68 VCC69 VCC70 VCC71 VCC72 VCC73 VCC74 VCC75 VCC76 VCC77 VCC78 VCC79 VCC80 VCC81 VCC82 VCC83 VCC84 VCC85 VCC86 VCC87 VCC88 VCC89 VCC90 VCC91 VCC92 VCC93 VCC94 VCC95 VCC96 VCC97 VCC98 VCC99 VCC100 SENSE LINES AG35 AG34 AG33 AG32 AG31 AG30 AG29 AG28 AG27 AG26 AF35 AF34 AF33 AF32 AF31 AF30 AF29 AF28 AF27 AF26 AD35 AD34 AD33 AD32 AD31 AD30 AD29 AD28 AD27 AD26 AC35 AC34 AC33 AC32 AC31 AC30 AC29 AC28 AC27 AC26 AA35 AA34 AA33 AA32 AA31 AA30 AA29 AA28 AA27 AA26 Y35 Y34 Y33 Y32 Y31 Y30 Y29 Y28 Y27 Y26 V35 V34 V33 V32 V31 V30 V29 V28 V27 V26 U35 U34 U33 U32 U31 U30 U29 U28 U27 U26 R35 R34 R33 R32 R31 R30 R29 R28 R27 R26 P35 P34 P33 P32 P31 P30 P29 P28 P27 P26 CORE SUPPLY +CPU_CORE POWER R163 10_0402_5% Should change to connect form power cirucit & layout differential with VCCIO_SENSE SV type CPU Compal Electronics, Inc Compal Secret Data Security Classification Issued Date A 2011/06/02 2012/06/02 Deciphered Date Title SCHEMATIC,MB A7912 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: Rev B 4019ID Sheet Friday, January 06, 2012 of 60 QC 46A DC 33A 1 +V_SM_VREF AL1 C688 0.1U_0402_16V4Z AF7 AF4 AF1 AC7 AC4 AC1 Y7 Y4 Y1 U7 U4 U1 P7 P4 P1 SA_DIMM_VREFDQ SB_DIMM_VREFDQ SA_DIMM_VREFDQ SB_DIMM_VREFDQ 2 2 SA RAIL A19 2 2 2 2 INTEL Recommend 1*330uF,3*10uF from CR PDDG 0.8 @ 0_0402_5% +VCCSA_SENSE + C221 @ 330U_D2_2V_Y VCCSA +VCCSA_SENSE H_VCCSA_VID0 H_VCCSA_VID1 C VID0 VID1 Vout Sandy 0 0.9V V Ivy V 0.8V V V 0.725V X V 1 0.675V X V B H_VCCSA_VID0 H_VCCSA_VID1 MISC VCCIO_SEL + R137 C829 10U_0603_6.3V6M VCCSA_VID[0] VCCSA_VID[1] C22 C24 +VCCSA C828 10U_0603_6.3V6M H23 +VCCSA M27 M26 L26 J26 J25 J24 H26 H25 VCCSA_SENSE INTEL Recommend 1*330uF,6*10uF from CR PDDG 0.8 +1.5VS 5A 6A VCCSA1 VCCSA2 VCCSA3 VCCSA4 VCCSA5 VCCSA6 VCCSA7 VCCSA8 R575 1K_0402_1% C355 330U_D2_2V_Y VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15 B4 D1 C361 10U_0603_6.3V6M DDR3 -1.5V RAILS SA_DIMM_VREFDQ SB_DIMM_VREFDQ C365 10U_0603_6.3V6M GRAPHICS VREF SM_VREF 2 SENSE LINES +V_SM_VREF should have 20 mil trace width C213 10U_0603_6.3V6M VCCIO_SEL R138 0_0402_5% @ TYCO_2013620-2_IVY BRIDGE CONN@ 2 R582 1K_0402_1% 10_0402_5% C341 10U_0603_6.3V6M +1.5VS R904 C219 10U_0603_6.3V6M VCCPLL1 VCCPLL2 VCCPLL3 VCC_AXG_SENSE VSS_AXG_SENSE C362 10U_0603_6.3V6M C653 1U_0402_6.3V6K C654 1U_0402_6.3V6K C655 10U_0603_6.3V6M @ C830 10U_0603_6.3V6M + B6 A6 A2 AK35 AK34 C605 10U_0603_6.3V6M +VCCPLL C831 10U_0603_6.3V6M 0_0805_5% C664 330U_D2_2V_Y R528 1.2A VAXG_SENSE VSSAXG_SENSE C364 10U_0603_6.3V6M +1.8VS VAXG1 VAXG2 VAXG3 VAXG4 VAXG5 VAXG6 VAXG7 VAXG8 VAXG9 VAXG10 VAXG11 VAXG12 VAXG13 VAXG14 VAXG15 VAXG16 VAXG17 VAXG18 VAXG19 VAXG20 VAXG21 VAXG22 VAXG23 VAXG24 VAXG25 VAXG26 VAXG27 VAXG28 VAXG29 VAXG30 VAXG31 VAXG32 VAXG33 VAXG34 VAXG35 VAXG36 VAXG37 VAXG38 VAXG39 VAXG40 VAXG41 VAXG42 VAXG43 VAXG44 VAXG45 VAXG46 VAXG47 VAXG48 VAXG49 VAXG50 VAXG51 VAXG52 VAXG53 VAXG54 C214 10U_0603_6.3V6M B INTEL Recommend 1*330uF,1*10uF and 2*1uF(0402) from CR PDDG 0.8 10_0402_5% C363 10U_0603_6.3V6M AT24 AT23 AT21 AT20 AT18 AT17 AR24 AR23 AR21 AR20 AR18 AR17 AP24 AP23 AP21 AP20 AP18 AP17 AN24 AN23 AN21 AN20 AN18 AN17 AM24 AM23 AM21 AM20 AM18 AM17 AL24 AL23 AL21 AL20 AL18 AL17 AK24 AK23 AK21 AK20 AK18 AK17 AJ24 AJ23 AJ21 AJ20 AJ18 AJ17 AH24 AH23 AH21 AH20 AH18 AH17 C D R903 JCPU1G POWER 1.8V RAIL +VGFX_CORE +VGFX_CORE D +3VALW * R909 10K_0402_5% 1/NC : (Default) +1.05VS_VTT A19 For 2012 CPU support 0: +1.0VS_VTT VCCIO_SEL RSVD26 had changed the name to VCCIO_SEL Need PH +3VALW 10K at +1.05VS_VTT source for 2012 processor +1.05V and +1.0V select R913 10K_0402_5% @ A A VCCIO_SEL Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2011/06/02 2012/06/02 Deciphered Date Title SCHEMATIC,MB A7912 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: Rev B 4019ID Sheet Friday, January 06, 2012 of 60 JCPU1H D AT35 AT32 AT29 AT27 AT25 AT22 AT19 AT16 AT13 AT10 AT7 AT4 AT3 AR25 AR22 AR19 AR16 AR13 AR10 AR7 AR4 AR2 AP34 AP31 AP28 AP25 AP22 AP19 AP16 AP13 AP10 AP7 AP4 AP1 AN30 AN27 AN25 AN22 AN19 AN16 AN13 AN10 AN7 AN4 AM29 AM25 AM22 AM19 AM16 AM13 AM10 AM7 AM4 AM3 AM2 AM1 AL34 AL31 AL28 AL25 AL22 AL19 AL16 AL13 AL10 AL7 AL4 AL2 AK33 AK30 AK27 AK25 AK22 AK19 AK16 AK13 AK10 AK7 AK4 AJ25 C B VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 JCPU1I VSS VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS98 VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160 D AJ22 AJ19 AJ16 AJ13 AJ10 AJ7 AJ4 AJ3 AJ2 AJ1 AH35 AH34 AH32 AH30 AH29 AH28 AH25 AH22 AH19 AH16 AH7 AH4 AG9 AG8 AG4 AF6 AF5 AF3 AF2 AE35 AE34 AE33 AE32 AE31 AE30 AE29 AE28 AE27 AE26 AE9 AD7 AC9 AC8 AC6 AC5 AC3 AC2 AB35 AB34 AB33 AB32 AB31 AB30 AB29 AB28 AB27 AB26 Y9 Y8 Y6 Y5 Y3 Y2 W35 W34 W33 W32 W31 W30 W29 W28 W27 W26 U9 U8 U6 U5 U3 U2 T35 T34 T33 T32 T31 T30 T29 T28 T27 T26 P9 P8 P6 P5 P3 P2 N35 N34 N33 N32 N31 N30 N29 N28 N27 N26 M34 L33 L30 L27 L9 L8 L6 L5 L4 L3 L2 L1 K35 K32 K29 K26 J34 J31 H33 H30 H27 H24 H21 H18 H15 H13 H10 H9 H8 H7 H6 H5 H4 H3 H2 H1 G35 G32 G29 G26 G23 G20 G17 G11 F34 F31 F29 TYCO_2013620-2_IVY BRIDGE CONN@ VSS161 VSS162 VSS163 VSS164 VSS165 VSS166 VSS167 VSS168 VSS169 VSS170 VSS171 VSS172 VSS173 VSS174 VSS175 VSS176 VSS177 VSS178 VSS179 VSS180 VSS181 VSS182 VSS183 VSS184 VSS185 VSS186 VSS187 VSS188 VSS189 VSS190 VSS191 VSS192 VSS193 VSS194 VSS195 VSS196 VSS197 VSS198 VSS199 VSS200 VSS201 VSS202 VSS203 VSS204 VSS205 VSS206 VSS207 VSS208 VSS209 VSS210 VSS211 VSS212 VSS213 VSS214 VSS215 VSS216 VSS217 VSS218 VSS219 VSS220 VSS221 VSS222 VSS223 VSS224 VSS225 VSS226 VSS227 VSS228 VSS229 VSS230 VSS231 VSS232 VSS233 VSS234 VSS235 VSS236 VSS237 VSS238 VSS239 VSS240 VSS241 VSS242 VSS243 VSS244 VSS245 VSS246 VSS247 VSS248 VSS249 VSS250 VSS251 VSS252 VSS253 VSS254 VSS255 VSS256 VSS257 VSS258 VSS259 VSS260 VSS261 VSS262 VSS263 VSS264 VSS265 VSS266 VSS267 VSS268 VSS269 VSS270 VSS271 VSS272 VSS273 VSS274 VSS275 VSS276 VSS277 VSS278 VSS279 VSS280 VSS281 VSS282 VSS283 VSS284 VSS285 VSS F22 F19 E30 E27 E24 E21 E18 E15 E13 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 D35 D32 D29 D26 D20 D17 C34 C31 C28 C27 C25 C23 C10 C1 B22 B19 B17 B15 B13 B11 B9 B8 B7 B5 B3 B2 A35 A32 A29 A26 A23 A20 A3 C B TYCO_2013620-2_IVY BRIDGE CONN@ A A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2011/06/02 2012/06/02 Deciphered Date Title SCHEMATIC,MB A7912 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: Rev B 4019ID Sheet Friday, January 06, 2012 10 of 60 A B C D +3VLP VMB @ PR14 10K_0402_1% 1 VCC TMSNS1 GND RHYST1 OT1 TMSNS2 OT2 RHYST2 2 EC_SMB_CK1 MAINPWON @ PR18 47K_0402_1% @PH2 @ PH2 100K_0402_1%_NCP15WF104F03RC G718TM1U_SOT23-8 VS +3VALWP TH @ PU2B LM393DR_SO8 O P 8 P - + - 1 @ PR24 1.5M_0402_5% @ PC11 100P_0402_50V8J @ PR25 100K_0402_1% 2 @ PD5 LL4148_LL34-2 + O S @ PU2A LM393DR_SO8 1 G G @ PC10 0.022U_0402_16V7K D PQ5A DMN66D0LDW-7_SOT363-6 @ PR23 10K_0402_1% @ PR22 47K_0402_1% H_PROCHOT# VS 1 VL G MAINPWON EC_SMB_DA1 @PU1 @ PU1 @ PR16 100K_0402_1% BATT_TEMP @ PR13 10K_0402_1% 1 PR102 0_0402_5% @ PC7 0.1U_0603_25V7K 1 PC9 0.01U_0402_25V7K 2 PR19 1K_0402_5% 1 PR21 1K_0402_1% +3VALWP PC8 1000P_0402_50V7K PR17 100_0402_1% PR15 100_0402_1% PR20 6.49K_0402_1% BATT+ PL2 SMB3025500YA_2P 2 CONN@ PJP2 SUYIN_200275GR008G13GZR BATT_S1 1 2 PI 3 TH 4 EC_SMCA 5 EC_SMDA 6 7 8 GND GND 10 +3VLP PH1 under CPU botten side : CPU thermal protection at 92 degree C Recovery at 56 degree C 65W@ PR33 3.92K_0402_1% PR29 21K_0402_1% PC14 0.1U_0603_25V7K 3 MAINPWON D PQ5B DMN66D0LDW-7_SOT363-6 G PU3 VCC TMSNS1 GND RHYST1 ~OT1 TMSNS2 ~OT2 RHYST2 PR35 9.53K_0402_1% 1 EC pin For 90W adapter==>action 97W , Recovery 75W Issued Date 9012@ PC17 1000P_0402_50V7K PH1 100K_0402_1%_NCP15WF104F03RC S For 65W adapter==>action 70W , Recovery 54W Deciphered Date 9012@ PR57 9012@PR57 0_0402_5% 65W@ PR36 10.5K_0402_1% 2012/06/02 Title SCHEMATIC,MB A7912 Date: B C VCIN1_PROCHOT PR38 10K_0402_1% THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A VCIN0_PH Compal Electronics, Inc Compal Secret Data 2011/06/02 90W@ PR36 16.2K_0402_1% G718TM1U_SOT23-8 Security Classification 90W@ PR33 8.87K_0402_1% 9012@PR37 9012@ PR37 0_0402_5% 1 2N7002KW_SOT323-3 S @ PR32 100K_0402_1% H_PROCHOT# PC15 1U_0402_6.3V6K PR31 100K_0402_1% D PQ7 G PR34 1K_0402_5% SPOK 1 PR28 100K_0402_1% 1 ADP_I 1 PC13 0.1U_0603_25V7K VL @ +VSBP PR27 22K_0402_1% 2 3 2 PR26 100K_0402_1% 1 B+ PC12 0.22U_0603_25V7K PQ6 TP0610K-T1-E3_SOT23-3 Rev B 4019ID Friday, January 06, 2012 D Sheet 46 of 60 A B C D D for reverse input protection S PQ8 SI1304BDL-T1-E3_SC70-3 G 2 PR40 3M_0402_5% PR43 0_0402_5% PC27 0.01U_0402_50V7K 1 SRN 12 SRN BATDRV 11 CSON1 PR55 6.8_0603_5% BQ24725_BATDRV PC36 0.01U_0402_50V7K PC39 2200P_0402_50V7K PC35 10U_0805_25V6K 1 2 PC34 10U_0805_25V6K CSON1 PC38 0.1U_0402_25V6 2 PC37 0.1U_0402_25V6 CSOP1 PR53 4.7_1206_5% PR54 10_0603_5% CSOP1 SRP ILIM IOUT SRP 13 @ 14 GND DL_CHG PC41 0.1U_0603_25V7K 15 PC40 680P_0402_50V7K 17 18 16 LODRV PL4 PR52 10UH_FDVE1040-H-100M=P3_6.5A_20% 0.01_1206_1% BQ24725_LX CHG @ +3VALW 1 PR58 316K_0402_1% PC42 0.01U_0402_25V7K 1 Vin Dectector PR63 154K_0603_0.1% L >H H >L 2 PR62 2M_0402_1% 2 PR60 280K_0603_0.1% PD9 RB751V-40_SOD323-2 VIN PR59 2M_0402_1% PR61 100K_0402_1% ACDET BATT+ 10 Pre_CHG ACIN SCL ACOK PR56 100K_0402_1% SDA ACDRV ACDET CMSRC BQ24725_ACDRV +3VLP PQ12 SIS412DN-T1-GE3_POWERPAK8-5 PC33 BQ24725ARGRR_VQFN20_3P5X3P5 BQ24725_CMSRC PC24 2200P_0402_50V7K PR48 2.2_0603_5% PR50 2.2_0402_5% DH_CHG 2DH_CHG-1 REGN ACP PD7 RB751V-40_SOD323-2 BTST HIDRV ACN 19 VCC PAD PHASE 20 2 21 @ PR44 4.12K_0603_1% 1U_0603_25V6K PU4 PC86 0.1U_0402_25V6 BQ24725_BATDRV PQ13 SIS412DN-T1-GE3_POWERPAK8-5 @ PR51 3.3_1210_5% BQ24725_BST 1U_0603_25V6K DH_CHG PC31 @ PC32 2.2U_0805_25V6K PC87 0.1U_0402_25V6 PC29 0.047U_0402_25V7K PR47 10_1206_1% BQ24725_ACP 2 BQ24725_ACN @ PR49 3.3_1210_5% PC30 0.1U_0603_25V7K @ PD6 BAS40CW_SOT323-3 BQ24725_LX PR46 4.12K_0603_1% PR45 4.12K_0603_1% 1 VIN 2 PC26 0.1U_0402_25V6 3 PC23 0.1U_0402_25V6 2 PQ11 AO4466L_SO8 PC22 10U_0805_25V6K 1 VIN CHG_B+ PL3 1.2UH_PNS40201R2YAF_3A_30% 2 @ PC16 0.1U_0402_25V6 PR42 0_0402_5% PC25 2200P_0402_50V7K B+ PR41 0.02_2512_1% PC21 10U_0805_25V6K P2 PQ10 AO4466L_SO8 P1 PQ9 AO4466L_SO8 VIN PR39 1M_0402_5% PC28 0.1U_0402_25V6 1 ILIM and external DPM EC_SMB_DA1 Min 3.906A S Close EC @ PC45 0.1U_0402_16V7K Compal Electronics, Inc Compal Secret Data Security Classification Issued Date Typ Max 4.006A 4.108A ADP_I 1 PC44 100P_0402_50V8J Max 18.275V 17.898V 2 PR66 0_0402_5% Typ 18.063V 17.687V EC_SMB_CK1 PR65 66.5K_0603_0.1% PC43 0.1U_0402_16V7K D 2 PQ15 2N7002KW_SOT323-3 G PQ14 PDTC115EUA_SC70-3 7,40,44,49,50> SUSP# PR64 100K_0402_1% FSTCHG ACDET Min 17.852V 17.476V 2011/06/02 Deciphered Date 2012/06/02 Title SCHEMATIC,MB A7912 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C Rev B 4019ID Sheet Friday, January 06, 2012 D 47 of 60 Note: Use TPS51125 IC can remove RTC refernece LDO Use TPS51427 IC must keep RTC refernece LDO PC46 1U_0603_10V6K 2VREF_8205 D G VS VL VS D G LG_5V PC65 4.7U_0805_10V6K PR78 150K_0402_1% RT8205_B+ Typ: 175mA PR76 4.7_1206_5% 2 PQ19 SI7716ADN-T1-GE3_POWERPAK8-5 @ +5VALWP PC62 330U_6.3V_M PC63 680P_0402_50V7K NC 18 VIN GND VREG5 17 13 RT8205LZQW(2) WQFN 24P PWM VL S 1 PC57 0.1U_0603_25V7K 19 PL7 4.7UH_FDSD0630-H-4R7M-P3_5.5A_20% + @ RT8205 TONSEL=VREF (1)SMPS1=300KHZ (+5VALWP) (2)SMPS2=375KHZ(+3VALWP) B TPS51125A TONSEL=VREF (1)SMPS1=245KHZ (+5VALWP) (2)SMPS2=305KHZ(+3VALWP) 3.3VALWP Delta I = 1.5836A (Freq=305KHz) Iocp = 7.4965A ~ 10.349A 5VALWP Delta I = 2.6342A (Freq=245KHz) Iocp = 7.4965A ~ 10.349A +3.3VALWP Ipeak=7A ; Imax=4.9A Delta I=1.5836A=>1/2Delta I=0.7918A (F=375K Hz) Rds(on)=18m ohm(max) ; Rds(on)=15m ohm(typical) Ilimit_min=(174K*10uA)/(10*18m*1.2)=7.4965A Ilimit_max=(174K*10uA)/(10*15m*1.2)=10.349A Iocp=Ilimit+1/2Delta I=7.4965A~10.349A +5VALWP Ipeak=7A ; Imax=4.9A Delta I=2.6342A=>1/2Delta I=1.3171A (F=300K Hz) Rds(on)=18m ohm(max) ; Rds(on)=15m ohm(typical) Ilimit_min=(174K*10uA)/(10*18m*1.2)=7.4965A Ilimit_max=(174K*10uA)/(10*15m*1.2)=10.349A Iocp=Ilimit+1/2Delta I=7.4965A ~ 10.349A A D 930@ PQ23B DMN66D0LDW-7_SOT363-6 G 930@ PQ22 S 930@ PQ23A PDTC115EUA_SC70-3DMN66D0LDW-7_SOT363-6 PC67 1U_0603_10V6K 930@ PR84 1M_0402_1% A 930@ PR83 316K_0402_1% PC53 2200P_0402_50V7K ENTRIP1 LGATE1 PQ20B DMN66D0LDW-7_SOT363-6 PQ21 PDTC115EUA_SC70-3 2 ACIN VIN 930@ PR81 1M_0402_1% 930@ PR85 10K_0402_1% 930@ PR82 402K_0402_1% 930@ PD11 LL4148_LL34-2 2 LGATE2 C SPOK PR79 100K_0402_1% PR80 0_0402_5% MAINPWON PQ17 SIS412DN-T1-GE3_POWERPAK8-5 EC_ON 9012@ PR100 9012@PR100 2.2K_0402_5% LX_5V 2VREF_8205 D G VL FB1 UG_5V 20 PC66 0.1U_0603_25V7K ENTRIP2 S ENTRIP1 21 PHASE1 PR77 499K_0402_1% GLZ5.1B_LL34-2 D REF UGATE1 PHASE2 VFB=2.0V B PQ20A DMN66D0LDW-7_SOT363-6 UGATE2 EN B+ ENTRIP1 PR74 PC59 2.2_0603_5% 0.1U_0603_25V7K BST_5V 2 PC64 1U_0603_10V6K PD10 @ TONSEL 22 ENTRIP2 23 BOOT1 16 12 PGOOD BOOT2 15 LG_3V VREG3 SKIPSEL PR75 4.7_1206_5% 1 PC54 4.7U_0805_10V6K PR73 BST_3V 2.2_0603_5% UG_3V 10 PC58 0.1U_0603_25V7K LX_3V 11 24 PQ18 SI7716ADN-T1-GE3_POWERPAK8-5 PC61 680P_0402_50V7K + PR72 174K_0402_1% VO1 VO2 @ PC60 220U_6.3V_M P PAD RT8205_B+ PL6 4.7UH_FDSD0630-H-4R7M-P3_5.5A_20% +3VALWP PU5 25 14 PR71 174K_0402_1% 2 PQ16 C SIS412DN-T1-GE3_POWERPAK8-5 PC52 2200P_0402_50V7K +3VLP PC51 4.7U_0805_25V6-K PC50 4.7U_0805_25V6-K PC49 0.1U_0603_25V7K PC48 560P_0402_50V7K PC47 560P_0402_50V7K B+ PR70 20K_0402_1% FB2 Typ: 175mA ENTRIP2 PR69 20K_0402_1% RT8205_B+ PL5 SUPPRE_ FBMA-L11-453215-800LMA90T_1812 PR68 30K_0402_1% PC56 4.7U_0805_25V6-K PR67 13.7K_0402_1% PC55 4.7U_0805_25V6-K D Compal Electronics, Inc Compal Secret Data Security Classification 2011/06/02 Issued Date S Deciphered Date 2012/06/02 Title SCHEMATIC,MB A7912 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: Friday, January 06, 2012 Rev B 4019ID Sheet 48 of 60 B D +VTT_REFP VTTSNS GND VTTREF RT8207MZQW_WQFN20_3X3 PGND 14 CS 13 VDDP 12 VDD 11 LG_1.5V PR88 9.1K_0402_1% 1 2 PL9 0.36UH_PDME104T-R36MS0R825_37A_20% +1.5VP DCR: 0.82mΩ±5% @ PR87 @PR87 4.7_1206_5% + PC74 330U_6.3V_M LX_1.5V UG_1.5V 16 17 PHASE BOOT UGATE 19 18 LGATE 15 B+ PC70 560P_0402_50V7K Rds=2.7mΩ(Typ) 3.3mΩ(Max) @ PC75 @PC75 680P_0402_50V7K VTTGND PR86 PC71 2.2_0603_5% 0.1U_0603_25V7K BST_1.5V-1 2 PAD VLDOIN 20 PU6 21 VTT Output Cap PAD PC73 10U_0805_25V6K 2 +0.75VSP PC72 10U_0805_25V6K BST_1.5V PJ13 JUMP_43X79 PQ24 MDU1516URH_POWERDFN56-8-5 1 PL8 SUPPRE_ FBMA-L11-453215-800LMA90T_1812 PQ25 MDU1511RH_POWERDFN56-8-5 +1.5VP 1.5V_B+ PC69 4.7U_0805_25V6-K C B PC68 4.7U_0805_25V6-K A S +5VALW 2 PR90 10K_0402_5% PC77 1U_0603_10V6K PGOOD 10 PR89 5.1_0603_5% PC78 1U_0603_10V6K @ PGOOD_1.5V @ PR94 5.9K_0402_1% 2 PQ27 2N7002KW_SOT323-3 @ PC79 0.1U_0402_16V7K PC325 0.1U_0402_16V7K +3VALW PR93 887K_0402_1% 1.5V_B+ D G SUSP SYSON TON S5 PR92 0_0402_5% S5_1.5V SUSP# S3_1.5V PR91 267K_0402_1% S3 VDDQ FB PC76 0.033U_0402_16V7K +1.5VP 2 FB=0.75V To GND = 1.5V To VDD = 1.8V PR95 5.76K_0402_1% STATE S3 S5 1.5VP VTT_REFP FB=0.6V 0.75VSP Note:Iload(max)=3.5A 3 @ PC83 22U_0805_6.3VAM PC82 22U_0805_6.3VAM FB_1.8V PC81 68P_0402_50V8J 1 PR97 20K_0402_1% 2 PR96 4.7_1206_5% +1.8VSP PR99 10K_0402_1% 2 FB 1 PR98 1M_0402_5% EN PG PR257 100K_0402_1% +1.8VSP_ON Note: S3 - sleep ; S5 - power off SVIN SUSP# LX PL10 1UH_NRS4018T1R0NDGJ_3.2A_30% PC85 680P_0402_50V7K Off Off Off (Discharge) (Discharge) (Discharge) LX LX_1.8V NC Lo PVIN Lo PC90 47P_0402_50V8J S4/S5 PC80 22U_0805_6.3VAM NC On TP On Hi 11 Lo +3VALW S3 On Off (Hi-Z) On PC84 0.1U_0402_16V7K On Hi Hi PU7 SY8033BDBC_DFN10_3X3 10 PVIN S0 @ PJ14 @PJ14 JUMP_43X79 1 2 Notice: Internal resistance about 500K on 2nd EN pin 4 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2011/06/02 Deciphered Date 2012/06/02 Title SCHEMATIC,MB A7912 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C Rev B 4019ID Friday, January 06, 2012 D Sheet 49 of 60 SW_+1.05VS_VTTP VFB V5IN +1.05VS_VTTP_5V TST DRVL LG_+1.05VS_VTTP FB_+1.05VS_VTTP +5VALW PQ30 MDU1511RH_POWERDFN56-8-5 PC98 4.7U_0805_25V6-K 2 Rds=2.7mΩ(Typ) 3.3mΩ(Max) + @ PR115 4.7_1206_5% TPS51212DSCR_SON10_3X3 PC101 1U_0603_10V6K @ PC104 680P_0402_50V7K PC103 0.1U_0402_16V7K PC102 330U_6.3V_M PR276 0_0402_5% VSSIO_SENSE PR114 470K_0402_1% 11 TP +1.05VS_VCCPP 1 PL14 1UH_MMD-10DZ-1R0M-X1A_18A_20% UG_+1.05VS_VTTP EN PC99 0.1U_0603_25V7K 2 SW TRIP EN_+1.05VS_VTTP PR111 2.2_0603_5% D DRVH TRIP_+1.05VS_VTTP2 RF_+1.05VS_VTTP PC100 0.1U_0402_16V7K BST_+1.05VS_VTTP VBST PR113 330K_0402_1% SUSP# 10 PGOOD B+ PU9 PC97 4.7U_0805_25V6-K 2 PC96 2200P_0402_50V7K 2 @ PR274 0_0402_5% PR112 38.3K_0402_1% PL13 FBMA-L11-322513-151LMA50T_1210 +1.05VS_VTTP_B+ PC95 0.1U_0402_25V6 VCCPPWRGOOD Cesr= 15m ohm Ipeak= 15.37A Imax= 10.759A Delta I= 3.4368A ==>1/2 Delta I= 1.7184A Vtrip=Rtrip*10uA= 0.255V Iocp= 19.108A~29.416A PQ29 MDV1525URH_PDFN33-8-5 PR261 10K_0402_1% D VFB= 0.704V Vo=VFB*(1+PR116/PR119)= 1.05V Freq= 266~314KHz , 290KHz(typ) +3VS PR101 0_0402_5% 2 5 C C PR116 4.99K_0402_1% VFB=0.7V PC105 1000P_0402_50V7K PR117 1.2K_0402_1% PR118 100_0402_1% VCCIO_SENSE PR119 10K_0402_1% B B A A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2011/06/02 2012/06/02 Deciphered Date Title SCHEMATIC,MB A7912 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: Rev B 4019ID Sheet Friday, January 06, 2012 50 of 60 GPU@ PC328 1U_0402_6.3V6K +3VS PR120 100K_0402_5% 1 13 SW 11 SW 10 SW SW SW TP 25 PR125 PC108 0_0603_5% 0.22U_0603_16V7K 2+VCCSA_BT_1 PL15 0.47UH_FDVE0630-H-R47M=P3_17.7A_20% +VCCSA_PHASE 23 VIN 24 VIN MODE VOUT COMP VREF GND PAD-OPEN 43X118 @ @ PC109 680P_0402_50V7K @ GNDA_VCCSA @ @ PR127 33K_0402_5% @ C +VCCSA_PWR_SRC @PR126 @PR126 4.7_1206_5% TPS51461RGER_QFN24_4X4 +VCCSAP PC121 10U_0805_25V6K +VCCSA_PWR_SRC VIN SLEW PGND 22 21 +3VALW PC120 10U_0805_25V6K PJ15 PC119 0.1U_0603_25V7K PC118 2200P_0402_50V7K 12 PC117 22U_0805_6.3V6M EN C BST PC116 22U_0805_6.3V6M PGND PC115 2200P_0402_50V7K 20 VCCPPWRGOOD PC114 22U_0805_6.3V6M PGND +VCC_SAP TDC 4.2A Peak Current 6A OCP current 7.2A PC113 22U_0805_6.3V6M 19 PR124 0_0402_5% +VCCSA_EN VID0 V5DRV PU10 PGOOD Ien=10uA, Vth=0.3V, notice the res and pull high voltage from HW V5FILT PC107 2.2U_0603_10V7K +VCCSA_VID0 +VCCSA_VID1 17 15 18 PR123 10_0402_1% PC106 1U_0603_10V6K +5VALW 16 S G GPU@ PQ50 2N7002KW_SOT323-3 +VCCSA_PWRGD VGA_ON# SA_PGOOD D GPU@ PR264 0_0402_1% @ PR266 0_0402_1% VGA_PWROK# H_VCCSA_VID0 PR122 1K_0402_5% PC112 1U_0402_16V7K 2 1 @ PR270 22K_0402_5% D H_VCCSA_VID1 PC111 22U_0805_6.3V6M GPU@ PR260 6.04K_0402_1% VCCSA Vout 0.9V 0.8V 0.725V 0.675V output voltage adjustable network PC110 22U_0805_6.3V6M 2 GPU@ PC330 22U_0805_6.3V6M 14 GPU@ PR277 47_0603_5% PR121 1K_0402_5% VID[1] 1 FB=0.8V GPU@ PC327 1U_0402_6.3V6K GPU@ PC326 0.022U_0402_25V7K 2 @ PR258 18K_0402_1% VGA_ON +1.05VS_DGPUP GPU@ PR259 1.91K_0402_1% FB +VCCSA_PWRGD GPU@ PR263 18K_0402_1% VGA_PWROK VOUT VOUT EN POK GPU@ PC329 4.7U_0603_6.3V6K D VCNTL VIN VIN GND GPU@ PU16 APL5930KAI-TRG_SO8 VID1 +1.5VSDGPU VID [0] 0 1 The 1k PD on the VCCSA VIDs are empty These should be stuffed to ensure that VCCSA VID is 00 prior to VCCIO stability +3VALW PR128 100_0402_5% PC122 0.22U_0402_10V6K PC123 3300P_0402_50V7K B 1.5VSDGPU_EN GPU@ PC324 0.1U_0402_16V7K GPU@ PC316 10U_0805_25V6K VBST 10 BST_1.5VSDGPU TRIP DRVH DH_1.5VSDGPU EN SW LX_1.5VSDGPU GPU@ PR251 2.2_0603_5% GPU@ PC317 0.1U_0603_25V7K PGOOD GPU@ PL27 1.2UH_1164AY-1R2N=P3_9.8A_30% +5VALW VFB V5IN TST DRVL DL_1.5VSDGPU GPU@ PQ45 SI7716ADN-T1-GE3_POWERPAK8-5 @ PC319 680P_0402_50V7K + GPU@ PC320 330U_6.3V_M Cesr= 15m ohm Ipeak= 10.40A Imax= 7.28A Delta I= 4.002A ==>1/2 Delta I= 2.001A Vtrip=Rtrip*10uA= 1.13V Iocp= 12.464A~14.167A A Rds=13.5mΩ(Typ) 16.5mΩ(Max) GPU@ PR248 2K_0402_1% A VFB=0.7V VFB= 0.704V Vo=VFB*(1+PR248/PR255)= 1.5V Freq= 266~314KHz , 290KHz(typ) 2 GPU@ PC323 4.7U_0805_10V6K +1.5VSDGPUP @ PR247 4.7_1206_5% 11 TPS51212DSCR_SON10_3X3 GPU@ PR250 470K_0402_1% TP 2 @ PR256 10K_0402_5% B GNDA_VCCSA @ PR246 47K_0402_1% +VCCSA_SENSE PAD-OPEN1x1m VGA_ON 1 GPU@ PU15 GPU@ PR253 137K_0402_1% 1 GPU@ PQ46 SIS412DN-T1-GE3_POWERPAK8-5 GPU@ PR265 0_0402_5% VGA_PWROK 1.5VSDGPU_B+ GPU@ PC318 10U_0805_25V6K GPU@ PC322 560P_0402_50V7K B+ GPU@ PC321 560P_0402_50V7K GPU@ PL26 SUPPRE_ FBMA-L11-453215-800LMA90T_1812 PR130 0_0402_5% PJ16 PR129 10K_0402_5% PC124 0.01U_0402_25V7K 2 2011/06/02 Deciphered Date 2012/06/02 Title Issued Date Compal Electronics, Inc Compal Secret Data Security Classification GPU@ PR255 1.74K_0402_1% THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D C DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: SCHEMATIC,MB A7912 Document Number Rev B 4019ID Sheet Friday, January 06, 2012 51 of 60 PHASE3 GND TP LGATE3 BOOT1 PR156 4.7_1206_5% QC@ PR157 10K_0603_1% ISEN3 @ +5VS PR162 1_0603_5% VSUM- PQ35 MDV1525URH_PDFN33-8-5 @ PC186 0.01UF_0402_25V7K PR204 1_0402_5% ISEN2G @PR205 @ PR205 10K_0402_1% PC172 680P_0402_50V7K 2 +VGFX_CORE DCR: 0.82mΩ±5% ISEN21 PR181 10K_0603_1% VSUM+ PR188 1_0402_5% 2011/06/02 PC179 10U_0805_25V6K PC177 10U_0805_25V6K PC178 10U_0805_25V6K +CPU_CORE DCR: 0.82mΩ±5% @ ISEN11 PR196 10K_0603_1% @ PR197 10K_0402_1% ISEN2 VSUM+ @ PR262 10K_0402_1% ISEN3 @ PR198 3.65K_0603_1% VSUM2 A PR201 1_0402_5% Compal Electronics, Inc 2012/06/02 Deciphered Date Title SCHEMATIC,MB A7912 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC B ISEN3 @PR254 @ PR254 10K_0402_1% 2 Date: 1ISEN1 @PR182 @ PR182 10K_0402_1% PL21 0.36UH_PDME104T-R36MS0R825_37A_20% Compal Secret Data Security Classification Issued Date PQ37 MDV1525URH_PDFN33-8-5 PC176 10U_0805_25V6K PC175 PC187 0.22U_0603_16V7K VSUMG- @ PR179 4.7_1206_5% PQ36 MDU1511RH_POWERDFN56-8-5 1 PR180 12 2.61K_0402_1% 11K_0402_1% PC166 0.22U_0603_16V7K PR184 QC@ PC168 0.22U_0603_16V7K 1 2 PH6 10KB_0402_5%_ERTJ0ER103J PR194 2.2_0603_5% BOOT1 1 DCR: 0.82mΩ±5% QC@ PR202 10K_0603_1% VSUMG+ PR203 3.65K_0603_1% @ PR200 4.7_1206_5% PC190 680P_0402_50V7K 2 PQ40 MDU1511RH_POWERDFN56-8-5 BOOT1G LGATE1G PR206 2.2_0603_5% UGATE1-1 LGATE1 2 1 PR192 0_0402_5% PHASE1 For DC 35W 2+1 CPU_CORE LL= -1.9mΩ, OCP ~70A GFX_CORE LL= -3.9mΩ, OCP ~40A CPU_B+ For 45W 3+2 CPU_CORE LL= -1.9mΩ, OCP ~116A GFX_CORE LL= -3.9mΩ, OCP ~55A @ +CPU_CORE PR185 3.65K_0603_1% VSUM2 PC188 680P_0402_50V7K 2 PR195 4.7_1206_5% PL22 0.36UH_PDME104T-R36MS0R825_37A_20% PC189 0.22U_0603_16V7K VSUM- PQ39 MDU1511RH_POWERDFN56-8-5 VSSSENSE PHASE1G A DC@ PC168 0.1U_0603_25V7K PC157 @ @ VCCSENSE @ PR193 10_0402_1% PQ38 MDV1525URH_PDFN33-8-5 LGATE2 + @ @ PC180 330P_0402_50V7K 2 PC164 0.22U_0603_16V7K UGATE1 @ PR191 10_0402_1% ISEN1G CPU_B+ UGATE1G DC@ PC170 33P_0402_50V8J PC185 330P_0402_50V7K +CPU_CORE PR178 2.2_0603_5% BOOT2 1 PL20 0.36UH_PDME104T-R36MS0R825_37A_20% Close Phase choke DC@ PR187 390_0402_1% PC184 10U_0805_25V6K PC183 10U_0805_25V6K PC182 10U_0805_25V6K PC181 10U_0805_25V6K DC@ PR189 2.15K_0402_1% PC174 150P_0402_50V8J 2 PR190 267K_0402_1% C 1ISEN2 @PR163 @ PR163 10K_0402_1% 220U_25V_M UGATE2-1 PC161 10U_0805_25V6K UGATE2 PR175 0_0402_5% 1U_0402_16V7K QC@ PR189 3.65K_0402_1% 1 PC165 0.22U_0402_6.3V6K PC171 0.22U_0402_6.3V6K QC@ PC173 0.22U_0402_6.3V6K DC@ PR177 20.5K_0402_1% DCR: 0.82mΩ±5% 1ISEN1 @PR154 @ PR154 10K_0402_1% QC@ PR167 1_0402_5% @ PC160 10U_0805_25V6K +3VS @ PC169 0.068U_0402_16V7K QC@ PC170 47P_0402_50V8J 1 B QC@ PR187 475_0402_1% PC167 470P_0402_50V7K 2 PR183 499_0402_1% DC@ PC163 10P_0402_50V8J QC@ PR166 3.65K_0603_1% VSUM+ PC159 10U_0805_25V6K VGATE ISEN3 ISEN2 ISEN1 QC@ PR177 5.76K_0402_1% 2 CPU_B+ VSUM+ PR176 2K_0402_1% @ QC@ PL19 0.36UH_PDME104T-R36MS0R825_37A_20% PHASE2 PC162 560P_0402_50V7K PC131 10U_0805_25V6K @ +CPU_CORE ISL95836HRTZ-T_TQFN40_5X5~D 1.91K_0402_1% @ PC153 680P_0402_50V7K UGATE1 @ DC@ PR159 0_0603_5% PC154 1U_0603_10V6K LGATE1 LGATE BOOT3 PWM PHASE 2 ISL6208BCRZ-T_QFN8_2X2 LGATE2 PHASE1 UGATE FCCM BOOT VCC CPU_B+ QC@ PR146 1_0402_5% VSUMG- PR148 VSUMG+ 10K_0402_1% ISEN1G ISEN2G PL18 SUPPRE_ FBMA-L11-453215-800LMA90T_1812 B+ @ QC@ PQ34 MDU1511RH_POWERDFN56-8-5 PHASE2 QC@ PU12 30 29 28 27 26 25 24 23 22 21 QC@ PR150 2.2_0603_5% @ @ LGATE D PC150 680P_0402_50V7K GND TP DCR: 0.82mΩ±5% PC149 680P_0402_50V7K QC@ PC147 PC142 PR140 10U_0805_25V6K 680P_0402_50V7K 4.7_1206_5% 2 PC148 10U_0805_25V6K QC@ PR144 10K_0603_1% QC@ PR145 3.65K_0603_1% PWM PHASE +VGFX_CORE QC@ PC146 10U_0805_25V6K BOOT2G 2 QC@ PR138 2.2_0603_5% QC@ PC136 0.22U_0603_16V7K LGATE2G QC@ PQ33 QC@ PQ32 MDV1525URH_PDFN33-8-5 MDU1511RH_POWERDFN56-8-5 PC145 10U_0805_25V6K 2 UGATE2 QC@ PC130 10U_0805_25V6K PC129 10U_0805_25V6K QC@ PL17 0.36UH_PDME104T-R36MS0R825_37A_20% FCCM BOOT QC@ PR151 0_0402_5% UGATE31 2UGATE3-1 @ 2 QC@ PC132 1U_0603_10V6K QC@ PR133 0_0603_5% QC@ PC144 0.22U_0603_16V7K 40 39 38 37 36 35 34 33 32 31 BOOT2 PR174 @ PHASE2G PC155 1U_0603_10V6K PWMG2 PR147 ISL6208BCRZ-T_QFN8_2X2 BOOT1G ISUMNG RTNG FBG COMPG PGOODG PWM2G LGATE1G PHASE1G UGATE1G BOOT1G UGATE UGATE1G ISEN3/FB2 ISEN2 ISEN1 ISUMP ISUMN RTN FB COMP PGOOD BOOT1 VCC PC158 10U_0805_25V6K @ PC126 0.1U_0402_16V7K TP +5VS PHASE1G BOOT2 UGATE2 PHASE2 LGATE2 VCCP VDD PWM3 LGATE1 PHASE1 UGATE1 QC@ PQ31 MDV1525URH_PDFN33-8-5 2 +1.05VS_VTT 41 ISUMPG ISEN1G ISEN2G NTCG SCLK ALERT# SDA VR_HOT# VR_ON NTC UGATE2G DC@ PR137 2.55K_0402_1% LGATE1G 11 12 13 14 15 16 17 18 19 20 @ @ PH5 470K_0402_5%_ TSM0B474J4702RE 2 1 PR168 0_0402_5% PR169 130_0402_1% PR170 75_0402_5% PR171 54.9_0402_1% 470K_0402_5%_ TSM0B474J4702RE 2 PR160 0_0402_5% PR161 0_0402_5% PR164 0_0402_5% PR165 0_0402_5% @ PC156 47P_0402_50V8J 10 ISEN1G ISEN2G NTCG SCLK ALERT# SDA PR172 27.4K_0402_1% +5VS PH4 QC@ PC152 0.22U_0603_10V7K DC@ PR155 0_0402_5% PU13 PR173 3.83K_0402_1% PR158 3.83K_0402_1% VR_SVID_CLK VR_SVID_ALRT# VR_SVID_DAT VR_HOT# VR_ON C QC@ PC151 0.22U_0603_10V7K DC@ PC140 0.1U_0603_25V7K PR152 27.4K_0402_1% PC138 330P_0402_50V7K QC@ PC143 1U_0603_10V6K DC@ PR143 154K_0402_1% VSUMG+ PWMG2 1 1.91K_0402_1% +3VS CPU_B+ QC@ PU11 QC@ PR137 3.65K_0402_1% PC141 0.1U_0603_25V7K QC@ PC140 0.22U_0603_16V7K 2 @ PC139 0.022U_0402_16V7K 2 QC@ PR143 169K_0402_1% 2 PR142 11K_0402_1% PR141 2.61K_0402_1% 1U_0402_16V7K PC137 PH3 10KB_0402_5%_ERTJ0ER103J D PC135 150P_0402_50V8J PR136 267K_0402_1% PR139 2K_0402_1% QC@ PR135 316_0402_1% QC@ PR149 0_0603_5% DC@ PR135 357_0402_1% VSUMG- PC134 470P_0402_50V7K 2 PR134 499_0402_1% QC@ PC133 47P_0402_50V8J 1 PC127 0.01UF_0402_25V7K @ PR132 10_0402_1% QC@ PR153 0_0603_5% 10_0402_1% +5VS DC@ PC133 33P_0402_50V8J @ PC125 1000P_0402_50V7K 2 @ PR131 VCC_AXG_SENSE VSS_AXG_SENSE QC@ PC128 10U_0805_25V6K +VGFX_CORE Rev B 4019ID Friday, January 06, 2012 Sheet 52 of 60 0 0 1 1 1 1 0 0 0 0 0 0 BOOT2_VGA 2S@ PC195 0.22U_0603_10V7K BOOT2_2_VGA UGATE2_VGA 2S@ F +3VS GPU_VID6 GPU_VID5 GPU_VID4 GPU_VID3 GPU_VID2 GPU_VID1 GPU_VID0 @ PD12 RB751V-40TE17_SOD323-2 PR219 100K_0402_5% H 2 2S@ PR211 10K_0402_5% 2S@ PR214 3.65K_0402_1% 1 @ PR213 2.2_1206_5% B+ 2S@ PL24 0.36UH_PDME104T-R36MS0R825_37A_20% G +VGA_CORE V2N_VGA DCR: 0.82mΩ±5% 2S@ PR215 1_0402_5% 2S@ PR217 10K_0402_5% 2V1N_VGA VSUM+_VGA LGATE2_VGA GPU@ PR216 1.91K_0402_1% 51> VGA_PWROK @ VSUM-_VGA ISEN2_VGA @ PC198 680P_0402_50V7K CLK_ENABLE#_VGA 2S@ PQ42 MDU1511RH_POWERDFN56-8-5 @ PR212 1.91K_0402_1% GPU@ PR218 0_0402_5% GPU@ PL23 FBMA-L11-322513-151LMA50T_1210 PHASE2_VGA +3VS +VGA_B+ 1 GPU@ PC331 0.1U_0402_16V7K 2S@ PR208 2.2_0603_5% 2 VID0 0.9V VID1 2S@ PC194 10U_0805_25V6K N13P GV VID2 GPU@ PR210 10K_0402_1% G 0.9V VID3 GPU@ PR209 68K_0402_1% VGA_ON N13P GL VID4 GPU@ PR207 0_0402_5% @ PR278 0_0402_5% +3VSDGPU GPU_VID5 GPU_VID4 GPU_VID3 GPU_VID2 GPU_VID1 GPU_VID0 N12P GV4 0.9V VID5 2S@ PC193 10U_0805_25V6K N12P GS4 0.975V H VID6 Default Voltage 2S@ PC192 2200P_0402_50V7K VGA Chipset PC191 0.1U_0603_25V7K 2S@ PQ41 MDU1516URH_POWERDFN56-8-5 F GPU@ PR220 47K_0402_1% +3VS GPU@ PR222 0_0402_5% 2 +5VS E GPU@ PR221 0_0402_5% GPU@ PC201 1U_0603_10V6K +VGA_B+ Layout Note: Place near Phase1 Choke GPU@ PC213 10U_0805_25V6K GPU@ PC212 10U_0805_25V6K VSUM+_VGA @ PC223 680P_0402_50V7K +VGA_CORE GPU@ PC91 56P_0402_50V8 GPU@ PC89 56P_0402_50V8 GPU@ PC88 56P_0402_50V8 1 2S@ PR242 10K_0402_5% 2V2N_VGA 2 GPU@ PR238 3.65K_0402_1% 1 @ PR237 2.2_1206_5% C V1N_VGA DCR: 0.82mΩ±5% GPU@ PR240 1_0402_5% GPU@ PR234 2.61K_0402_1% LGATE1_VGA @ 2S@ PR245 953_0402_1% GPU@ PL25 0.36UH_PDME104T-R36MS0R825_37A_20% PHASE1_VGA GPU@ PR241 11K_0402_1% GPU@ PC218 0.1U_0603_25V7K 2 @ VSUM-_VGA B ISEN1_VGA VSUM-_VGA GPU@ PC224 0.1U_0402_16V7K GPU@ PR244 10_0402_5% GPU@ PC214 0.22U_0603_10V7K GPU@ PH7 10K_0402_1%_TSM0A103F34D1RZ 2 2S@ PC217 0.22U_0603_16V7K 1 GPU@ PC221 1000P_0402_50V7K PC216 0.01U_0402_25V7K VSSSENSE_VGA GPU@ PR243 0_0402_5% @ GPU@ PC215 330P_0402_50V7K PR233 82.5_0402_5% GPU@ PR236 0_0402_5% 1 PC222 330P_0402_50V7K VCCSENSE_VGA B GPU@ PR235 2.2_0603_5% BOOT1_1_VGA LL Disable phase OCP ~33A phase OCP ~57A 2S@ PR239 10K_0402_5% VSUM+_VGA GPU@ PR232 10_0402_5% 1 @ +VGA_CORE C PC210 0.1U_0603_25V7K UGATE1_VGA VSUM-_VGA GPU@ PC211 2200P_0402_50V7K +5VS GPU@ PC209 0.22U_0603_25V7K GPU@ PC208 1U_0603_10V6K 2 D +VGA_B+ GPU@ PR230 1_0402_5% +5VS +5VS BOOT1_VGA GPU@ PR231 255K_0402_1% ISEN1_VGA GPU@ PR229 324K_0402_1% 1S@ PR249 0_0402_5% ISEN2_VGA 2 GPU@ PR226 0_0402_5% GPU@ PQ43 MDU1516URH_POWERDFN56-8-5 GPU@ PR228 0_0402_5% GPU@ PQ44 MDU1511RH_POWERDFN56-8-5 GPU@ PC203 470P_0402_50V7K 1S@ PR252 0_0402_5% 2 ISL62883CHRTZ-T_TQFN40_5X5 11 12 13 14 15 16 17 18 19 20 GPU@ PR225 499_0402_1% 1 GPU@ PC205 150P_0402_50V8J AGND GPU@ PR227 3.57K_0402_1% D 41 30 29 28 27 26 25 24 23 22 21 GPU@ PC204 47P_0402_50V8J 2 2 GPU@ PC202 1000P_0402_50V7K GPU@ PR224 8.06K_0402_1% 1S@ PR223 120K_0402_1% @ PC200 33P_0402_50V8J BOOT2 UGATE2 PHASE2 VSSP2 LGATE2 VCCP PWM3 LGATE1 VSSP1 PHASE1 1 @ PR199 3.83K_0402_1% PGOOD PSI# RBIAS VR_TT# NTC VW COMP FB ISEN3 ISEN2 ISEN1 VSEN RTN ISUMISUM+ VDD VIN IMON BOOT1 UGATE1 2 10 2S@ PC207 0.22U_0402_10V4Z @ PR186 27.4K_0402_1% 2S@ PC206 0.22U_0402_10V4Z E 40 39 38 37 36 35 34 33 32 31 @ PR275 10K_0402_5% @ PH8 470K_0402_5%_ TSM0B474J4702RE 2S@ PC199 1U_0603_10V6K CLK_EN# DPRSLPVR VR_ON VID6 VID5 VID4 VID3 VID2 VID1 VID0 GPU@ PU14 GPU_HOT# 1S@ PR245 590_0402_1% 1S@ PC217 0.1U_0603_25V7K A 2011/06/02 Issued Date Deciphered Date 2012/06/02 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D C DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A Compal Electronics, Inc Compal Secret Data Security Classification SCHEMATIC,MB A7912 Document Number Rev B 4019ID Friday, January 06, 2012 Sheet 53 of 60 PWR Rule CPU 330uF/9m *5,22uF *16,10uF*10 GFX 470uF/4.5m*1,330uF/9m*1,22uF*12 PC246 22U_0805_6.3V6M PC245 22U_0805_6.3V6M PC244 22U_0805_6.3V6M PC243 22U_0805_6.3V6M PC242 22U_0805_6.3V6M @ PC262 22U_0805_6.3V6M @ PC261 22U_0805_6.3V6M PC260 22U_0805_6.3V6M PC259 22U_0805_6.3V6M PC258 330U_D2_2V_Y PC257 330U_D2_2V_Y PC241 22U_0805_6.3V6M PC256 470U_D2_2VM_R4.5M PC255 330U_D2_2V_Y @ 2 2 2 2 2 2 2 PC254 22U_0805_6.3V6M 2 @ 1 PC253 22U_0805_6.3V6M @ 1 PC252 22U_0805_6.3V6M + PC240 10U_0805_25V6K 1 PC251 22U_0805_6.3V6M + D +CPU_CORE 1 PC239 10U_0805_25V6K 2 PC250 22U_0805_6.3V6M + PC249 22U_0805_6.3V6M C PC248 22U_0805_6.3V6M + PC247 22U_0805_6.3V6M PC238 10U_0805_25V6K PC237 10U_0805_25V6K PC236 10U_0805_25V6K 2 1 PC235 22U_0805_6.3V6M PC234 22U_0805_6.3V6M PC233 22U_0805_6.3V6M PC232 22U_0805_6.3V6M PC231 22U_0805_6.3V6M PC230 22U_0805_6.3V6M PC229 10U_0805_25V6K PC228 10U_0805_25V6K PC227 10U_0805_25V6K PC226 10U_0805_25V6K D PC225 10U_0805_25V6K +VGFX_CORE +CPU_CORE @ C 2 PC270 22U_0805_6.3V6M PC269 22U_0805_6.3V6M PC268 22U_0805_6.3V6M PC267 22U_0805_6.3V6M PC266 22U_0805_6.3V6M PC265 22U_0805_6.3V6M ‧ Can connect to GND if motherboard only supports external graphics and if GFX VR is not stuffed in a common motherboard design, ‧ VAXG can be left floating in a common motherboard design (Gfx VR keeps VAXG from floating) if the VR is stuffed PC264 22U_0805_6.3V6M Vaxg PC263 22U_0805_6.3V6M +CPU_CORE + PC271 330U_D2_2V_Y + + PC272 330U_D2_2V_Y 2 + PC273 330U_D2_2V_Y PC274 330U_D2_2V_Y + PC275 470U_D2_2VM_R4.5M B B @ + @ 2 PC285 22U_0805_6.3V6M PC284 22U_0805_6.3V6M PC283 22U_0805_6.3V6M PC282 22U_0805_6.3V6M PC280 22U_0805_6.3V6M PC281 PC291 22U_0805_6.3V6M 330U_D2_2.5VY_R15M @ PC279 22U_0805_6.3V6M PC290 330U_D2_2.5VY_R15M PC289 22U_0805_6.3V6M 2 PC278 22U_0805_6.3V6M 1 PC288 22U_0805_6.3V6M 2 PC277 22U_0805_6.3V6M PC286 22U_0805_6.3V6M PC276 22U_0805_6.3V6M +1.05VS_VTT 1 PC287 22U_0805_6.3V6M +1.05VS_VTT + A A INTEL Recommend 3*330uF(1 in other page),12*22uF, no stuff from PDDG 1.0 2011/06/02 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification Deciphered Date 2012/06/02 Title SCHEMATIC,MB A7912 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: Rev B 4019ID Friday, January 06, 2012 Sheet 54 of SCHEMATIC,MB A7912 60 + + + GPU@ PC220 470U_V_2.5VM + 2 2 @ PC315 22U_0805_6.3V6M GPU@ PC299 0.1U_0402_16V7K GPU@ PC307 4.7U_0603_6.3V6K @ PC314 22U_0805_6.3V6M GPU@ PC298 0.1U_0402_16V7K GPU@ PC306 4.7U_0603_6.3V6K @ PC313 22U_0805_6.3V6M GPU@ PC297 0.1U_0402_16V7K GPU@ PC305 4.7U_0603_6.3V6K GPU@ PC312 22U_0805_6.3V6M GPU@ PC296 0.1U_0402_16V7K GPU@ PC304 4.7U_0603_6.3V6K GPU@ PC311 47U_0805_4V6 GPU@ PC295 0.1U_0402_16V7K GPU@ PC303 4.7U_0603_6.3V6K GPU@ PC310 470U_V_2.5VM GPU@ PC294 0.1U_0402_16V7K GPU@ PC302 4.7U_0603_6.3V6K GPU@ PC293 0.1U_0402_16V7K 2 GPU@ PC301 4.7U_0603_6.3V6K GPU@ PC339 4.7U_0603_6.3V6K 1 GPU@ PC338 4.7U_0603_6.3V6K + GPU@ PC219 390U_2.5V_M +VGA_CORE GPU@ PC337 4.7U_0603_6.3V6K 1 GPU@ PC309 4.7U_0603_6.3V6K 2 @ PC197 330U_D2_2V_Y 1 GPU@ PC336 4.7U_0603_6.3V6K C GPU@ PC292 0.1U_0402_16V7K 2 GPU@ PC300 4.7U_0603_6.3V6K GPU@ PC196 390U_2.5V_M GPU@ PC308 4.7U_0603_6.3V6K D GPU@ PC335 4.7U_0603_6.3V6K 2 Security Classification Issued Date 2011/06/02 Deciphered Date 2012/06/02 +VGA_CORE Under GPU D C Near GPU B B A A Compal Secret Data Title Compal Electronics, Inc THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: Document Number SCHEMATIC,MB A7912 4019ID Friday, January 06, 2012 Rev Sheet 55 of 60 B Version change list (P.I.R List) Item Fixed Issue Reason for change S3 sequence @ DC Meet Intel sequence SPEC 1.5VSDGPU lose Improve FB pin anit-noise Cut-in SMT memo Rev PG# Modify List Page of for PWR Change RP91 to 267K 2011 1208 DVT 51 Change RP248 to 2K, PR255 to 1.74K, PR253 to 137K 2011 1208 DVT 52 Add PC182, PC184 2011 1208 DVT 2011 1212 2011 1217 DVT 2011 1221 DVT Standard design D Change PR138, PR150, PR178, PR194, RP205 , PR235 to 2.2 Vth has risk Enable select Phase 49 D Date Cut-in EMI solution 51 Change PU16 from G971 to APL5930 51 Add PR266 53 Add PC88, PC89, PC91 DVT C C 10 11 B B 12 13 14 15 16 17 A 18 A 19 2011/06/02 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification Deciphered Date 2012/06/02 Title SCHEMATIC,MB A7912 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: Rev B 4019ID Friday, January 06, 2012 Sheet 56 of 60 Version change list (P.I.R List) Item D Fixed Issue Reason for change Rev PG# Modify List Page of for PWR Date Phase D C C 10 11 B B 12 13 14 15 16 A A 17 2011/06/02 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification Deciphered Date 2012/06/02 Title SCHEMATIC,MB A7912 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: Rev B 4019ID Friday, January 06, 2012 Sheet 57 of 60 Version Change List ( P I R List ) Item Page# D C B Date Request Owner Page Issue Description Solution Description Rev P.40.13 9/7 EC Change th HDA_SDO to ME_EN P.40 9/7 HW Add R2085 ,change the EC_ACIN pull high to +3VLP 0.2 P.37 9/7 HW Add fl1009 USB3.0 TX coupling capacitor (c2060,c2061) 0.2 P.38.39.40 9/7 HW Add USB chargaer schematic(C2060.C2061.R2077~R2084,R2065~R2072) 0.2 P.22.40 9/7 HW Follow ABO request,add ADPS function(Q2005),R2086.R2087) 0.2 P.20 9/7 HW Add +5VALW TO +5VALW_PCH schematic(Q2006.C2062.R2088) 0.2 P.44 9/7 HW Add +3VALW TO +3VALW_PCH schematic(U2006,R2073~R2076,C2056~C2059,Q2003,Q2004) 0.2 P.43 9/7 HW For FSOV spec,Chang R714,R716 from 75ohm to 47ohm 0.2 P.13 9/7 HW For WIN8,Change R681.R651.R684.R652 to 33ohm 0.2 10 P.44 9/7 HW Delete C817,Change C826 from D2 size to B2 size 0.2 11 P.17.37 9/7 HW Follow chief river common design, please chang Mini-Card 2(port 11) to port 0.2 12 P.38 9/7 HW Delete +1.5V to +1.05V_V128 Transfer(U2002.R2002.R2003.R2005.C2002.C2003.C2005.R2008) 0.2 13 P.38 9/7 HW Delete USB3.0 EEPROM(U2004.R2035.R2034.C2039) 0.2 14 P.37 9/7 HW Reserve Mini-Card 0.2 15 P.19 9/7 HW 16 P.22.40 9/8 HW 17 P41 9/14 HW 18 19 A Title P27.30 P06.11.17.35 P39.40.42 9/14 HW 9/14 HW 20 P16 9/16 HW 21 P31 9/16 HW 0.2 Add SW5.SW6 for EG project 0.2 Swap MDC37 and MDC38 Swap MDA13 and MDA14 For ESD request Add C2065~C2075 For HDMI PCH_DPB_HPD noise Add C2076 For LVDS power sequence Change R5 from 300 to 200 ohm Change R2 from 1k to 10k ohm change C2 from 0.047uF to 1uF 0.2 0.2 0.2 9/16 HW Delete PCH test ponit(T31~T46,T49~T61,T63~T65) 0.2 23 P21,40 9/19 HW Change Q22,Q26 from SB000008J10 to SB000009080 0.2 P14,22,35,38 9/19 HW For Crystal Change Y2 ,Y4 from SJ10000DJ00 to SJ10000E800 Change Y1000 from SJ10000DK00 to SJ100009700 Change C630,C631,C2019,C2028,C1008,C1009 to 10pF Change C681,C679 to 15pF Issued Date 0.2 2011/06/02 2012/06/02 Deciphered Date Title SCHEMATIC,MB A7912 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A Compal Electronics, Inc Compal Secret Data Security Classification B 0.2 P18 C F2 flick issue on projector P5202 D-sub 0.2 Add C2063.C2064 Change VGA GPIO12 of dGPU connection to EC controlled for the power limited usage 0.2 Add EC pin 107 >GPU_ACIN 22 24 D Rev B 4019ID Sheet Friday, January 06, 2012 58 of 60 Version Change List ( P I R List ) Item Page# D Title Date Request Owner Page Issue Description Solution Description Rev 25 P.44 9/20 EMI For EMI request (Add C2079~C2084) 26 P.36 9/20 HW For SD3.0 issue (Add R2088.R2089) 0.2 27 P.20 10/17 HW Add +5VALW TO +5VALW_PCH schematic(Q2006.C2062.R2090) 0.3 28 P.44 10/17 HW Add +3VALW TO +3VALW_PCH schematic(U2006,R2073~R2076,C2056~C2059,Q2003,Q2004) 0.3 29 P.40 10/17 HW 30 P.40 10/17 HW 31 P.17,39 10/17 HW 32 P.18 10/18 HW Board ID error Add R353 Board ID 0.3 Change R353 to 18K Follow Intel’s suggestion; Change USB3.0 from port to port Change USB2.0 from port 0,1 to port 2,9 Support eDP GPIO71 >0 (eDP) GPIO71 >1 (LVDS) Co_lay NPCE885N Delete U38,C722,R690,R695,C727 Add C2085,R2091~R2096 C 33 P.13.40 10/25 0.2 HW D 0.3 0.3 0.3 0.3 C 0.3 B B A A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2011/06/02 2012/06/02 Deciphered Date Title SCHEMATIC,MB A7912 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: Rev B 4019ID Sheet Friday, January 06, 2012 59 of 60 Version Change List ( P I R List ) Item Page# D C B A Title Date Request Owner Page Issue Description Solution Description Rev Delete SW5,SW6, Pop SW2,SW3 43 P.41 11/16 ME 44 P.05 11/16 HW BUF_CPU_RST# noise Add C2090 45 P.35 11/17 HW LAN SPROM on Chip De-pop U31,R537 Pop R538 46 P.36 11/17 EMI 47 P.13 11/17 HW 48 P.31,32,41 11/17 ESD De-pop D3,D4,D17,D18,D15 Pop D24,D36 0.4 49 P.40 11/17 HW De-pop R891,R893 0.4 50 P.24 11/21 HW N13P_GS Change strap2 to PD 15k Change strap4 to PD 10k 0.4 51 P.13 11/21 HW Chip Select Change R651,R2049 to 0ohm 0.4 52 P.13,40 11/21 HW Delete NPCE885N (R2091.R2092.R2094.R2095.R2096,R698, R699,R692,C2085) 0.4 53 P.45 11/22 HW Change +1.05VSDGPU JUMP size PJ19 change to 43x118 0.4 55 P.35,36 11/23 HW 0.4 56 P.13 11/23 HW Card Reader Change R216 to 22 ohm Change R2088 to 47ohm Change R2089 to 22 ohm Add C2091~C2093 Change R525,R536,R537,R538 to 1k Delete R2093,R2049,R651(0ohm) 57 P.13 11/23 HW Change N13P-GS to SA000051880 Change U33 to SA00005AG00 0.4 58 P.35, P36 11/23 HW 0.4 59 P.36 11/24 HW Del C2093, R222, R2089, net(CR_CLK_XD_RY_BY#_23) Add R2101, C2094 ADD R2102, C2096 for EMI ISSUE 0.4 0.4 0.4 Change C478 to 10P_50V 0.4 Change C682,C686 to 15P RTC issue Issued Date 0.4 2011/06/02 2012/06/02 Deciphered Date 0.4 A Title SCHEMATIC,MB A7912 Date: B 0.4 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC C Compal Electronics, Inc Compal Secret Data Security Classification D Rev B 4019ID Sheet Friday, January 06, 2012 60 of 60 ... 0.22U_0 402_ 10V6K 0.22U_0 402_ 10V6K 0.22U_0 402_ 10V6K 0.22U_0 402_ 10V6K 0.22U_0 402_ 10V6K 0.22U_0 402_ 10V6K 0.22U_0 402_ 10V6K 0.22U_0 402_ 10V6K 0.22U_0 402_ 10V6K 0.22U_0 402_ 10V6K 0.22U_0 402_ 10V6K 0.22U_0 402_ 10V6K... 0.22U_0 402_ 10V6K 0.22U_0 402_ 10V6K 0.22U_0 402_ 10V6K 0.22U_0 402_ 10V6K 0.22U_0 402_ 10V6K 0.22U_0 402_ 10V6K 0.22U_0 402_ 10V6K 0.22U_0 402_ 10V6K 0.22U_0 402_ 10V6K 0.22U_0 402_ 10V6K 0.22U_0 402_ 10V6K 0.22U_0 402_ 10V6K... C1037 0.1U_0 402_ 16V4Z DIS@ C 1027 0.1U_0 402_ 16V4Z DIS@ C 1026 0.1U_0 402_ 16V4Z DIS@ C 1025 0.1U_0 402_ 16V4Z DIS@ C 1024 1U_0 402_ 6.3V6K DIS@ C 1023 4.7U_0603_6.3V6K C Under GPU DIS@ C1017 1U_0 402_ 6.3V6K