Áp dụng các kỹ thuật điều chế độ rộng xung để cải tiến chất lượng điện cho bộ nghịch lưu ba bậc NPC

ĐẠI HỌC QUỐC GIA TP HCM TRƯỜNG ĐẠI HỌC BÁCH KHOA PHẠM ĐĂNG KHOA ÁP DỤNG CÁC KỸ THUẬT ĐIỀU CHẾ ĐỘ RỘNG XUNG ĐỂ CẢI TIẾN CHẤT LƯỢNG ĐIỆN NĂNG CHO BỘ NGHỊCH LƯU BA BẬC NPC Chuyên ngành : Kỹ Thuật Điện Mã số: 60520202 LUẬN VĂN THẠC SĨ TP HỒ CHÍ MINH, năm 201 CƠNG TRÌNH ĐƯỢC HOÀN THÀNH TẠI TRƯỜNG ĐẠI HỌC BÁCH KHOA –ĐHQG -HCM Cán hướng dẫn khoa học : PGS.TS Nguyễn Văn Nhờ (Ghi rõ họ, tên, học hàm, học vị chữ ký) Cán chấm nhận xét : (Ghi rõ họ, tên, học hàm, học vị chữ ký) Cán chấm nhận xét : (Ghi rõ họ, tên, học hàm, học vị chữ ký) Luận văn thạc sĩ bảo vệ Trường Đại học Bách Khoa, ĐHQG Tp HCM ngày tháng năm 201 Thành phần Hội đồng đánh giá luận văn thạc sĩ gồm: (Ghi rõ họ, tên, học hàm, học vị Hội đồng chấm bảo vệ luận văn thạc sĩ) Xác nhận Chủ tịch Hội đồng đánh giá LV Trưởng Khoa quản lý chuyên ngành sau luận văn sửa chữa (nếu có) CHỦ TỊCH HỘI ĐỒNG TRƯỞNG KHOA ĐIỆN-ĐIỆN TỬ ĐẠI HỌC QUỐC GIA TP.HCM TRƯỜNG ĐẠI HỌC BÁCH KHOA CỘNG HÒA XÃ HỘI CHỦ NGHĨA VIỆT NAM Độc lập - Tự - Hạnh phúc NHIỆM VỤ LUẬN VĂN THẠC SĨ Họ tên học viên : PHẠM ĐĂNG KHOA MSHV:7140413 Ngày, tháng, năm sinh: 10/01/1990 Nơi sinh: TP HỒ CHÍ MINH Chuyên ngành: Kỹ Thuật Điện Mã số : 60520202 I TÊN ĐỀ TÀI: ÁP DỤNG CÁC KỸ THUẬT ĐIỀU CHẾ ĐỘ RỘNG XUNG ĐỂ CẢI TIẾN CHẤT LƯỢNG ĐIỆN NĂNG CHO BỘ NGHỊCH LƯU BA BẬC NPC II NHIỆM VỤ VÀ NỘI DUNG: + Khảo sát chọn kỹ thuật điều chế độ rộng xung cho nghịch lưu ba bậc NPC + Đề phương pháp để đánh giá so sánh kỹ thuật điều chế độ rộng xung chọn + Xây dựng mơ hình mơ MATLAB cho tất phương pháp chọn để tiến hành lấy kết so sánh kết tất phương pháp + Xây dựng mơ hình thực NPC ba bậc Các phương pháp chọn lập trình vi điều khiển TMS320F377D Kết lấy từ thực nghiệm so sánh với nhau, đồng thời kiểm chứng kết mô + Áp dụng kỹ thuật điều chế độ rộng xung năm bậc NPC bảy bậc cascade nghịch lưu vào nghịch lưu ba bậc NPC để triệt tiêu điện áp common mode, đồng thời giảm độ méo dạng dịng giảm tổn hao đóng cắt III NGÀY GIAO NHIỆM VỤ : 10/07/2017 IV NGÀY HOÀN THÀNH NHIỆM VỤ : 03/12/2017 V CÁN BỘ HƯỚNG DẪN: PGS.TS Nguyễn Văn Nhờ Tp HCM, ngày 03 tháng 12 năm 2017 CÁN BỘ HƯỚNG DẪN (Họ tên chữ ký) CHỦ NHIỆM BỘ MÔN ĐÀO TẠO (Họ tên chữ ký) TRƯỞNG KHOA ĐIỆN-ĐIỆN TỬ (Họ tên chữ ký) ACKNOWLEDGEMENTS Thank you to Prof Nguyen Van Nho who have helped guide me through this exciting and challenging journey, provide insightful feedback, and teach me how to conduct thorough research His wisdom and expertise in this field of study is exceptional, and it was both a pleasure and an honor to have him as an advisor and a professor I would like to thank Mr Nguyen Van Vui for his practical experience during the experiment setup Finally, I sincerely thank my family for all of their support they have given to me over the years ABSTRACT Multilevel Inverters especially the three-level Neutral Point Clamped Inverters are widely used in motor drive applications Compared to the conventional two-level inverters, the three-level inverters offer better harmonic performance However, Common-mode Voltage and Neutral Point Voltage Imbalance are the two technical challenges that need to be addressed in order to optimize the performance of motor drive systems The Common-mode voltage causes bearing failure and Electromagnetic Interference (EMI) These two problems reduce the life expectancy of motors and have other equipment working in close proximity not to function properly Moreover, the Neutral Point Voltage Imbalance causes excessive stress on switching devices and low-order harmonics at the output Therefore, both common-mode voltage and neutral point voltage imbalance must be mitigated by either hardware or software solutions In this thesis, the software solutions, specifically Pulse-Width Modulation (PWM) strategies are the main focus The thesis tackles the problem in the literature, which is the common-mode voltage and neutral point voltage imbalance are solved separately For example, a certain proposed PWM method for CMV reduction does not mention neutral point voltage imbalance, and vice versa Therefore, the thesis aims to select some prominent PWM strategies in the literature and make a comparison among them in terms of CMV mitigation, NP voltage balancing performance, and harmonic distortion The simulation of all the PWM methods are implemented from MATLAB 2016b while the experiment is conducted at PERLAB The simulation results are compared against one another The experimental results are also compared against one another validate the simulation results TÓM TẮT Nghịch lưu đa bậc, đặc biệt nghịch lưu ba bậc NPC sử dụng rộng rãi ứng dụng điều khiển động So với nghịch lưu hai bậc thông thường, nghịch lưu ba bậc cho chất lượng đầu tốt Tuy nhiên, điện áp common mode lệch điện áp trung tính hai vấn đề cần giải để tối ưu hóa hệ thống điều khiển động Điện áp common mode gây nhiều hư hỏng cho động nhiễu điện từ trường Hai vấn đề làm giảm tuổi thọ động thiết bị xung quanh Hơn nữa, lệch điện áp trung tính tụ gây hài bậc thấp dòng áp ngõ Do đó, điện áp common mode lệch điện áp trung tính tụ cần giải phương pháp phần cứng hay phần mềm Trong luận văn này, phương pháp phần mềm đặc biệt phương pháp độ rộng xung trọng tâm Luận văn giải vấn đề điện áp common mode lệch điện áp tụ trung tính thường giải riêng lẽ Do đó, luận văn chọn số phương pháp điều chế độ rộng xung tiêu biểu so sánh phương pháp mặc giảm common mode, khả cân tụ, độ méo dạng song hài ngõ Kết mô phương pháp thực MATLAB thực nghiệm tiến hành phịng thí nghiệm PERLAB Kết mô so sánh đối chiếu với Kết thực nghiệm so sánh đối chiếu với xác nhận kết mô DECLARATION I certify that the work is that of the author alone The work has not been submitted previously The content of the thesis is the result of work which has been carried out since the official commencement date of the thesis Pham Dang Khoa TABLE OF CONTENTS Acknowledgements…………………………………………………………………………………………………………………….1 Abstract……………………………………………………………………………………………………………………………….…… Declaration…………………………………………………………………………………………………………………………….… Table of Contents…………………………………………………………………………………………………….………………….4 List of Figures………………………………………………………………………………………………………… ………………….7 List of Tables…………………………………………………………………………………………………………………………… 15 Introduction……………………………………………………………………………………………………………………… 16 1.1 Background………………………………………………………………………………………………………………….17 1.2 Problem Definition………………………………………………………………………………………….……………18 1.3 Current Understanding of the Problem, Existing Solutions, and Barriers to these Solutions…………………………………………………………………………………………………………………………….19 1.4 Expected Results and its Significance………………………………………………………………………… 20 Literature Review of Common-Mode Voltage Problem……………………………………………………….…21 2.1 Common-mode Voltage Definition…………………………………………………………………………… 21 2.2 Causes of Common-Mode Voltage……………………………………………………………………………….21 2.3 Common-Mode Voltage’s Effects on motor drive systems………………………………………… 22 2.4 Solutions to Mitigate Common-Mode Voltage…………………………………………………………… 26 2.4.1 Hardware Solutions to Mitigate Common-Mode Voltage………………………………… 26 2.4.2 Software Solutions to Mitigate Common-Mode Voltage………………………….……… 33 Literature Review of Neutral Point Voltage Imbalance Problem……………………………….……….…38 3.1 Neutral Point Voltage Imbalance Definition……………………………………………………….……… 38 3.2 Causes of Neutral Point Voltage Imbalance……………………………………………………….…………38 3.3 NP Voltage Imbalance’s Effects……………………………………………………………………….……………39 3.4 Solutions to Mitigate Neutral Point Voltage Imbalance…………………………………….………….39 Methodology………………………………………………………………………………………………………… …………….47 Implementations of the Selected Pulse-Width Modulation (PWM) Methods in Three-Level Neutral Point Clamped Inverters…………………………………………………………………………………… ……… 49 5.1 Conventional Sinusoidal Pulse-Width Modulation (SPWM)………………………………………….49 5.2 Sinusoidal Pulse-Width Modulation with the Proportional Controller (SPWM+P)…………50 5.3 Sinusoidal Pulse-Width Modulation by Song (SPWM+Song)…………………………………………52 5.4 Centered Space Vector Pulse Width Modulation with the Proportional Controller (CSVPWM+P)…………………………………………………………………………………………………………………… 55 5.5 Optimized Nearest Three Virtual Vectors (ONTVV)………………………………………………………58 5.6 Zero Common-Mode Voltage Pulse-Width Modulation with reduced switching loss (ZCMV PWM with reduced switching loss)…………………………………………………………………………61 5.7 Zero Common-Mode Voltage Pulse-Width Modulation with reduced current ripple (ZCMV PWM with reduced current ripple)…………………………………………………………………………65 Simulation and Experiment………………………………………………………………………………………………… 67 6.1 Simulation Setup…………………………………………………………………………………………………………67 6.1.1The SPWM with Proportional Controller (SPWM+P)……………………………………………68 6.1.2 The Centered Space Vector with Proportional Controller (CSVPWM+P)…………….69 6.1.3 The SPWM+Song……………………………………………………………………………………………….70 6.1.4 The Optimized Nearest Three Virtual Vector (ONTVV)……………………………………….71 6.1.5 The Zero Common Mode Voltage PWM with reduced switching loss (ZCMV PWM + reduced switching loss)……………………………………………………………………………………………….72 6.1.6 The Zero Common Mode Voltage PWM with reduced current ripple (ZCMV PWM + reduced current ripple)……………………………………………………………………………………………….73 6.2 Simulation Results…………………………………………………………………………………………………… 74 6.2.1 The SPWM with Proportional Controller (SPWM+P)…………………………………………74 6.2.2 The Centered Space Vector with Proportional Controller (CSVPWM+P)…….…… 80 6.2.4 The SPWM+Song………………………………………………………………………………………….……85 6.2.3 The Optimized Nearest Three Virtual Vector (ONTVV)……………………….…………… 90 6.2.5 The Zero Common Mode Voltage PWM with reduced switching loss (ZCMV PWM + reduced switching loss)………………………………………………………………………….……………….95 6.2.6 The Zero Common Mode Voltage PWM with reduced current ripple (ZCMV PWM + reduced current ripple)……………………………………………………………………………………… 100 6.3 Comparison and Evaluation of Simulation Results……………………………………………….……104 6.4 Experiment Setup…………………………………………………………………………….………….……………117 6.5 Experiment Results……………………………………………………………… …………………………… …124 6.5.1 The SPWM with Proportional Controller (SPWM+P)……………………………… ….… 124 6.5.2 The Centered Space Vector with Proportional Controller (CSVPWM+P)…….…….129 6.5.3 The Optimized Nearest Three Virtual Vector (ONTVV)………………………… …………135 6.5.4 The SPWM+Song……………………………………………………………………………….…… …… 140 6.5.5 The Zero Common Mode Voltage PWM with reduced switching loss (ZCMV PWM + reduced switching loss)…………………………………………………………………… …………………146 6.5.6 The Zero Common Mode Voltage PWM with reduced current ripple (ZCMV PWM + reduced current ripple)……………………………………………………………….………………… ……151 6.6 Comparison and Evaluation of Experimental Results…………………….………… ………… 156 Conclusion and Future Works……………………………………………………………………………………… …162 LIST OF FIGURES Figure 1: Topology of Three-Level NPC Inverter………………………………………………………………….……17 Figure 2: Space Vector diagram of the NPC converter………………………………………………………………19 Figure 3: A three-level NPC inverter with a diode front-end………………………………………………….…21 Figure 4: Electrical and physical models of parasitic capacitances in a motor………………………… 22 Figure 5: Electrical representation of parasitic capacitances in a motor………………………………… 22 Figure 6: The shaft voltage and common-mode voltage in a driven-PWM inverter………………….24 Figure 7: Bearing currents in a motor……………………………………………………………………………………….24 Figure 8: An isolation transformer for CMV mitigation…………………………………………………………….27 Figure 9: Differential mode (DM) noise……………………………………………………………………………………27 Figure 10: Common-mode (CM) noise…………………………………………………………………………………… 28 Figure 11: Integrated DC choke in the CSI for CMV elimination……………………………………………… 28 Figure 12: Integrated AC choke in VSI for CMV elimination………………………………………………………29 Figure 13: Integrated DC Choke……………………………………………………………………………………………….29 Figure 14: Circular-shaped integrated AC choke………………………………………………………………………30 Figure 15: A three-level NPC inverter with an addition of a fourth-leg…………………………………….31 Figure 16: Two 2-level Inverters connected to an Induction Motor with Open-End Windings….31 Figure 17: Two Cascaded H-bridge Inverter connected to an Induction Motor with Open-End Windings………………………………………………………………………………………………………………………………….32 Figure 18: An auxiliary circuit for CMV elimination………………………………………………………………… 32 Figure 19: Phase leg during O -> P transition……………………………………………………………………………36 Figure 20: Impact of Dead time on CM voltage generation………………………………………………………36 Figure 21: The three-level NPC inverter with diode front-end………………………………………………….38 Figure 22: Effects of inverter operating modes on NP voltage and NP current…………………………39 Figure 23: Absolute NP Ripple Magnitude for 4200uF vs 840uF……………………………………………….40 Figure 24: Dynamic NP Performance for 4200uF vs 840uF……………………………………………………….40 Figure 25: Space Vector Diagram for Sector VREF is within the subsector 2……………………………41 Figure 202: The Frequency Spectrum of Phase Voltage Van Comment: The frequency spectrum of phase voltage Van in the experiment is similar to that of the simulation results The magnitude of fundamental component (50 Hz) is about 96V It also contains the harmonics at KHz and 10 KHz The Line-Line Voltage Vab Figure 203: The Line-Line Voltage Vab (100V/div, 5.00ms/div) The Frequency Spectrum of Line-Line Voltage Vab 152 Figure 204: The Frequency Spectrum of Line-Line Voltage Vab Comment: The frequency spectrum of line-line voltage Vab is similar to that of the simulation results The magnitude of fundamental component is around 165V The magnitude of harmonics around KHz is about 15V The three-phase currents ia, ib, ic Figure 205: The three-phase current ia, ib, ic The Frequency Spectrum of Phase Current ia 153 Figure 206: The Frequency Spectrum of Phase Current ia Comment: The magnitude of fundamental component of phase current ia is about 1.45 A It also contains low-order harmonics component due to the use of small inductance value of the load in the experiment (2.71 mH) The THD of the phase current is higher than that of the simulation because of the difference in the use of the inductance value of the load The Common-Mode Voltage Vno Figure 207: The Common-Mode Voltage Vno (100V/div, 5.00ms/div) The Frequency Spectrum of Common-Mode Voltage Vno 154 Figure 208: The Frequency Spectrum of Common-Mode Voltage Vno Comment: The magnitude of all the harmonics is well below 1V It demonstrates the effectiveness of the Zero CMV PWM method The DC-link capacitor voltages Vc1, Vc2 at the steady state Figure 209: The DC-link capacitor voltages Vc1, Vc2 at the steady state (100V/div, 5.00ms/div) The Frequency Spectrum of NP voltage Vn (Vc1-Vc2) 155 Figure 210: The Frequency Spectrum of NP voltage Vn (Vc1 – Vc2) Comment: Under balanced load condition, the NP voltage imbalance is small However, the rd harmonics still exist in the neutral point voltage due to charging and discharging of the upper and lower capacitor three times over the course of fundamental period 6.6 Comparison and Evaluation of Experimental Results The THD, WTHD of the output voltage and current of all the seven PWM strategies will be compared against one another for the modulation index 0.1, 0.4, 0.7, 1.0 At the transient state, the dynamic NP voltage balancing performance will be observed and compared to evaluate the effectiveness of PWM methods for balancing the NP voltage At the steady state, instead of measuring the absolute maximum magnitude of NP voltage imbalance, the magnitude of DC component and third harmonics of neutral point voltage will be observed and compared against one another The magnitude of Common-mode voltage will not be included here since all the PWM strategies have the maximum magnitude of CMV of 68V (1/3VDC) except the two ZCMV PWM methods having the maximum magnitude of CMV of almost close zero The THD of Phase Voltage Van under balanced load condition for C = 4700𝝁𝑭 156 Figure 211: The THD of Phase Voltage Van under balanced condition for C = 4700 𝜇𝐹 Comment: The experimental results are consistent with the ones in the simulation The ONTVV and CSVPWM+P offers excellent harmonic performance at low modulation index from 0.1 to 0.7 Generally, the two Zero CMV PWM methods have higher THD than PWM method with NP voltage balancing control This has been verified in the simulation results In Zero CMV PWM methods, Zero CMV PWM method with reduced current ripple has lower THD than that of reduced switching loss since the control purpose of it is to reduce the output current ripple From the Figure 211, CSPWM+P has the best harmonic performance The THD of Line-Line Voltage Vab under balanced load condition for C = 4700 𝝁𝑭 157 Figure 212: THD of Line-Line Voltage Vab under balanced condition for C = 4700 𝜇𝐹 Comment: The PWM methods with NP voltage balancing control have similar harmonic performance As expected, the two Zero CMV PWM methods have higher THD than the ones with the NP voltage balancing control The THD of the Zero CMV PWM method with reduced current ripple is less than that of the Zero CMV PWM method with reduced switching loss The WTHD of Line-Line Voltage Vab under balanced condition for C = 4700 𝝁𝑭 Figure 213: The WTHD of Line-Line Voltage Vab under balanced condition for C = 4700 𝜇𝐹 158 Comment: The harmonics performance in terms of the WTHD of line-line voltage Vab is similar for all PWM methods at the modulation index from 0.1 to 1.0 The ONTVV has the smallest WTHD of line-line voltage Vab at the low modulation index from 0.1 to 0.4 The THD of the Phase Current ia under balanced load condition C = 4700 𝝁𝑭 Figure 214: The THD of the Phase Current ia under balanced load condition C = 4700 𝜇𝐹 Comment: The ONTVV offers excellent harmonics performance in terms of the THD of the phase current at low modulation index from 0.1 to 0.7 The CSVPWM+P also has excellent harmonic performance over the whole range of modulation index At high modulation index, all PWM methods with NP voltage balancing have similar harmonics performance The two Zero CMV PWM methods have high THD compared to other methods since they not obey the Nearest Three Vector Principle (NTV) The dynamic NP voltage balancing performance under balanced load condition C = 4700 𝝁𝑭 at the transient state 159 Figure 215: The dynamic NP voltage balancing performance under balanced load condition C = 4700 𝜇𝐹 at the transient state Comment: The SPWM+Song has the best dynamic performance at the modulation index from 0.4 to 0.8 The CSVPWM+P and SPWM+P have similar dynamic performance The ONTVV has the slowest dynamic performance The results in the experimental results are consistent with the ones in the simulation The Magnitude of DC Component of NP voltage at the steady state under load condition C = 4700 𝝁𝑭 Figure 216: The Magnitude of DC Component of NP voltage at the steady state under load condition C = 4700 𝜇𝐹 160 Comment: The Magnitude of DC component of NP voltage specifies the NP voltage imbalance at the steady state The SPWM+P, CSVPWM+P, ONTVV, and SPWM+Song have small magnitude of DC component of NP voltage (well below 1V) The SPWM with the open loop has high magnitude of DC component of NP voltage as expected The Zero CMV with reduced switching loss has low magnitude of DC component of NP voltage at high modulation index from 0.7 to 1.0 The Magnitude of the 3rd component of NP voltage at steady state under load condition C = 4700 𝝁𝑭 Figure 217: The Magnitude of the 3rd component of NP voltage at steady state under load condition C = 4700 𝜇𝐹 Comment: All the PWM methods have low magnitude of 3rd component of NP voltage (below 0.2V) except the conventional SPWM 161 Conclusion and Future Works All the seven PWM strategies are implemented and analyzed in both simulation and experiement In terms of output quality, SPWM+P and CSVPWM offer a good harmonic performance over a wide range modulation index and load angle while the ONTVV has better harmonic performance for low modulation index from to 0.4 In general, there is no significant improvement of harmonic performance for PWM strategies with NP voltage balancing control As for two zero common-mode PWM methods, the harmonic performance is worse than those with NP voltage balancing control It is expected due to the fact that the two zero CMV PWM methods not utilize the Nearest Three Vector Principle (NTV) like those with the NP voltage balancing control In terms of dynamic NP voltage balancing performance, the SPWM+Song is superior over a wide range of modulation index and load angle However, it is achieved at the expense of harmonic performance The ONTVV has the worst dynamic NP voltage balancing performance The dynamic performance of SPWM+P and CSVPWM+P are comparatively similar The two Zero CMV PWM methods are not included for NP voltage balancing performance since they not contain any NP voltage balancing control In terms of NP voltage ripple at steady state which is dictated by the three-time fundamental frequency component, all the PWM methods with NP voltage balancing control have this oscillation However, the magnitude of this component of all the PWM methods are similar The magnitude of it is below 0.2 V.It is due to the fact that the DC-link capacitance value is large The magnitude of the ripple will increase when the DC-link capacitance value is small In terms of common-mode voltage elimination, the two Zero CMV PWM methods which were applied for 5-level NPC and 7-level cascaded inverters, are derived for 3-level NPC inverters The two methods successfully eliminate the CMV voltage However, the spikes still exist in the CMV waveform Therefore, the future work will develop the Zero CMV with the reduction of spikes in the CMV waveform The Zero CMV PWM methods usually result in high THD and WTHD, high switching loss, and high current ripple at the output Therefore, besides eliminating CMV, the switching loss and/or output current ripple should be included in Zero CMV PWM methods In the Zero CMV PWM method with reduced switching loss, there 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CHÍ MINH Chuyên ngành: Kỹ Thuật Điện Mã số : 60520202 I TÊN ĐỀ TÀI: ÁP DỤNG CÁC KỸ THUẬT ĐIỀU CHẾ ĐỘ RỘNG XUNG ĐỂ CẢI TIẾN CHẤT LƯỢNG ĐIỆN NĂNG CHO BỘ NGHỊCH LƯU BA BẬC NPC II NHIỆM VỤ VÀ NỘI... chọn kỹ thuật điều chế độ rộng xung cho nghịch lưu ba bậc NPC + Đề phương pháp để đánh giá so sánh kỹ thuật điều chế độ rộng xung chọn + Xây dựng mơ hình mô MATLAB cho tất phương pháp chọn để tiến. .. TẮT Nghịch lưu đa bậc, đặc biệt nghịch lưu ba bậc NPC sử dụng rộng rãi ứng dụng điều khiển động So với nghịch lưu hai bậc thông thường, nghịch lưu ba bậc cho chất lượng đầu tốt Tuy nhiên, điện áp