The following will be discussed in this chapter: Design of systems that input flip flops and combinational logic, specifications start with a word description, create a state table to indicate next states, convert next states and outputs to output and flip flop input equations, draw resulting circuits.
DLD Lecture 26 Finite State Machine Design Procedure Overvie w ° Design of systems that input flip flops and combinational logic ° Specifications start with a word description ° Create a state table to indicate next states ° Convert next states and outputs to output and flip flop input equations • Reduce logic expressions using truth tables ° Draw resulting circuits Concept of the State Machine Computer Hardware = Datapath + Control Registers Combinational Functional Units (e.g., ALU) Busses Qualifiers FSM generating sequences of control signals Instructs datapath what to next Control Control State Control Signal Outputs Qualifiers and Inputs Datapath Concept of the State Machine Concept of the State Machine Computer Hardware = Datapath + Control Registers Combinational Functional Units (e.g., ALU) Busses Qualifiers Control FSM generating sequences of control signals Instructs datapath what to next Control State Control Signal Outputs Qualifiers and Inputs Datapath °Divide circuit into combinational logic and state °Localize feedback loops and make it easy to break cycles °Implementation of storage elements leads to various forms of sequential logic Inputs Combinational Logic State Inputs Outputs State Outputs Storage Elements Designing Finite State Machines ° Specify the problem with words ° (e.g Design a circuit that detects three consecutive inputs) ° Assign binary values to states ° Develop a state table ° Use K-maps to simplify expressions ° Flip flop input equations and output equations ° Create appropriate logic diagram ° Should include combinational logic and flip flops Example: Detect Consecutive inputs ° State S0 : zero 1s detected ° State S1 : one detected ° State S2 : two 1s detected ° State S3 : three 1s detected ° Note that each state has output arrows ° Two bits needed to encode state State Table for Sequence Detector ° Sequence of outputs, inputs, and Present Next flip flop states enumerated in Input State Output State state table A B x A B y 0 0 0 0 0 0 ° 0 0 1 0 1 0 0 1 0 0 0 0 ° 0 1 1 1 0 0 1 0 0 0 0 0 ° 1 0 1 1 1 0 1 1 0 0 0 1 1 1 1 1 1 1 Present state indicates current value of flip flops Next state indicates state after next rising clock edge Output is output value on current clock edge ° S0 = 00 ° S2 = 10 ° S1 = 01 ° S3 = 11 Finding Expressions for Next State and Output Value ° Create K-map directly from state table (3 columns = K-maps) ° Minimize K-maps to find SOP representations ° Separate circuit for each next state and output value Circuit for Consecutive 1s Detector ° Note location of state flip flops ° Output value (y) is function of state ° This is a Moore machine Concept of the State Machine PI Example: Odd Parity Checker Next State/Output Functions NS = PS xor PI; OUT = PS PS NS NS Input D CLK Q R PS/Output Q \Reset D FF Implementation Input 0 1 1 1 Clk Output 1 1 0 Timing Behavior: Input 0 1 1 1 1 Mealy and Moore Machines Solution 1: (Mealy) 0/0 Even Odd Reset O/P is dependent on current state and Output input in Mealy 1/1 1/0 Transition Arc Input Solution 2: (Moore) 0/1 Mealy Machine: Output is associated with the state transition Appears before the state transition is completed (by the next clock pulse) Even Output [0] 1 Odd [1] Input Output is dependent only on current state Moore Machine: Output is associated with the state Appears after the state transition takes place Vending Machine FSM Step Step 1 Specify Specify the the problem problem Deliver package of gum after 15 cents deposited Single coin slot for dimes, nickels No change Design the FSM using combinational logic and flip flops Vending Machine FSM State Diagram State Diagram Reuse Reuse states states whenever whenever possible possible Symbolic State Table Vending Machine FSM State State Encoding Encoding How many flip-flops are needed? Vending Machine FSM Determine Determine F/F F/F implementation implementation Q1 Q0 DN Q1 Q1 Q0 DN Q1 N D Q1 N D Q0 K-map for D1 Q1 Q0 DN N D Q0 K-map for D0 Q0 K-map for Open Minimized Implementation Q1 D1 D Q0 N CLK D Q R Q1 Q1 Q OPEN Reset N Q0 Q0 D0 N Q1 N Q1 D CLK D Q R Q Q0 Q0 Reset Vending machine FSM implementation based on D flipflops(Moore) Count Sequence Design Procedure Complex Count Sequence Step 1: Derive the State Transition Diagram Count sequence: 000, 010, 011, 101, 110 Design Procedure More Complex Count Sequence Design Procedure Complex Count Sequence Design Procedure Complex Count Sequence Design Procedure Complex Count Sequence Design Procedure Complex Count Sequence ... 101, 110 Design Procedure More Complex Count Sequence Design Procedure Complex Count Sequence Design Procedure Complex Count Sequence Design Procedure Complex Count Sequence Design Procedure. .. forms of sequential logic Inputs Combinational Logic State? ?Inputs Outputs State? ?Outputs Storage Elements Designing Finite State Machines ° Specify the problem with words ° (e.g Design a circuit... change ? ?Design the FSM using combinational logic and flip flops Vending Machine FSM State? ?Diagram State? ?Diagram Reuse Reuse states states whenever whenever possible possible Symbolic State Table