ĐIỆN tử VIỄN THÔNG 05b lab1 hierarchy v9 noan khotailieu

Building Hierarchy Lab Building Hierarchy Lab www.xilinx.com 1-877-XLX-CLAS 5b-2 Building Hierarchy Lab Introduction In this lab, you will write a complete RTL description for the entities MY_AND2 and MY_OR2 and build the circuit shown below (Figure 5b-1) in a structural VHDL description of the top-level entity AND_OR Objectives After completing this lab, you will be able to:  Write RTL descriptions for simple gates  Create a structural VHDL description for a simple circuit  Build hierarchy by using VHDL  Use the HDL editor in the ISE™ software Procedure Examine the circuit below (Figure 5b-1) In this lab, you will write a complete RTL description for the entities MY_AND2 and MY_OR2 and build the circuit in a structural VHDL description of the top-level entity AND_OR Note the signal names and that INP is a 4-bit bus INP(0) MY_AND2 INP(1) U0 SIG1 Top level : AND_OR MY_OR2 INP(2) MY_AND2 INP(3) U1 MY_AND2 SIG2 Z U2 MY_OR2 Figure 5b-1 AND_OR Structure and Underlying Components Building Hierarchy Lab www.xilinx.com 1-877-XLX-CLAS 5b-3 NOTE: Toolwire is the default platform for running labs Use R:\ for all directory references This lab comprises three primary steps: You will create an ISE™ software project; write the RTL descriptions; and, finally, check the syntax (analyze) and generate a schematic For each procedure within a primary step, there are general instructions (indicated by the symbol) These general instructions only provide a broad outline for performing the procedure Below these general instructions, you will find accompanying step-by-step directions and illustrated figures that provide more detail for performing the procedure If you feel confident about completing a procedure, you can skip the step-by-step directions and move on to the next general instruction Note: When using Toolwire to perform this lab, all software programs, files and projects will be located on the R:\ drive instead of C:\ Note: If you are unable to complete the lab at this time, you can download the lab files for this module from the Xilinx FTP site at ftp://ftp.xilinx.com/pub/documentation/education/lang11000-9-rev1-xlnx_lab_files.zip Creating a New Project Step For each procedure within a primary step, there are general instructions (indicated by the symbol) These general instructions only provide a broad outline for performing the procedure Below these general instructions, you will find accompanying step-by-step directions and illustrated figures that provide more detail for performing the procedure If you feel confident about completing a procedure, you can skip the step-by-step directions and move on to the next general instruction General Flow for this Lab: Step 1: Creating a New Project Step 2: Writing the RTL Descriptions Step 3: Performing a Syntax Check/ Generating a Schematic Create an ISE software project named lab1 in the R:\training\vhdl\labs directory  Select Start  Programs  Xilinx ISE 9.1i  Project Navigator to launch the Project Navigator  In the Project Navigator, select File  New Project  Browse to R:\training\vhdl\labs in the Project Location field Enter My_Class_Labs in the Project Name field Building Hierarchy Lab www.xilinx.com 1-877-XLX-CLAS 5b-4 Note: As you type, the Project Location field updates to show My_Class_Labs as the specified location Make certain not to browse below this level in the directory (Figure 5b-2) Figure 5b-2 Create New Project Dialog Box  Verify that HDL is selected from the Top-Level Source Type drop-down list  Click Next  Set the following parameters (Figure 5b-3)  Product Category: All  Family: Spartan3  Device: XC3S50  Package: PQ208  Speed Grade: -5  Synthesis Tool: XST (VHDL/Verilog)  Simulator: ISE Simulator (VHDL/Verilog) Building Hierarchy Lab www.xilinx.com 1-877-XLX-CLAS 5b-5 Figure 5b-3 Device Properties Dialog Box  Leave all other options at their default setting  Click Next, leaving all fields blank in the Create New Source File dialog box  Click Next, leaving all fields blank in the Add Existing Sources dialog box  Click Finish in the Summary dialog box to create the new project Writing the RTL Descriptions Step General Flow for this Lab: Step 1: Creating a New Project Step 2: Writing the RTL Descriptions Step 3: Performing a Syntax Check/ Generating a Schematic Write the VHDL code for the MY_AND2 entity  Select Project  New Source Building Hierarchy Lab www.xilinx.com 1-877-XLX-CLAS 5b-6  In the New Source dialog box, select VHDL Module, enter MY_AND2 in the File name field, and click Next to open the Define Module dialog box  Enter the port data for the intended module as shown in Figure 5b-4 Figure 5b-4 Define Module Dialog Box  When you are finished, click Next and click Finish The tool automatically creates the entity declaration based on the data that you entered Note: After you exit the wizard, you must make all subsequent edits in the HDL editor, including any necessary changes to items that were originally specified in the wizard  Use the and/or VHDL operators to describe the functionality of the And and Or gates; that is, C