DIGITAL LOGIC TESTING AND SIMULATION DIGITAL LOGIC TESTING AND SIMULATION SECOND EDITION Alexander Miczo A JOHN WILEY & SONS, INC., PUBLICATION Copyright 2003 by John Wiley & Sons, Inc All rights reserved Published by John Wiley & Sons, Inc., Hoboken, New Jersey Published simultaneously in Canada No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic, mechanical, photocopying, recording, scanning, or otherwise, except as permitted under Section 107 or 108 of the 1976 United States Copyright Act, without either the prior written permission of the Publisher, or authorization through payment of the appropriate per-copy fee to the Copyright Clearance Center, Inc., 222 Rosewood Drive, Danvers, MA 01923, 978-750-8400, fax 978-750-4470, or on the web at www.copyright.com Requests to the Publisher for permission should be addressed to the Permissions Department, John Wiley & Sons, Inc., 111 River Street, Hoboken, NJ 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or fax 317-572-4002 Wiley also publishes its books in a variety of electronic formats Some content that appears in print, however, may not be available in electronic format Library of Congress Cataloging-in-Publication Data: Miczo, Alexander Digital logic testing and simulation / Alexander Miczo—2nd ed p cm Rev ed of: Digital logic testing and simulation c1986 Includes bibliographical references and index ISBN 0-471-43995-9 (cloth) Digital electronics—Testing I Miczo, Alexander Digital logic testing and simulation II Title TK7868.D5M49 2003 621.3815′48—dc21 2003041100 Printed in the United States of America 10 CONTENTS Preface xvii Introduction 1.1 Introduction 1.2 Quality 1.3 The Test 1.4 The Design Process 1.5 Design Automation 1.6 Estimating Yield 11 1.7 Measuring Test Effectiveness 14 1.8 The Economics of Test 20 1.9 Case Studies 1.9.1 The Effectiveness of Fault Simulation 1.9.2 Evaluating Test Decisions 23 23 24 1.10 Summary 26 Problems 29 References 30 Simulation 33 2.1 Introduction 33 2.2 Background 33 2.3 The Simulation Hierarchy 36 2.4 The Logic Symbols 37 2.5 Sequential Circuit Behavior 39 2.6 The Compiled Simulator 2.6.1 Ternary Simulation 44 48 v vi CONTENTS 2.6.2 2.6.3 2.6.4 2.6.5 Sequential Circuit Simulation Timing Considerations Hazards Hazard Detection 48 50 50 52 2.7 Event-Driven Simulation 2.7.1 Zero-Delay Simulation 2.7.2 Unit-Delay Simulation 2.7.3 Nominal-Delay Simulation 54 56 58 59 2.8 Multiple-Valued Simulation 61 2.9 Implementing the Nominal-Delay Simulator 2.9.1 The Scheduler 2.9.2 The Descriptor Cell 2.9.3 Evaluation Techniques 2.9.4 Race Detection in Nominal-Delay Simulation 2.9.5 Min–Max Timing 64 64 67 70 71 72 2.10 Switch-Level Simulation 74 2.11 Binary Decision Diagrams 2.11.1 Introduction 2.11.2 The Reduce Operation 2.11.3 The Apply Operation 86 86 91 96 2.12 Cycle Simulation 101 2.13 Timing Verification 2.13.1 Path Enumeration 2.13.2 Block-Oriented Analysis 106 107 108 2.14 Summary 110 Problems 111 References 116 Fault Simulation 119 3.1 Introduction 119 3.2 Approaches to Testing 120 3.3 Analysis of a Faulted Circuit 3.3.1 Analysis at the Component Level 3.3.2 Gate-Level Symbols 3.3.3 Analysis at the Gate Level 122 122 124 124 CONTENTS vii 3.4 The Stuck-At Fault Model 3.4.1 The AND Gate Fault Model 3.4.2 The OR Gate Fault Model 3.4.3 The Inverter Fault Model 3.4.4 The Tri-State Fault Model 3.4.5 Fault Equivalence and Dominance 125 127 128 128 128 129 3.5 The Fault Simulator: An Overview 131 3.6 Parallel Fault Processing 3.6.1 Parallel Fault Simulation 3.6.2 Performance Enhancements 3.6.3 Parallel Pattern Single Fault Propagation 134 134 136 137 3.7 Concurrent Fault Simulation 3.7.1 An Example of Concurrent Simulation 3.7.2 The Concurrent Fault Simulation Algorithm 3.7.3 Concurrent Fault Simulation: Further Considerations 139 139 141 146 3.8 Delay Fault Simulation 147 3.9 Differential Fault Simulation 149 3.10 Deductive Fault Simulation 151 3.11 Statistical Fault Analysis 152 3.12 Fault Simulation Performance 155 3.13 Summary 157 Problems 159 References 162 Automatic Test Pattern Generation 165 4.1 Introduction 165 4.2 The Sensitized Path 4.2.1 The Sensitized Path: An Example 4.2.2 Analysis of the Sensitized Path Method 165 166 168 4.3 The D-Algorithm 4.3.1 The D-Algorithm: An Analysis 4.3.2 The Primitive D-Cubes of Failure 4.3.3 Propagation D-Cubes 4.3.4 Justification and Implication 4.3.5 The D-Intersection 170 171 174 177 179 180 viii CONTENTS 4.4 Testdetect 182 4.5 The Subscripted D-Algorithm 184 4.6 PODEM 188 4.7 FAN 193 4.8 Socrates 202 4.9 The Critical Path 205 4.10 Critical Path Tracing 208 4.11 Boolean Differences 210 4.12 Boolean Satisfiability 216 4.13 Using BDDs for ATPG 4.13.1 The BDD XOR Operation 4.13.2 Faulting the BDD Graph 219 219 220 4.14 Summary 224 Problems 226 References 230 Sequential Logic Test 233 5.1 Introduction 233 5.2 Test Problems Caused by Sequential Logic 5.2.1 The Effects of Memory 5.2.2 Timing Considerations 233 234 237 5.3 Sequential Test Methods 5.3.1 Seshu’s Heuristics 5.3.2 The Iterative Test Generator 5.3.3 The 9-Value ITG 5.3.4 The Critical Path 5.3.5 Extended Backtrace 5.3.6 Sequential Path Sensitization 239 239 241 246 249 250 252 5.4 Sequential Logic Test Complexity 5.4.1 Acyclic Sequential Circuits 5.4.2 The Balanced Acyclic Circuit 5.4.3 The General Sequential Circuit 259 260 262 264 5.5 Experiments with Sequential Machines 266 5.6 A Theoretical Limit on Sequential Testability 272 CONTENTS 5.7 Summary ix 277 Problems 278 References 280 Automatic Test Equipment 283 6.1 Introduction 283 6.2 Basic Tester Architectures 6.2.1 The Static Tester 6.2.2 The Dynamic Tester 284 284 286 6.3 The Standard Test Interface Language 288 6.4 Using the Tester 293 6.5 The Electron Beam Probe 299 6.6 Manufacturing Test 301 6.7 Developing a Board Test Strategy 304 6.8 The In-Circuit Tester 307 6.9 The PCB Tester 6.9.1 Emulating the Tester 6.9.2 The Reference Tester 6.9.3 Diagnostic Tools 310 311 312 313 6.10 The Test Plan 315 6.11 Visual Inspection 316 6.12 Test Cost 319 6.13 Summary 319 Problems 320 References 321 Developing a Test Strategy 323 7.1 Introduction 323 7.2 The Test Triad 323 7.3 Overview of the Design and Test Process 325 7.4 A Testbench 7.4.1 The Circuit Description 7.4.2 The Test Stimulus Description 327 327 330 .. .DIGITAL LOGIC TESTING AND SIMULATION DIGITAL LOGIC TESTING AND SIMULATION SECOND EDITION Alexander Miczo A JOHN WILEY & SONS, INC., PUBLICATION Copyright 2003 by John Wiley & Sons,... Miczo, Alexander Digital logic testing and simulation / Alexander Miczo 2nd ed p cm Rev ed of: Digital logic testing and simulation c1986 Includes bibliographical references and index ISBN 0-471-43995-9... Problems related to the testing of digital components and Digital Logic Testing and Simulation, Second Edition, by Alexander Miczo ISBN 0-471-43995-9 Copyright © 2003 John Wiley & Sons, Inc INTRODUCTION