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SEQUENTIAL TEST METHODS 257 conflict. For purposes of illustration we select Y σ 2 . It requires a D from input V and a 0 from input U. Table 5.6 is used to justify the D. The column with header D reveals that a D occurs at the input to Y if V is true while at rest, A, or if it is presently true but toggles false, T, at the next time frame. Since no cubes exist in Table 5.7 with a T on the out- put of V, we check entries from Table 5.6 with A and find, by going across to the left, that they result from intersection with either an A or t on the output of V. From the D-cubes for V in Table 5.7, V σ 4 is selected. Finally, in similar fashion, a 0 is justified on U by means of cube U α . Four cubes have now been identified that extend a sensitized path back from out- put Z to primary inputs and other elements. Before continuing, we point out that the sensitized path extends through both logic and time, since the cubes impose switch- ing conditions as well as logic values. As a result, intersections are more complex and require attention to more detail than is the case with the D-algorithm. Some cubes must be intersected in the same time frame, and others, linked by synchronous switching conditions, are used to satisfy conditions required in the preceding time frame. Consider the first D-cube selected, Z σ 1 . It creates a t on the output of Z by assign- ing a 1 and a d to the inputs of the AND gate. The 1 is satisfied by assigning a 1 to input F. The d, which is an asynchronous D, must be justified in the present time frame. This is accomplished by intersecting Z σ 1 with the second cube previously selected, Y σ 2 . Performing the intersection according to the rules in Table 5.6, we obtain the following: The resultant cube applies a 0 to the Set input of flip-flop Y. The fourth cube pre- viously selected, U α , which was chosen to justify the 0 on the Set input, is asyn- chronously coupled to Y via the unclocked Set input. Therefore, according to the intersection rules, it must be intersected with the previous result. The remaining cube, V σ 4 , was selected to justify a D on the input to Y. Since the input is synchronized to the clock, the cube V σ 4 becomes part of the preceding time frame. Values on Z, U, V, and Y for this resultant cube are interpreted by using the legends at the bottom of Table 5.6. Super blocks Z, U and Y have both a final value t XX d X XX X X 1 Z σ 1 X0Dt XXXX1/0XY σ 2 t 0Dt XXXX1/01 t 0Dt X X X X 1/0 1 XA XX0 0 X X X X U α t A Dt 0 0 X X 1/0 1 258 SEQUENTIAL LOGIC TEST and a switching action specified. During an exercising sequence the t denotes a transition on the outputs of Z and Y from a present state of 0 to a final state of 1. The A on U denotes a super flip-flop that is false at rest; that is, its final value is false and, furthermore, it did not change. Therefore, the Set input to Y is inactive. Super flip- flop V has a D, which is an input value; therefore no final value is specified for that super flip-flop. The interpretation, then, of the resultant cube is that there is an output of 1, 0, X, 1 at time n + 1 from the four super blocks. At time n the circuit requires values 0, 0, 1, 0 on the outputs of the super blocks and values A, B, C, D, E, F = (0, 0, X, X, 1/0, 1) on the primary inputs. Note that the clock value is spec- ified as 1/0 and is regarded as a single stimulus, although in fact it requires two time images. The values (Z, U, V, Y) = (0, 0, 1, 0) required on the super blocks at time n must now be justified. The original third cube, V σ 4 , which was selected to justify a D at the input to V, puts a t on the output of V and requires a 0 on the input driven by U. Its combinational logic inputs require a 0 on input C and a D on the input from super flip-flop Y. The t represents a true final state on V and therefore satisfies the require- ment imposed by the previously created pattern. However, we still need 0s on the other super flip-flops. We must justify these values without conflicting with values of the cube V σ 4 . There is already an apparent conflict. The cube requires a D on Y, and the pre- viously created cube requires a 0 on Y. However, the D is an input to the super flip-flop at time n − 1 as specified by the cube V σ 4 . The 0 is an output require- ment at time n and the cube V σ 4 specifies that flip-flop V is to perform a toggle. The apparent problem is caused by the fact that a loop exists. We attempt to jus- tify the 0 required on U. The cube U ρ will justify the 0. We then select Z ρ 1 to get a 0 on Z, and we select Y ρ to get a 0 on Y. The intersection of these cubes yields the following: All columns except column 4, corresponding to super flip-flop Y, follow directly from the intersection table. As mentioned, the fourth column requires a d output from Y and a D input. In addition, the cube Y σ 2 requires a 1/0 toggle. Therefore, we intersect a D and t to get T and then intersect T with d to again get a T. The exercising sequence is now complete. The values t, A, T, T satisfy the require- ments for 0, 0, 1, 0 that we set out to obtain, but they in turn impose initial conditions of 1, 0, 0, 1. We therefore must create an initialization sequence by continuing to justify backward in time until we eventually reach a point in which tXXdXXXX X 1 Z ρ 1 X0Dt X X X X 1/0 X Y σ 2 XtXX0dXXX X U ρ X0 tD X X 0 X 1/0 X V σ 4 tAT T 0 d 0 X 1/0 1 SEQUENTIAL LOGIC TEST COMPLEXITY 259 all of the super blocks have X states. To satisfy the assignments 1, 0, 0, 1, we intersect the following: During creation of the initialization sequence, we are aided by an additional observation. The t, which implied a true final state and a false start state while build- ing the exercising sequence, still implies a true final state but implies an x state while constructing the initializing sequence. Therefore the values t, A, T, t on the super blocks satisfy the 1,0,0,1 requirement and also imply a previous state of X, 0, 1, X on the super block outputs. Thus, two of the super blocks can be ignored. To get the previous state in which U = 0 and V = 1, we intersect: Again, the t satisfies the requirement for V = 1 and specifies a previous don’t care state. Since we are constructing an initializing sequence at this point, rather than an exercising sequence, the D is ignored; that is, it is treated as a logic 1. A 0 is now required on the output of super flip-flop U. The D-cube U ρ is used, which puts a t on the output of the flip-flop, hence a 0 preceded by a don’t care state. The inputs for that cube are 0 and d. The d is again treated as a 1 because this is the initializing sequence. The task is done; we now go back and reconstruct the entire sequence. We get: 5.4 SEQUENTIAL LOGIC TEST COMPLEXITY A general solution to the test problem for sequential logic has proven elusive. Recall that several algorithms exist that can find a test for any fault in a combinational circuit, t XX dXXXX X 1Z σ 1 XtXX0dXXXXU ρ X0 t XXX1D1/0 X V ρ 1 X0D tX X X X 1/0 X Y σ 2 t A Tt0d1D1/0 1 XAXX0 0 XX X X U α X0 t X X X 1 D 1/0 X V σ 2 XA t X 0 0 1 D 1/0 X nZUVYABCDEF 1 XXXX 0 1 XX X X 2 X0XX 00111/0X 3 X01X 01101/01 4 1001 010X1/01 5 0010 00XX1/01 6 10X1 260 SEQUENTIAL LOGIC TEST if a test exists, given only a list of the logic elements used in the circuit and their inter- connections. No comparable theoretical basis for sequential circuits exists under the same set of conditions. 5.4.1 Acyclic Sequential Circuits The analysis of sequential circuits begins with the circuit of Figure 5.8. Although it is sequential, it is loop-free, or acyclic. There is no feedback, apart from that which exists inside the flip-flops. In fact, the memory devices need not be flip-flops, the circuit could be implemented with delays or buffers to obtain the required delay. The circuit would not behave exactly the same as a circuit with clocked flip-flops, since flip-flops can hold a value for an indefinite period if the clock is halted, whereas signals propagate unimpeded through delay lines. However, with delay lines equalling the clock period, it would be impossible for an observer strobing the outputs to determine if the circuit were implemented with delay lines or clocked flip-flops. If the circuit is made up of delay lines, then for many of the faults the circuit could be considered to be purely combinational logic. The signal at the output fluc- tuates for a while but eventually stabilizes and remains constant as long as the inputs are held constant. If a tester connected to the output samples the response at a suffi- ciently late time relative to the total propagation time through the circuit, the delay lines would have no more effect than wires with zero delay and could therefore be completely ignored. If the delays are flip-flops, how much does the analysis change? Suppose the goal is to create a test for an SA1 fault on the top input to gate B 4 . A test for the SA1 fault can be obtained by setting I 1 = 0, FF 2 = X and FF 3 = 1. If FF 4 represents time image n, then a 1 is required on primary input I 6 in time image n − 1 in order to justify the 1 on FF 3 in time image n. Propagation through FF 5 in time image n + 1 is achieved by requiring FF 7 = 1. That can be justified by setting I 5 = 1 in time image n and I 4 = 1 in time image n − 1. The entire sequence becomes Figure 5.8 An acyclic sequential circuit. FF 5 FF 4 B 5 I 6 B 4 B 3 FF 2 FF 3 FF 7 B 2 FF 1 B 6 B 1 FF 6 I 1 I 2 I 3 I 4 I 5 Out SEQUENTIAL LOGIC TEST COMPLEXITY 261 Figure 5.9 The acyclic rank-ordered circuit. To summarize, a fault is sensitized in time image n, and assignments are justified backward in time to image n − 1 and are propagated forward in time to image n + 1. The result finally appears at an observable output in time image n + 2. Of interest here is the fact that the test pattern could almost as easily have been generated by a combi- national ATPG. The circuit has been redrawn as an S-graph in Figure 5.9, where the nodes in the graph are the original flip-flops. The logic gates have been left out but the connections between the nodes represent paths through the original combinational logic. The nodes have been rank-ordered in time, with the time images indicated at the top of Figure 5.9. Because FF 7 fans out, it appears twice, as does its source FF 6 . In order to test the same fault in the redrawn circuit, the flip-flops can be ignored while computing input stimuli and the rank-ordered circuit can be used to determine the time images in which stimuli must occur. For test purposes, the complexity of this circuit is comparable to that of a combinational circuit. Since the number of test patterns for a combinational circuit with n inputs is upper bounded by 2 n , the num- ber of test patterns for this pseudo-combinational circuit is upper-bounded by k · 2 n , where k is circuit depth; that is, k is the maximum number of flip-flops in any path between any input and any output. Example A test will be created for the bottom input of B 4 SA1. The input stimuli are Time I 1 I 2 I 3 I 4 I 5 I 6 Out n − 1 XXX1X1 X n 0 XXX1X X n + 1 X X X X X X X n + 2 D I 1 I 2 I 3 I 4 I 5 I 6 1 1 1 1/1 1/1 0 FF 5 FF 4 I 6 FF 2 FF 3 FF 7 FF 6 I 4 I 5 I 5 I 4 FF 6 I 3 I 2 I 1 Out n n + 1 n + 2 n + 3 n + 4 n + 5 FF 1 FF 7 262 SEQUENTIAL LOGIC TEST The double assignments for I 4 and I 5 represent values at different times due to fanout. If destination flip-flops exist in different time images, we can permit what would nor- mally be conflicting assignments. If the fanout is to two or more destination flip-flops, all of which exist in the same time image, then the assignments must not conflict. From the rank-ordered circuit it is evident that the values must occur in the following time images: The previously generated test sequence can be shifted three units forward in time and merged with the second test sequence to give 5.4.2 The Balanced Acyclic Circuit The concept of using a combinational ATPG for the circuit of Figure 5.8 breaks down for some of the faults. For example, an SA0 on the top input to B 6 , driven by FF 6 , cannot be tested in this way because the fault requires a 0 for sensitization and a 1 for propagation. The circuit is said to be unbalanced because there are two fanout paths from FF 7 to the output and there are a different number of flip-flops in each of the fanout paths. When every path between any two nodes in an acyclic sequential circuit has the same number of flip-flops, it is called a balanced acyclic sequential circuit. The sequential depth d max of the balanced circuit is the number of nodes or vertices on the longest path in the S-graph. Given a balanced circuit, the sequential elements in Out I 1 I 2 I 3 I 4 I 5 I 6 Time XXXX1XX n XXXXX1Xn + 1 XXX1XXXn + 2 XX1X1X0n + 3 X1XXX1Xn + 4 XXXXXXXn + 5 D n + 6 Out I 1 I 2 I 3 I 4 I 5 I 6 Time X XXX1XX n X XXXX 1 X n + 1 X XX1 1X 1 n + 2 X 01X11 1 n + 3 X 1XXX1 X n + 4 D XXXXXX n + 5 D n + 6  SEQUENTIAL LOGIC TEST COMPLEXITY 263 Figure 5.10 A strongly balanced circuit. the model can be replaced by wires or buffers. Vectors can then be generated for faults in the resulting circuit model using a combinational ATPG. The vector thus generated is applied to the circuit for a duration of d max + 1 clock cycles. 8 An internally balanced acyclic sequential circuit is one in which all node pairs except those involving primary inputs are balanced. 9 Like the balanced sequential circuit, the internally balanced circuit can be converted to combinational form by replacing all flip-flops with wires or buffers. However, one additional modification to the circuit model is required: The primary inputs that are unbalanced are split and represented by additional primary inputs so that the resulting circuit is bal- anced. Then, the combinational ATPG can be used to create a test pattern. Each test pattern is replicated d max + 1 times. The logic bits on the replicated counterpart I j ' to the original input I j must be inserted into the bitstream for input I j at the appropriate time. Another distinction can be made with respect to balanced circuits. A strongly balanced acyclic circuit is balanced and, in addition, all paths from any given node in the circuit to the primary inputs driving its cone have the same sequential depth. 10 This is illustrated in Figure 5.10. A backtrace from Out to any primary input encounters three flip-flops. For test purposes, the model can be altered such that the flip-flops are converted to buffers. Then, test vectors for individual faults can be generated by a combinational ATPG. These are then stacked and clocked through the actual circuit on successive clock periods. The last vector, applied to the inputs at time n, will cause a response at Out during time n + 3. A hierarchy of circuit types, based on sequential constraints, is represented in Figure 5.11 (combinational circuits are most constrained). A general sequential circuit can be converted to acyclic sequential by means of scan flip-flops (cf. Chapter 8). The flip-flops to be scanned can be chosen using a variant of the loop- cutting algorithm described in Section 5.3.2. Given an acyclic circuit, it has been shown that a balanced model of the circuit can be created for ATPG purposes. Each FF 8 FF 6 B 5 I 4 B 4 B 2 FF 2 FF 3 FF 7 B 1 FF 1 B 3 FF 4 I 1 I 2 I 3 I 5 I 6 FF 5 Out 264 SEQUENTIAL LOGIC TEST Figure 5.11 Classification based on sequential constraints. vector created by the combinational ATPG is then transformed into a test sequence for the actual circuit. 11 It is reported that this approach reduces the ATPG time by an order of magnitude while producing vector lengths comparable to those obtained by sequential ATPGs. 5.4.3 The General Sequential Circuit Consider what happens when we make one alteration to the circuit in Figure 5.8. Input I 5 is eliminated and a connection is added from the output of B 5 to the input of B 6 . With this one slight change the entire nature of the problem has changed and the complexity of the problem that we are trying to solve has been compounded by orders of magnitude. In the original circuit the output was never dependent on inputs beyond six time frames. Furthermore, no flip-flop was ever dependent on a previous state generated in part by that same flip-flop. That has changed. The four flip-flops FF 1 , FF 2 , FF 4 , and FF 7 constitute a state machine of 16 states in which the present state may be dependent on inputs that occurred at any arbitrary time in the past. This can be better illustrated with the state transition graph of Figure 5.12. If we start in state S 1 the sequence 1011111 takes Figure 5.12 State transition graph. Sequential Acyclic Sequential Internally Balanced Balanced Strongly Balanced Combinational Most constrained Least constrained S 1 S 7 S 5 S 6 S 4 S 2 S 8 S 3 0/0 1/0 0/0 1/0 1/0 0/00/0 1/1 1/0 1/1 0/0 0/0 0/1 1/1 1/1 0/0 SEQUENTIAL LOGIC TEST COMPLEXITY 265 us to S 2 {S 7 , S 8 , S 5 , S 6 }*, where the braces and asterisk denote an arbitrary number of repetitions of the four states in braces. From the almost identical sequence 11011111 , we get the state sequence S 2 , S 3 {S 3 ,S 4 ,S 1 ,S 2 }*. The corresponding output sequences are 0,0{0,0,0,1}* and 0,1,0{1,1,0,1}*, a significant difference in output response that will continue as long as the input consists of a string of 1s. In a circuit with no feedback external to the flip-flops the output sequences will coincide within k time images where k again represents the depth of the circuit. How much effect does that feedback line have on the testability of the circuit? We will compute an upper bound on the number of test patterns required to test a state machine in which the present state is dependent on an input sequence of indetermi- nate length—that is, one in which present state of the memory cells is functionally dependent upon a previous state of those same memory cells. Given a state machine with n inputs and M states, 2 m−1 < M < 2 m , and its corre- sponding state table with M rows, one for each state, and 2 n columns, one for each input combination, there could be as many as 2 n unique transitions out of each state. Hence, there could be as many as M · 2 n , or approximately 2 m+n , transitions that must be verified. Given that we are presently in state S i , and we want to verify a transition from state S j to state S k , it may require M − 1 transitions to get from S i to S j before we can even attempt to verify the transition S j → S k . Thus, the number of test vectors required to test the state machine is upper bounded by 2 2m+n , and that assumes we can observe the present state without requiring any further state transitions. The argument was derived from a state table, but is there a physical realization requiring such a large number of tests? A realization can, in fact, be constructed directly from the state table. The circuit is implemented with m flip-flops, the out- puts of which are used to control m multiplexers, one for each flip-flop. Each mul- tiplexer has M inputs, one for each row of the state table. Each multiplexer input is connected to the output of another multiplexer that has 2 n inputs, one correspond- ing to each column of the state table. The inputs to this previous bank of multi- plexers are fixed at 1 and 0 and are binary m-tuples corresponding to the state assignments and the next states in the state table. In effecting state transitions, the multiplexers connected directly to the flip-flops select the row of the state table and the preceding set of multiplexers, under control of the input signal, select the column of the state table, thus the next state is selected by this configuration of multiplexers. In this implementation M · 2 n m-tuples must be verified, one for each entry in the state table. From the structure it can be seen that checking a given path could require as many as M − 1 transitions of the state machine to get the correct selection on the first bank of multiplexers. Consequently, the number of test patterns required to test this implementation is upper bounded by 2 2m+n . This is not a practical way to design a state machine, but it is necessary to consider worst-case examples when establishing bounds. Of more significance, the implementation serves to illustrate the dramatic change in the nature of the problem caused by the presence of feed- back lines. 266 SEQUENTIAL LOGIC TEST Figure 5.13 Canonical implementation of state table. Example Consider the machine specified by the following state table and flip-flop state assignments: This machine can be implemented in the canonical form of Figure 5.13.  5.5 EXPERIMENTS WITH SEQUENTIAL MACHINES Early efforts at testing state machines consisted of experiments aimed at determin- ing the properties or behavior of a state machine from its state table. 12 Such experi- ments consist of applying sequences of inputs to the machine and observing the output response. The input sequences are derived from analysis of the state table and may or may not also be conditional upon observation of the machine’s response to previous inputs. Sequences in which the next input is selected using both the state table and the machine’s response to previous inputs are called adaptive experiments. I 01 Q 1 Q 1 S 0 S 0 S 2 S 2 00 S 1 S 3 S 2 S 1 01 S 2 S 1 S 0 S 2 10 S 3 S 2 S 3 S 3 11 DQ 1 0 1 1 1 0 0 1 1 AB AB D Q 0 0 0 1 0 1 0 0 1 MUX MUX I Clock [...]... architectures and test strategies have evolved in order to locate defects in ICs and PCBs and provide the highest possible quality of delivered goods at the lowest possible price.This chapter provides a very brief overview of some of the more important highlights and concepts involved in applying test stimuli to digital circuits and monitoring their response Space does not permit a Digital Logic Testing and Simulation, ... D4 + D5 + D6 + D7’; OUTBUS ‘Q0 + Q1 + Q2 + Q3 + Q4 + Q5 + Q6 + Q7’; ALL ‘CLK + CLR + OE + INBUS + OUTBUS’; } Spec timingspec { Category prop_time { tplh { Min ‘2.00ns’; Typ ‘3.00ns’; Max ‘4.00ns’; } tphl { Min ‘2.00ns’; Typ ‘3.00ns’; Max ‘4.00ns’; } tpzl { Min 5. 25ns’; Typ ‘6.00ns’; Max ‘7.00ns’; } tpzh { Min ‘4 .50 ns’; Typ 5. 50ns’; Max ‘6 .50 ns’; } tplz { Min ‘3.45ns’; Typ ‘4.20ns’; Max 5. 75ns’;... others Indicate unresolvable conflicts with a dash 5. 6 Redesign the circuit in Figure 5. 1 by replacing the DFF with the gated latch of Figure 2.4(b) Cut all loops and use the 9-value ITG to find a test for the fault indicated in Figure 5. 1 5. 7 Create a table for the exclusive-OR similar to Tables 5. 2 and 5. 3 5. 8 Use the critical path method of Section 5. 3.4 to find a test for a SA1 fault on the Data input... SA1 fault 5. 15 Complete the checking sequence for the example that was started in Section 5. 5 5. 16 Find a synchronizing sequence for the following state machine: S0 S1 S2 S3 S4 S5 S6 S7 0 S0 S1 S2 S3 S0 S1 S0 S0 1 S4 S5 S6 S7 S2 S3 S0 S1 5. 17 Describe an algorithm for finding a preset distinguishing sequence 5. 18 The machine (a) below has synchronizing sequence 101 If it starts in state C, and the machine... of ±0.1% and measures 5. 0 V, the true voltage may lie anywhere between 4. 95 V and 5. 05 V Resolution refers to the degree to which a change can be observed Referring again to the voltmeter, if it is a digital voltmeter, its resolution is expressed as a number of bits However, the last few bits may not be meaningful if measurements are being taken in a noisy environment If the noise is random and there... synchronizing sequence are {S0, S1} → {S2, S3} → {S0, S2} → {S0} 276 SEQUENTIAL LOGIC TEST D Q1 Q1 Data D Q0 Clock Figure 5. 22 Machine with length 4 synchronizing sequence If we assign flip-flop Q1 = 0 for states S0 and S1, Q1 = 1 for states S2 and S3, and Q0 = 0 for states S0 and S2, then simulation of the machine, as implemented in Figure 5. 22, causes the machine to go into a completely specified state at the... states, hence simulation of any binary input value must leave both output bits, Q1 and Q0, uncertain; that is, both Q1 and Q0 could possibly be in a 0 state or a 1 state, hence, both Q1 and Q0 remain in the X state Data Data 0 1 0 1 S0 S1 S1 S0 S1 S1 S1 S3 S2 S1 S2 S1 S3 S2 S3 S2 S1 S3 S0 S3 S0 S3 S3 S0 Figure 5. 20 State tables 274 SEQUENTIAL LOGIC TEST Data D Q1 Q1 D Q0 Clock Q0 Figure 5. 21 Implementation... work PROBLEMS 279 5. 9 Use EBT to find a test for the indicated fault in the circuit of Figure 5. 6 For the state machine, use the circuit in Figure 5. 12 Identify the TP, and show your work 5. 10 Substitute a D flip-flop for the JK flip-flop in the circuit of Figure 5. 7 Assume the existence of a set input Duplicate the calculations for the path exercised in the text, using this D flip-flop 5. 11 Show that a SA1... both of them are testable The state tables for the machines of Figure 5. 19(a) and 5. 19(b) are shown in Figures 5. 20(a) and 5. 20(b), respectively For machine A the synchronizing sequence I = (0, 1, 0, 1, 0) will put the machine in state S1 For machine B the synchronizing sequence I = (0, 0) will put the machine in state S3 The length and nature of the synchronizing sequence plays a key role in determining... Trans Comput., Vol C- 25, No 6, June 1976, pp 630–636 5 Marlett, Ralph, EBT: A Comprehensive Test Generation Technique for Highly Sequential Circuits, Proc 15th Des Autom Conf., June 1978, pp 332–339 6 Kriz, T A., A Path Sensitizing Algorithm for Diagnosis of Binary Sequential Logic, Proc 9th Symposium on Switching and Automata Theory, 1970, pp 250 – 259 7 Kriz, T A., Machine Identification Concepts of Path . D I 1 I 2 I 3 I 4 I 5 I 6 1 1 1 1/1 1/1 0 FF 5 FF 4 I 6 FF 2 FF 3 FF 7 FF 6 I 4 I 5 I 5 I 4 FF 6 I 3 I 2 I 1 Out n n + 1 n + 2 n + 3 n + 4 n + 5 FF 1 FF 7 262 SEQUENTIAL LOGIC TEST The double. 1–= 2 i m i   ⋅ 276 SEQUENTIAL LOGIC TEST Figure 5. 22 Machine with length 4 synchronizing sequence. If we assign flip-flop Q 1 = 0 for states S 0 and S 1 , Q 1 = 1 for states S 2 and S 3 , and Q 0 = 0 for states S 0 and. ATPGs. 5. 4.3 The General Sequential Circuit Consider what happens when we make one alteration to the circuit in Figure 5. 8. Input I 5 is eliminated and a connection is added from the output of B 5