Digital logic testing and simulation phần 1 pdf

[...]... Codes 10 .7 .1 Vector Spaces 10 .7.2 The Hamming Codes 10 .7.3 ECC Implementation 10 .7.4 Reliability Improvements 10 .7.5 Iterated Codes 537 538 540 542 543 545 10 .8 Summary 546 Problems 547 References 549 11 IDDQ 5 51 11. 1 Introduction 5 51 11. 2 Background 5 51 11. 3 Selecting Vectors 11 .3 .1 Toggle Count 11 .3.2 The Quietest Method 553 553 554 11 .4 Choosing a Threshold 556 11 .5 Measuring Current 557 11 .6 IDDQ... References 510 10 Memory Test 513 10 .1 Introduction 513 CONTENTS xiii 10 .2 Semiconductor Memory Organization 514 10 .3 Memory Test Patterns 517 10 .4 Memory Faults 5 21 10.5 Memory Self-Test 10 .5 .1 A GALPAT Implementation 10 .5.2 The 9N and 13 N Algorithms 10 .5.3 Self-Test for BIST 10 .5.4 Parallel Test for Memories 10 .5.5 Weak Read–Write 524 525 529 5 31 5 31 533 10 .6 Repairable Memories 535 10 .7 Error Correcting... 559 11 .7 Problems with Large Circuits 562 11 .8 Summary 564 Problems 565 References 565 xiv CONTENTS 12 Behavioral Test and Verification 567 12 .1 Introduction 567 12 .2 Design Verification: An Overview 568 12 .3 Simulation 12 .3 .1 Performance Enhancements 12 .3.2 HDL Extensions and C++ 12 .3.3 Co-design and Co-verification 570 570 572 573 12 .4 Measuring Simulation Thoroughness 12 .4 .1 Coverage Evaluation 12 .4.2... DEPOT 12 .8.3 The Fault Simulator 12 .8.4 Building Goal Trees 12 .8.5 Sequential Conflicts in Goal Trees 12 .8.6 Goal Processing for a Microprocessor 12 .8.7 Bidirectional Goal Search 12 .8.8 Constraint Propagation 12 .8.9 Pitfalls When Building Goal Trees 12 .8 .10 MaxGoal Versus MinGoal 12 .8 .11 Functional Walk 12 .8 .12 Learn Mode 12 .8 .13 DFT in TDX 607 607 614 616 617 618 620 624 625 626 627 629 630 633 12 .9... Diagnostic Tools 310 311 312 313 6 .10 The Test Plan 6 .11 Visual Inspection 316 6 .12 Test Cost 319 6 .13 Summary 319 Problems 320 References 7 315 3 21 Developing a Test Strategy 323 7 .1 Introduction 323 7.2 The Test Triad 323 7.3 Overview of the Design and Test Process 325 7.4 A Testbench 7.4 .1 The Circuit Description 7.4.2 The Test Stimulus Description 327 327 330 x CONTENTS 7.5 Fault Modeling 7.5 .1 Checkpoint... 578 12 .5 Random Stimulus Generation 5 81 12.6 The Behavioral ATPG 12 .6 .1 Overview 12 .6.2 The RTL Circuit Image 12 .6.3 The Library of Parameterized Modules 12 .6.4 Some Basic Behavioral Processing Algorithms 587 587 588 589 593 12 .7 The Sequential Circuit Test Search System (SCIRTSS) 12 .7 .1 A State Traversal Problem 12 .7.2 The Petri Net 597 597 602 12 .8 The Test Design Expert 12 .8 .1 An Overview of TDX 12 .8.2... it relates to digital products, we shift our attention to the subject of testing The test will first be defined in a broad, generic sense Then we put the subject of digital logic testing into perspective by briefly examining the overall design process Problems related to the testing of digital components and Digital Logic Testing and Simulation, Second Edition, by Alexander Miczo ISBN 0-4 71- 43995-9 Copyright... Design Verification 12 .9 .1 Formal Verification 12 .9.2 Theorem Proving 635 636 636 CONTENTS 12 .9.3 Equivalence Checking 12 .9.4 Model Checking 12 .9.5 Symbolic Simulation xv 638 640 648 12 .10 Summary 650 Problems 652 References 653 Index 657 PREFACE About one and a half decades ago the state of the art in DRAMs was 64K bytes, a typical personal computer (PC) was implemented with about 60 to 10 0 dual in-line... Pattern Compaction 7.9.7 Test Counting 368 368 369 369 3 71 372 372 374 7 .10 Miscellaneous Considerations 7 .10 .1 The ATPG/Fault Simulator Link 378 378 CONTENTS 7 .10 .2 ATPG User Controls 7 .10 .3 Fault-List Management xi 380 3 81 7 .11 Summary Problems 383 References 385 Design-For-Testability 387 8 .1 Introduction 387 8.2 Ad Hoc Design-for-Testability Rules 8.2 .1 Some Testability Problems 8.2.2 Some Ad Hoc Solutions... graphical interfaces, the input medium for digital circuits has migrated from graphics (schematic editors) to text Topics include event-driven simulation and selective trace Delay models for simulation include 0-delay, unit delay, and nominal delay Switch-level simulation xx PREFACE represents one end of the simulation spectrum Behavioral simulation and cycle simulation represent the other end Binary . Cycle Simulation 10 1 2 .13 Timing Verification 10 6 2 .13 .1 Path Enumeration 10 7 2 .13 .2 Block-Oriented Analysis 10 8 2 .14 Summary 11 0 Problems 11 1 References 11 6 3 Fault Simulation 11 9 3 .1 Introduction. 549 11 I DDQ 5 51 11 .1 Introduction 5 51 11. 2 Background 5 51 11. 3 Selecting Vectors 553 11 .3 .1 Toggle Count 553 11 .3.2 The Quietest Method 554 11 .4 Choosing a Threshold 556 11 .5 Measuring. Simulation 14 7 3.9 Differential Fault Simulation 14 9 3 .10 Deductive Fault Simulation 15 1 3 .11 Statistical Fault Analysis 15 2 3 .12 Fault Simulation Performance 15 5 3 .13 Summary 15 7 Problems 15 9 References