Chapter 11_Memory Devices

1 Lecture: DIGITAL SYSTEMS Nguyen Thanh Hai, PhD Chapter 11: Memory Devices University of Technical Education Faculty of Electrical & Electronic Engineering University of Technical Education Faculty of Electrical & Electronic Engineering Memory Devices 2 Nguyen Thanh Hai, PhD 11.1 Introduction 11.2 ROM Architecture 11.3 Flash Memory 11.4 RAM Architecture 11.5 Cache Memory University of Technical Education Faculty of Electrical & Electronic Engineering Memory Devices 3 Nguyen Thanh Hai, PhD 11.1 Introduction Types of memory devices University of Technical Education Faculty of Electrical & Electronic Engineering Memory Devices 4 Nguyen Thanh Hai, PhD 0 A 1 A 2 A 3 A 4 A 3 I 2 I 1 I 0 I WR/ ME 432 × Memory outputs Data 3 O 2 O 1 O 0 O MSB inputs Address inputs Data command Read/write enable Memory 0 1 1 0 1 0 0 1 1 1 1 1 1 0 0 0 0 0 0 1 0 0 0 0 . . . . . . . . . . . . 1 1 0 1 1 1 0 1 0 1 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 . . . . . . . . . . . . . . . 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 cellsMemory Addresses 3 D 2 D 1 D 0 D 3 A 2 A 1 A 0 A 4 A University of Technical Education Faculty of Electrical & Electronic Engineering Memory Devices 5 Nguyen Thanh Hai, PhD 0 1 1 0 1 0 0 1 1 1 1 1 0 1 0 0 0 0 0 1 0 0 0 0 . . . . . . . . . . . . 1 1 0 1 1 1 0 1 0 1 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 . . . . . . . . . . . . . . . 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 Addresses 0 1 1 0 1 0 0 1 1 1 1 1 1 0 0 0 0 0 0 1 0 0 0 0 . . . . . . . . . . . . 1 1 0 1 1 1 0 1 0 1 1 1 0100 1101 WRITING the data word 0100 into memory location 00011 READING the data word 1101 from memory location 11110 3 I 2 I 1 I 0 I 3 O 2 O 1 O 0 O 3 A 2 A 1 A 0 A 4 A Data input Data output University of Technical Education Faculty of Electrical & Electronic Engineering Memory Devices 6 Nguyen Thanh Hai, PhD bus Address CPU Memory IC Memory IC bus Data bus Control Three groups of lines connect the main memory ICs to the CPU CPU: Central Processing Unit University of Technical Education Faculty of Electrical & Electronic Engineering Memory Devices 7 Nguyen Thanh Hai, PhD 11.2 ROM (Read Only Memory) ROM block diagram Address decoder Controller Registers R/W Output buffer D 0 D 7 CE 1 CE 2 CE 3 Control bus Data bus A 9 A 0 Address bus University of Technical Education Faculty of Electrical & Electronic Engineering Memory Devices 8 Nguyen Thanh Hai, PhD 11.2 ROM 0 A 1 A 2 A 3 A 816 × ROM select) (Chip CS ∇ inputs Address input Control 3 D 4 D 5 D 6 D 7 D 0 D 1 D 2 D tristate = ∇ - 1 register = 8 bits = 1 byte - 4 addresses for 16 register locations University of Technical Education Faculty of Electrical & Electronic Engineering Memory Devices 9 Nguyen Thanh Hai, PhD Address Word Data Address Data Word University of Technical Education Faculty of Electrical & Electronic Engineering Memory Devices 10 Nguyen Thanh Hai, PhD 11.2 ROM A 3 A 2 A 1 A 0 =0001 Memory cell R 1 R 1 contains 8 data bits (D 0 -D 7 ) University of Technical Education Faculty of Electrical & Electronic Engineering Memory Devices 11 Nguyen Thanh Hai, PhD University of Technical Education Faculty of Electrical & Electronic Engineering Memory Devices 12 Nguyen Thanh Hai, PhD Example 11.5 University of Technical Education Faculty of Electrical & Electronic Engineering Memory Devices 13 Nguyen Thanh Hai, PhD Example 11.6 University of Technical Education Faculty of Electrical & Electronic Engineering Memory Devices 14 Nguyen Thanh Hai, PhD Example 11.7 University of Technical Education Faculty of Electrical & Electronic Engineering Memory Devices 15 Nguyen Thanh Hai, PhD 11.2.1 EPROM (Erasable Programmable ROM) University of Technical Education Faculty of Electrical & Electronic Engineering Memory Devices 16 Nguyen Thanh Hai, PhD - EPROM can be used to program, erase or reprogram as often as desired. - To erase an EPROM cell programmed, we can use ultraviolet (UV) light through a window of the EPROM as show in Figure above. -After erasing, EPROM can be reprogrammed and programming can be done using a circuit. University of Technical Education Faculty of Electrical & Electronic Engineering Memory Devices 17 Nguyen Thanh Hai, PhD 11.2.2 EEPROM (Electrically Erasable PROM) EEPROM AT28C64B, 64K = 8K x 8 bits University of Technical Education Faculty of Electrical & Electronic Engineering Memory Devices 18 Nguyen Thanh Hai, PhD 11.3 Flash Memory University of Technical Education Faculty of Electrical & Electronic Engineering Memory Devices 19 Nguyen Thanh Hai, PhD University of Technical Education Faculty of Electrical & Electronic Engineering Memory Devices 20 Nguyen Thanh Hai, PhD [...]... Education Faculty of Electrical & Electronic Engineering Memory Devices 11.4 RAM Architecture 21 Nguyen Thanh Hai, PhD University of Technical Education Faculty of Electrical & Electronic Engineering Memory Devices Nguyen Thanh Hai, PhD Examples 11.9 – 11.10 22 University of Technical Education Faculty of Electrical & Electronic Engineering Memory Devices 11.4.1 SRAM (Static RAM) - SRAM using many transistors... Engineering Memory Devices 11.4.2 DRAM (Dynamic RAM) - A cell designed using row and column to control MOSFET and a capacity is to charge or recharge for 0 or 1 level 24 Nguyen Thanh Hai, PhD University of Technical Education Faculty of Electrical & Electronic Engineering Memory Devices 25 Nguyen Thanh Hai, PhD University of Technical Education Faculty of Electrical & Electronic Engineering Memory Devices -TMS... Faculty of Electrical & Electronic Engineering Memory Devices Expanding Capacity of RAM -CS inverted using common line, AB4 through NOT gate to select RAM -Two groups of Data lines in common A RAM 32Kx4 generated by using 2 RAMs 16Kx4 27 Nguyen Thanh Hai, PhD University of Technical Education Faculty of Electrical & Electronic Engineering Memory Devices CS inverted using common line 28 Nguyen Thanh... Technical Education Faculty of Electrical & Electronic Engineering Memory Devices -CS inverted using common line, AB4 through NOT gate to select RAM -Data lines not to be in common 29 Nguyen Thanh Hai, PhD A way to generate a RAM 32Kx8 from 2 RAMs 16Kx8 University of Technical Education Faculty of Electrical & Electronic Engineering Memory Devices 11.5 Cache Memory CPU SRAM CPU Cache Cache CPU Controller DRAM... of Cache 30 Nguyen Thanh Hai, PhD University of Technical Education Faculty of Electrical & Electronic Engineering Memory Devices Diagram of a cache in the CPU system 31 Nguyen Thanh Hai, PhD University of Technical Education Faculty of Electrical & Electronic Engineering Memory Devices Diagram of a CPU memory cache -Thousands or millions of bytes of internal memory (RAM and ROM) -To store programs... Thanh Hai, PhD University of Technical Education Faculty of Electrical & Electronic Engineering Memory Devices -Take a look Examples from pages - Answer Review questions at page - Homework 34 Nguyen Thanh Hai, PhD University of Technical Education Faculty of Electrical & Electronic Engineering Memory Devices The End 35 Nguyen Thanh Hai, PhD ... need a block of high-speed cache memory for processing something However it is not for all 32 Nguyen Thanh Hai, PhD University of Technical Education Faculty of Electrical & Electronic Engineering Memory Devices -Cache memory often has architecture as RAM (SRAM) and in some specific cases, it can use DRAM chip -Cache memory has high speed and is located between a main memory and CPU -Usually to store instructions . Electrical & Electronic Engineering Memory Devices 2 Nguyen Thanh Hai, PhD 11. 1 Introduction 11. 2 ROM Architecture 11. 3 Flash Memory 11. 4 RAM Architecture 11. 5 Cache Memory University of Technical. 0 . . . . . . . . . . . . 1 1 0 1 1 1 0 1 0 1 1 1 0100 110 1 WRITING the data word 0100 into memory location 00 011 READING the data word 110 1 from memory location 111 10 3 I 2 I 1 I 0 I 3 O 2 O 1 O 0 O 3 A 2 A 1 A 0 A 4 A Data. Engineering Memory Devices 3 Nguyen Thanh Hai, PhD 11. 1 Introduction Types of memory devices University of Technical Education Faculty of Electrical & Electronic Engineering Memory Devices 4 Nguyen