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1 Lecture: DIGITAL SYSTEMS Nguyen Thanh Hai, PhD Chapter 8: Integrated Circuits University of Technical Education Faculty of Electrical & Electronic Engineering University of Technical Education Faculty of Electrical & Electronic Engineering Integrated Circuits 2 Nguyen Thanh Hai, PhD 8.1 TTL and CMOS Families 8.2 Data sheet 8.3 The loading and the Fan-out 8.4 Open-Collector/Open-Drain Outputs 8.5 Tristate (Three-State) Logic Outputs 8.6 TTL Driving CMOS 8.7 CMOS Driving TTL University of Technical Education Faculty of Electrical & Electronic Engineering Integrated Circuits 3 Nguyen Thanh Hai, PhD 8.1 TTL and CMOS Families CMOS Family TTL Family Large impendence Ohm law: R=U/I Complementary metal–oxide–semiconductor (CMOS) Transistor–Transistor Logic (TTL) B C E University of Technical Education Faculty of Electrical & Electronic Engineering Integrated Circuits 4 Nguyen Thanh Hai, PhD 8.2 Data sheet University of Technical Education Faculty of Electrical & Electronic Engineering Integrated Circuits 5 Nguyen Thanh Hai, PhD 8.2 Data sheet University of Technical Education Faculty of Electrical & Electronic Engineering Integrated Circuits 6 Nguyen Thanh Hai, PhD -V IH (min) – High - Level Input Voltage -V IL (max) – Low - Level Input Voltage -V OH (min) – High - Level Output Voltage -V OL (max) – Low - Level Output Voltage -I IH High - Level Input Current -I IL Low - Level Input Current -I OH High-Level Output Current -I OL Low - Level Output Current 8.3 TTL Loading and the Fan-out University of Technical Education Faculty of Electrical & Electronic Engineering Integrated Circuits 7 Nguyen Thanh Hai, PhD Performance ratings 74 74 S 74LS 74AS 74AL S 74F Propagation delay (ns) 9 3 9.5 1.7 4 3 Power dissipation (mW) 10 20 2 8 1.2 6 Speed-power product (pJ) 90 60 19 13.6 4.8 18 Max. clock rate (MHz) 35 125 45 200 70 100 Fan-out (same series) 10 20 20 40 20 33 Voltage parameters V OH (min)_V 2.4 2.7 2.7 2.5 2.5 2.5 V OL (max)_V 0.4 0.5 0.5 0.5 0.5 0.5 V IH (min)_mV 2.0 2.0 2.0 2.0 2.0 2.0 V IL (max)_mV 0.8 0.8 0.8 0.8 0.8 0.8 Table-1 8.3 TTL Loading and the Fan-out University of Technical Education Faculty of Electrical & Electronic Engineering Integrated Circuits 8 Nguyen Thanh Hai, PhD 8.3 TTL Loading and the Fan-out Source University of Technical Education Faculty of Electrical & Electronic Engineering Integrated Circuits 9 Nguyen Thanh Hai, PhD 8.3 TTL Loading and the Fan-out Sink University of Technical Education Faculty of Electrical & Electronic Engineering Integrated Circuits 10 Nguyen Thanh Hai, PhD - To calculate for driving many inputs OL I IL I IL I IL I 8.3 TTL Loading and the Fan-out -Output of a logic gate can drive inputs -Fan-out is also called loading factor: the fan-out value of the output can drive the maximum number of the logic inputs. University of Technical Education Faculty of Electrical & Electronic Engineering Integrated Circuits 11 Nguyen Thanh Hai, PhD University of Technical Education Faculty of Electrical & Electronic Engineering Integrated Circuits 12 Nguyen Thanh Hai, PhD University of Technical Education Faculty of Electrical & Electronic Engineering Integrated Circuits 13 Nguyen Thanh Hai, PhD Example 8.1: How many 74ALS00 NAND gate inputs can be driven by a 74ALS00 NAND gate output? Solution: According to 74ALS00 data sheet, one finds I OL (max) = 8 mA (Low output); I IL (max) = 0.1 mA (Low input) I OH (max) = 400 uA (High output); I IH (max) = 20 uA (High input) Fan-out •Fan-out (LOW) = I OL (max)/I IL (max)=8 mA/0.1 mA = 80. Then, the number of inputs possibly driven in the LOW state is 80. •Fan-out (HIGH) = I OH (max)/I IH (max)=400 uA/20 uA = 20. Then, the number of inputs possibly driven in the HIGH state is 20. •High and Low states are not the same, so we can choose so that the 74ALS00 can drive up to 20 other 74ALS00 NAND gates. University of Technical Education Faculty of Electrical & Electronic Engineering Integrated Circuits 14 Nguyen Thanh Hai, PhD Example 8.2: A 74LS00 NAND gate output is driving three 74SXX gate inputs and one 7406 input. Determine if there is a loading problem. Solution: 1. Add all of the I IH values: 3.(I IH for 74S) + 1.(I IH for 74) Total = 3.(50 uA) + 1.(40 uA) = 190 uA I OH for the 74LS output is 400 uA (max) > 190 uA. This satisfies the HIGH output. 2. Add all of the I IL values: 3.(I IL for 74S) + 1.(I IL for 74) Total = 3.(2 mA) + 1.(1.6 mA) = 7.6 mA I OL for the 74LS output is 8 mA (max) > 7.6 mA. This satisfies the LOW output. University of Technical Education Faculty of Electrical & Electronic Engineering Integrated Circuits 15 Nguyen Thanh Hai, PhD 8.4 Open-Collector/Open-Drain Outputs Q 3 ON V 0 = V OL ≤ 0.4 V Q 3 OFF V 0 = V OL = +5 V 0 V )( R p external R p = 10kΩ is small enough for the minimum below V OH and I OL (max) R p is connected outside V 0 at the output University of Technical Education Faculty of Electrical & Electronic Engineering Integrated Circuits 16 Nguyen Thanh Hai, PhD 8.4 Open-Collector/Open-Drain Outputs University of Technical Education Faculty of Electrical & Electronic Engineering Integrated Circuits 17 Nguyen Thanh Hai, PhD 8.4 Open-Collector/Open-Drain Outputs Symbolizes the wired-AND connection A B C Ωk 10 V 5 + C.B.A Output = A B C 444 3444 21 drain)-(open 74HC05 or collector)-(open 74LS05 -Only pulling outputs LOW -Sharing the same wire for transmitting in a logic level University of Technical Education Faculty of Electrical & Electronic Engineering Integrated Circuits 18 Nguyen Thanh Hai, PhD 8.4 Open-Collector/Open-Drain Outputs Transistor shown for illustrative purposes Q CLK J K 0 V + − mA 25 V, 24 7406 74LS112 Q V 24 + -7406 buffer between FF and Lamp -Lamp acting as the pull-up resistor for the open-collector output -Q = 1, the lamp is on and otherwise Q = 0, it is off. University of Technical Education Faculty of Electrical & Electronic Engineering Integrated Circuits 19 Nguyen Thanh Hai, PhD 8.4 Open-Collector/Open-Drain Outputs -In this case, 7406 open-collector output is to drive an indicator LED. -The resistor R s is for limiting the current Q CLK D s R 7406 74HCT74 Q V 5 + University of Technical Education Faculty of Electrical & Electronic Engineering Integrated Circuits 20 Nguyen Thanh Hai, PhD 8.5 Tristate (Three-State) Logic Outputs V + LOW HIGH ON OFF enabled 1 OE = (a) V + HIGH LOW ON OFF enabled 1 OE = (b) V + LOW or HIGH Z - HI OFF disabled 0 OE = OFF (c) [...]... Engineering Integrated Circuits 8.5 Tristate (Three-State) Logic Outputs 74LS126 74LS125 A A X X E E E X E X 0 1 A Hi-Z 0 1 Hi-Z A 21 Nguyen Thanh Hai, PhD University of Technical Education Faculty of Electrical & Electronic Engineering Integrated Circuits 8.5 Tristate (Three-State) Logic Outputs 74LS126 74LS126 A Disabled A X EA EA B EB C EC Nguyen Thanh Hai, PhD Common bus To other circuits B Enabled... Education Faculty of Electrical & Electronic Engineering Integrated Circuits Example 8.3: 25 Nguyen Thanh Hai, PhD University of Technical Education Faculty of Electrical & Electronic Engineering Integrated Circuits Example 8.4: 26 Nguyen Thanh Hai, PhD University of Technical Education Faculty of Electrical & Electronic Engineering Integrated Circuits Example 8.5: 27 Nguyen Thanh Hai, PhD University of Technical... Electronic Engineering Integrated Circuits Example 8.6: 28 Nguyen Thanh Hai, PhD University of Technical Education Faculty of Electrical & Electronic Engineering Integrated Circuits -Take a look Examples from pages - Answer Review questions - Homework 29 Nguyen Thanh Hai, PhD University of Technical Education Faculty of Electrical & Electronic Engineering Integrated Circuits The End 30 Nguyen Thanh... Outputs 74LS126 74LS126 A Disabled A X EA EA B EB C EC Nguyen Thanh Hai, PhD Common bus To other circuits B Enabled EB +5 V C Disabled X EC To other circuits 22 University of Technical Education Faculty of Electrical & Electronic Engineering Integrated Circuits 8.6 TTL Driving CMOS +5 V External pull-up resistor is used when TTL drive COMS 10 kΩ CMOS TTL +10 V +5 V 74LS112 10 KΩ J CMOS Q 74LS07 CLK... K A 7407 opencollector buffer can be used to interface TTL to high-voltage COMS TTL 23 Nguyen Thanh Hai, PhD University of Technical Education Faculty of Electrical & Electronic Engineering Integrated Circuits 8.7 CMOS Driving TTL VDD = +15 V VDD = +5 V 15 V 0 A B VCC = +5 V 5V 0 C 4001B 4050B CMOS CMOS VDD=+15V VDD=+5V 74LS00 CMOS VCC=+5V A 4050B buffer simply passes the 4001B output signal to the . 2.0 V IL (max)_mV 0 .8 0 .8 0 .8 0 .8 0 .8 0 .8 Table-1 8. 3 TTL Loading and the Fan-out University of Technical Education Faculty of Electrical & Electronic Engineering Integrated Circuits 8 Nguyen Thanh. Electronic Engineering Integrated Circuits 2 Nguyen Thanh Hai, PhD 8. 1 TTL and CMOS Families 8. 2 Data sheet 8. 3 The loading and the Fan-out 8. 4 Open-Collector/Open-Drain Outputs 8. 5 Tristate (Three-State). Engineering Integrated Circuits 4 Nguyen Thanh Hai, PhD 8. 2 Data sheet University of Technical Education Faculty of Electrical & Electronic Engineering Integrated Circuits 5 Nguyen Thanh Hai, PhD 8. 2