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1 Lecture: DIGITAL SYSTEMS Chapter 5: Flip_Flops and Related Devices Nguyen Thanh Hai, PhD University of Technical Education Faculty of Electrical & Electronic Engineering University of Technical Education Faculty of Electrical & Electronic Engineering Flip-Flops and Related Devices 2 Nguyen Thanh Hai, PhD 5.1 NAND Gate Latch 5.2 NOR Gate Latch 5.3 Clock signals 5.4 Clocked S-R Flip-Flop 5.5 Clocked J-K Flip-Flop 5.6 Clocked D Flip-Flop 5.7 D Latch 5.8 Asynchronous Input 5.9 Flip-Flop Synchronization 5.10 Data Storage Transfer 5.11 Serial Data Transfer 5.12 Analyzing Sequential Circuit 5.13 Clock Generator Circuits University of Technical Education Faculty of Electrical & Electronic Engineering Flip-Flops and Related Devices 3 Nguyen Thanh Hai, PhD 5.1 NAND Gate Latch Input Output S R Q n+1 0 1 1 1 0 0 1 1 Q n No change 0 0 Forbidden (invalid) -R-S (Reset-Set) NAND Flip-Flop Or C-S (Clear-Set) -Two stable states S R University of Technical Education Faculty of Electrical & Electronic Engineering Flip-Flops and Related Devices 4 Nguyen Thanh Hai, PhD Input Output S R Q 0 1 1 0 Q R S 1 0 Input Output S R Q 1 0 0 1 Q R S 0 1 5.1 NAND Gate Latch University of Technical Education Faculty of Electrical & Electronic Engineering Flip-Flops and Related Devices 5 Nguyen Thanh Hai, PhD Input Output S R Q 1 1 No change S R Q 0 1 1 1 Input Output S R Q 0 0 Forbidden S R Q 5.1 NAND Gate Latch University of Technical Education Faculty of Electrical & Electronic Engineering Flip-Flops and Related Devices 6 Nguyen Thanh Hai, PhD 5.2 NOR Gate Latch Input Output S R Q n+1 0 1 0 1 0 1 1 1 Forbidden (invalid) 0 0 Q n No change R-S (Reset-Set) NOR Flip-Flop University of Technical Education Faculty of Electrical & Electronic Engineering Flip-Flops and Related Devices 7 Nguyen Thanh Hai, PhD Example 5.1: The waveforms of the below figure are applied to the inputs of the latch of the figure. Assume that initially Q=0, and determine the Q waveform. S R University of Technical Education Faculty of Electrical & Electronic Engineering Flip-Flops and Related Devices 8 Nguyen Thanh Hai, PhD University of Technical Education Faculty of Electrical & Electronic Engineering Flip-Flops and Related Devices 9 Nguyen Thanh Hai, PhD Example 5.2: University of Technical Education Faculty of Electrical & Electronic Engineering Flip-Flops and Related Devices 10 Nguyen Thanh Hai, PhD University of Technical Education Faculty of Electrical & Electronic Engineering Flip-Flops and Related Devices 11 Nguyen Thanh Hai, PhD University of Technical Education Faculty of Electrical & Electronic Engineering Flip-Flops and Related Devices 12 Nguyen Thanh Hai, PhD 5.3 Clock Signals HIGH input clock pulse Positive transition input clock pulse (edge- triggered) LOW input clock pulse Negative transition input clock pulse (edge- triggered) University of Technical Education Faculty of Electrical & Electronic Engineering Flip-Flops and Related Devices 13 Nguyen Thanh Hai, PhD • The circuit for generating a narrow clock pulse Ck with positive transition (edge). University of Technical Education Faculty of Electrical & Electronic Engineering Flip-Flops and Related Devices 14 • The circuit for generating a narrow clock pulse Ck with negative transition (edge). Nguyen Thanh Hai, PhD University of Technical Education Faculty of Electrical & Electronic Engineering Flip-Flops and Related Devices 15 Nguyen Thanh Hai, PhD 5.4 Clocked S-R Flip-Flop Input Output S R CL K Q n+1 0 0 No change 1 0 1 0 1 0 1 1 Ambiguous Logic Circuit Truth Table University of Technical Education Faculty of Electrical & Electronic Engineering Flip-Flops and Related Devices 16 Input Output S R CL K Q n+1 0 0 No change 1 0 1 0 1 0 1 1 Ambiguous R Q CK S 1 0 Set change No Reset Set Set Time CLK FF Triggers positive transition Respond to positive edge clock pulse 5.4 Clocked S-R Flip-Flop University of Technical Education Faculty of Electrical & Electronic Engineering Flip-Flops and Related Devices 17 Input Output S R CL K Q n+1 0 0 No change 1 0 1 0 1 0 1 1 Ambiguous Respond to negative edge clock pulse CLK Triggers on negative edge R Q CK S 1 0 Set change No Reset Set Set Time 5.4 Clocked S-R Flip-Flop University of Technical Education Faculty of Electrical & Electronic Engineering Flip-Flops and Related Devices 18 Nguyen Thanh Hai, PhD 5.5 Clocked J-K Flip-Flop University of Technical Education Faculty of Electrical & Electronic Engineering Flip-Flops and Related Devices 19 Nguyen Thanh Hai, PhD 5.5 Clocked J-K Flip-Flop )0,1,1,1( 11*10*1 ==== = + = QQKJ )0,0,1,0( 00*01*0 ==== = + = QQKJ University of Technical Education Faculty of Electrical & Electronic Engineering Flip-Flops and Related Devices 20 Nguyen Thanh Hai, PhD 5.5 Clocked J-K Flip-Flop [...]... Electrical & Electronic Engineering Flip-Flops and Related Devices 5.7 D Latch 25 Nguyen Thanh Hai, PhD University of Technical Education Faculty of Electrical & Electronic Engineering Flip-Flops and Related Devices Example 5.3: 26 Nguyen Thanh Hai, PhD University of Technical Education Faculty of Electrical & Electronic Engineering Flip-Flops and Related Devices 27 Nguyen Thanh Hai, PhD University of Technical... Electrical & Electronic Engineering Flip-Flops and Related Devices Example 5.4: 28 Nguyen Thanh Hai, PhD University of Technical Education Faculty of Electrical & Electronic Engineering Flip-Flops and Related Devices 29 Nguyen Thanh Hai, PhD University of Technical Education Faculty of Electrical & Electronic Engineering Flip-Flops and Related Devices 5.7 Asynchronous Input PRESET CLEAR FF response 1...University of Technical Education Faculty of Electrical & Electronic Engineering Flip-Flops and Related Devices 5.6 Clocked D Flip-Flop D CLK CLK Edge-triggered D FF using J-K FF 21 Nguyen Thanh Hai, PhD University of Technical Education Faculty of Electrical & Electronic Engineering Flip-Flops and Related Devices 5.6 Clocked D Flip-Flop D-FF with its waveforms with positive edge clock 22 Nguyen Thanh Hai,... University of Technical Education Faculty of Electrical & Electronic Engineering Flip-Flops and Related Devices 5.6 Clocked D Flip-Flop D-FF with its waveforms with negative edge clock 23 Nguyen Thanh Hai, PhD University of Technical Education Faculty of Electrical & Electronic Engineering Flip-Flops and Related Devices 5.7 D Latch D-Latch with waveforms Enable=1, D=1, Q=1 Nguyen Thanh Hai, PhD Enable=1, D=0,... Flip-Flops and Related Devices Example 5.5: + 5V Point PRE a Operation b Synchronous toggle on NGT of CLK Asynchronous set on PRE= 0 c Synchronous toggle d Synchronous toggle e Asynchronous clear on CLR = 0 f CLR over-rides the NGT of CLK Synchronous toggle g CLR 31 Nguyen Thanh Hai, PhD University of Technical Education Faculty of Electrical & Electronic Engineering Flip-Flops and Related Devices Example... Education Faculty of Electrical & Electronic Engineering Flip-Flops and Related Devices 5.8 Flip-Flop Synchronization Debounced switch A X CLOCK CLOCK A Q X T1 Nguyen Thanh Hai, PhD 14444244443 T2 4 4 33 Complete Pulses University of Technical Education Faculty of Electrical & Electronic Engineering Flip-Flops and Related Devices 5.9 Data Storage and Transfer A B CLK A B A B Q=0 Q=1 B goes HIGH before... Flip-Flops and Related Devices 5.9 Data Storage and Transfer Register X 64444444 4444444 7 8 X1 Transfer X3 X1 D X2 X2 X3 D Y1 CLK Y1 D Y2 Y3 CLK Y3 CLK Y2 144444444 44444444 2 3 Register Y Parallel data transfer of contents of register X into register Y 35 Nguyen Thanh Hai, PhD University of Technical Education Faculty of Electrical & Electronic Engineering Flip-Flops and Related Devices 5.10 Serial... Technical Education Faculty of Electrical & Electronic Engineering Flip-Flops and Related Devices 5.10 Serial Data Transfer: Shift register Shift pulses DATA IN T1 T2 T3 T4 X3 X2 X1 X0 37 Nguyen Thanh Hai, PhD University of Technical Education Faculty of Electrical & Electronic Engineering Flip-Flops and Related Devices 5.11 Microcomputer Application D A15 A14 A13 A12 A11 A10 A9 A8 MPU CLK D 1 X2 2 CLK... Electrical & Electronic Engineering Flip-Flops and Related Devices 5.12 Analyzing Sequential Circuits 1 0 1 J 0 J X CLK 1 1 KHz clock X Z 1 K From 0 1 FFs 1 0 J CLK CLK 1 K 1 Y Y Z K W CK J K Qn+1 1 0 0 Qn 1 0 1 0 1 1 0 1 1 1 1 1 Qn 39 Nguyen Thanh Hai, PhD University of Technical Education Faculty of Electrical & Electronic Engineering Flip-Flops and Related Devices 5.12 Analyzing Sequential Circuits Clock... Thanh Hai, PhD University of Technical Education Faculty of Electrical & Electronic Engineering Flip-Flops and Related Devices 5.13 Clock Generator Circuits 41 Nguyen Thanh Hai, PhD University of Technical Education Faculty of Electrical & Electronic Engineering Flip-Flops and Related Devices 5.13 Clock Generator Circuits t1 = 0.693 R b C t 2 = 0.693 (R a + R b )C T = t1 + t 2 Frequency: f = 1/T duty . and Related Devices 2 Nguyen Thanh Hai, PhD 5. 1 NAND Gate Latch 5. 2 NOR Gate Latch 5. 3 Clock signals 5. 4 Clocked S-R Flip-Flop 5. 5 Clocked J-K Flip-Flop 5. 6 Clocked D Flip-Flop 5. 7 D Latch 5. 8. Engineering Flip-Flops and Related Devices 20 Nguyen Thanh Hai, PhD 5. 5 Clocked J-K Flip-Flop University of Technical Education Faculty of Electrical & Electronic Engineering Flip-Flops and Related Devices 21 Nguyen. toggle CLK 0=PRE 0=CLR CLR CLK PRE CLR V5 + University of Technical Education Faculty of Electrical & Electronic Engineering Flip-Flops and Related Devices 32 Nguyen Thanh Hai, PhD Example 5. 5: Waveforms showing how a clocked FF