accurate analog synthesis based on circuit matrix models

UNIVERSITY OF CINCINNATI Date: I, , hereby submit this original work as part of the requirements for the degree of: in It is entitled: Student Signature: This work and its defense approved by: Committee Chair: 11/15/2009 172 8-Sep-2009 Almitra Pradhan Doctor of Philosophy Computer Science & Engineering Accurate Analog Synthesis Based On Circuit Matrix Models Ranganadha Vemuri, PhD Harold Carter, PhD Wen Ben Jone, PhD Carla Purdy, PhD Jintai Ding, PhD Ranganadha Vemuri, PhD Harold Carter, PhD Wen Ben Jone, PhD Carla Purdy, PhD Jintai Ding, PhD Almitra Pradhan Accurate Analog Synthesis With Circuit Matrix Models A dissertation submitted to the Graduate School at the University of Cincinnati in partial fulfillment of the requirements for the degree of DOCTOR OF PHILOSOPHY in the Department of Electrical and Computer Engineering and Computer Science of the College of Engineering 2009 by Almitra Pradhan Bachelor of Engineering (EE) Veermata Jeejabai Technological Institute (V.J.T.I.), Mumbai University June 2002 Thesis Advisor and Committee Chair: Dr. Ranga Vemuri Abstract Automated synthesis is imperative for the rapid design of analog circuits. Knowledge based and optimization based methods have emerged to provide solutions for analog synthesis, especially for device sizing. Posing analog sizing as a constrained optimization problem facilitates the application of many well developed algorithms for this purpose. All optimization based sizing methods are based on the common thread of design space exploration and performance evaluation. Design space exploration is required for finding design solutions satisfying the given performance constraints. During exploration a performance evaluator is required to determine the quality of the examined solutions. The efficiency of the sizing procedure is completely dependant upon the speed of the perfor- mance evaluator. Some of the recently proposed techniques construct models for performance pa- rameters in the circuits design space and use them for performance prediction. Methods based on this principle can be collectively called Performance Macromodeling methods. Avoiding simulation gives the advantage of fast synthesis to these methods at the expense of moderate modeling errors. Performance macromodeling methods can rapidly explore the design space and offer sizing solu- tions in a reasonable time. However, they are successful only for synthesizing those specifications who models have been developed. In this dissertation we propose performance prediction using Circuit Matrix Models to estimate the performance of analog circuits. Using these models the entire a.c. behavior of the circuit is captured. With the use of matrix models, the limitation that a circuit can by synthesized for the modeled performance specifications is eliminated. Any linear performance characteristic can be calculated from the models. Analog circuits need to be designed with high accuracy. With circuit matrix models it is seen that performance prediction is precise and synthesized circuits are very accurate. We then develop techniques to expedite synthesis by making matrix model evaluation extremely fast. The first technique uses hashing for obtaining the desired speedup. This technique takes advantage of matrix elements being dependent on a subset of design variables. Design sub-spaces are visited several times when the entire space is being explored in a synthesis run. Hash tables save the matrix element values computed in the visited subspace and reuse them when that subspace is visited again. This saves a large amount of recomputations and imparts speedup to the synthesis procedure. i The second technique has a nearest neighbor searching algorithm at its core. It uses values at design points visited to incrementally compute values at neighboring design points. A first order Taylor series approximation is sufficient for such incremental computation and this makes per- formance estimation procedure extremely fast. A balanced box decomposition tree data structure makes detecting exact or approximate neighbors quite efficient. The circuit design variables form the dimensions of the search space. The distance metric for neighbor computation is modified by considering sensitivity of matrix elements to the search space dimensions. Using this method, very few computations are required during the synthesis process. Layout parasitics are detrimental to the performance of analog circuits. Considering their effects early in the design flow is essential for achieving designs with parasitic closure. We have developed circuit matrix models inclusive of parasitic effects. The models use area and perimeter as predictor variables and can be used to compute parasitic inclusive matrix element values for many geometries. Thus, the most suitable geometry for component modules is selected dynamically by the optimizer as a part of synthesis. Operational amplifiers and filter topologies have been synthesized as a part of this work. The optimization objectives for analog circuits can be conflicting and often for improving a particular performance several others have to be sacrificed. Considering the performance tradeoffs is quite important for such multi-objective optimization problems. The developed circuit matrix models have been used to generate parasitic-aware pareto-optimal performance curves. The method stores an archive of non-dominated performance points and the corresponding design points that achieve this performance. This can be used for determining the limits of achievable performance for a given topology as well as for sizing. ii iii Acknowledgments I would like to thank Dr. Ranga Vemuri for his guidance that helped shape this dissertation. His advice helped the research direction, explore several ideas, and refine experiments and publications developed during the course of this work. My committee members, Dr. Wen-ben Jone, Dr. Hal Carter, Dr. Carla Purdy and Dr. Jintai Ding, offered helpful suggestions which have further im- proved this work and my sincere thanks to them. This work was funded in part by the grant from National Science Foundation (CCF-0429717)which made this research work possible. DDEL has been a great place to work and I would like to thank Angan, Shubhankar, Bala, Vijay - my colleagues for the most part here, for allowing me to learn from their experience, the encouragement when the going was rough and the discussions that sometimes helped put things in perspective. Coffee breaks in the lab with Annie, Mike, Surya, Pritesh and others have given moments of respite which were valuable, especially on difficult days. I would also like to thank Dr. Anuradha Agarwal for responding to my queries even after graduating from the lab. Cincinnati became a home away from home thanks to great support from my friends, the whole of ’Cinci Friends’ group, Ketaki and many others. These times spent enjoying and arguing, cele- brating or just relaxing will be cherished forever. I would also like to thank my colleagues from the Graduate School office who have been a great bunch and with whom I really enjoyed working during both my stints there. I would never have been here but for my parents who always encouraged me to pursue higher educational goals and have been a constant source of encouragement. My younger sister Asmita and my extended family back home have been a great support system for me. I would also like to thank my mother-in-law, Mrs. Anjali Salgaonkar for being encouraging about my educational aspirations. Nothing has been more important in the completion of this dissertation than the support of my husband, Dr. Vasant Salgaonkar. We were both enrolled in doctoral programs at the same time, but things did not seem too difficult due to his patience, help and support. Vasant has been a constant source of encouragement through the completion of this research work which had its ups and downs but none that seemed overwhelming thanks to his support. We made it !! iv Contents List of Figures x List of Tables xiii 1 Introduction 1 1.1 Overview of the synthesis process . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.2 Alternatives for analog circuit synthesis . . . . . . . . . . . . . . . . . . . . . . . 4 1.3 Desirable Macromodel Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 9 1.4 Research Approach and Overview . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.5 Thesis Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2 Circuit Matrix Models for Accurate Performance Estimation 17 2.1 Introduction to Circuit Matrix Models . . . . . . . . . . . . . . . . . . . . . . . . 17 2.2 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.3 Modeling Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.3.1 Circuit Matrix Generation . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.3.2 Reducing number of models . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.3.3 Data Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.3.4 Fitting Models for the Matrix Elements . . . . . . . . . . . . . . . . . . . 24 2.4 Description of Test Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.5 Accuracy of the developed models . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.6 Estimation using Performance Macromodels . . . . . . . . . . . . . . . . . . . . . 31 v 2.7 Synthesis Using Circuit Matrix Models . . . . . . . . . . . . . . . . . . . . . . . 33 2.7.1 Synthesis with common performance specifications . . . . . . . . . . . . . 33 2.7.2 Synthesis with non-standard specifications . . . . . . . . . . . . . . . . . 34 2.7.3 Alternate forms of target specifications . . . . . . . . . . . . . . . . . . . 36 2.8 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3 Hash Classes for Efficient Synthesis 38 3.1 Review of Hashing Algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.1.1 R-B trees for implementing hash tables . . . . . . . . . . . . . . . . . . . 40 3.2 The Concept of Hash Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.3 Partial Solutions in SA based search . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.4 Proposed synthesis flow using hash tables . . . . . . . . . . . . . . . . . . . . . . 44 3.5 Hash Table Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.6 Estimation of Speedup by Hashing . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.7 Integrating Hash Classes in the Synthesis Flow . . . . . . . . . . . . . . . . . . . 47 3.8 Experiments to determine speedup with hash tables . . . . . . . . . . . . . . . . . 48 3.8.1 Single Ended Opamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.8.2 High Gain Differential Amplifier . . . . . . . . . . . . . . . . . . . . . . . 52 3.9 Synthesis Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 3.10 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4 Sensitivity Based Near Neighbor Search 57 4.1 Limitation of the hashing approach . . . . . . . . . . . . . . . . . . . . . . . . . . 57 4.2 Calculation of matrix values by incremental updates . . . . . . . . . . . . . . . . . 58 4.3 Algorithms for Near(est) Neighbor Search . . . . . . . . . . . . . . . . . . . . . . 59 4.4 The Optimal Nearest Neighbor Search Algorithm . . . . . . . . . . . . . . . . . . 61 4.4.1 Distance Measures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 4.5 Multi-dimensional Near Neighbor Search for Analog Synthesis . . . . . . . . . . . 62 4.6 Method for computing allowable perturbations . . . . . . . . . . . . . . . . . . . . 63 4.7 Algorithm for synthesis with sensitivity based near neighbor searches . . . . . . . 64 vi 4.8 Experiments to determine synthesis speedup . . . . . . . . . . . . . . . . . . . . . 65 4.9 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 5 Layout-aware Synthesis with Module Geometry Selection 69 5.1 Need for Layout-Aware Circuit Models . . . . . . . . . . . . . . . . . . . . . . . 70 5.2 Parasitic Aware Matrix Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 5.2.1 Schematic Matrix Models . . . . . . . . . . . . . . . . . . . . . . . . . . 72 5.2.2 Device Parasitic Models . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 5.2.3 Models for Non-Device Parasitics . . . . . . . . . . . . . . . . . . . . . . 75 5.3 Synthesis with Dynamic Geometry Selection . . . . . . . . . . . . . . . . . . . . 77 5.4 Proposed Layout-Aware Synthesis Flow . . . . . . . . . . . . . . . . . . . . . . . 78 5.5 Experiments and Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 5.5.1 Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 5.5.2 Fourth Order Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 5.5.3 Dynamic Geometry Selection . . . . . . . . . . . . . . . . . . . . . . . . 82 5.6 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 6 Pareto-optimal Circuit Performance Curves 85 6.1 Related work for Pareto-optimal performance curve generation . . . . . . . . . . . 86 6.2 Layout-aware Pareto-optimal curves using circuit matrix models . . . . . . . . . . 88 6.3 Extracting the Pareto-Optimal Performance Curves . . . . . . . . . . . . . . . . . 91 6.3.1 Problem Formulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 6.3.2 Front Generation Methods . . . . . . . . . . . . . . . . . . . . . . . . . . 93 6.3.3 Improving the Efficiency of Pareto Curve Generation . . . . . . . . . . . . 95 6.3.4 Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 6.3.5 Sizing procedure using a generated Pareto Front . . . . . . . . . . . . . . 97 6.4 Experiments and Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 6.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 7 Additional applications of the efficient SA algorithm 104 7.1 SA description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 vii 7.2 Problem characteristics suitable for using the new SA algorithm . . . . . . . . . . 105 7.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 7.3.1 Recursive determinant calculation . . . . . . . . . . . . . . . . . . . . . . 106 7.3.2 Circuit performance variability calculation . . . . . . . . . . . . . . . . . 109 7.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 8 Conclusions and Future Work 112 8.1 Summary of Research Contributions . . . . . . . . . . . . . . . . . . . . . . . . . 112 8.2 Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 8.3 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 8.3.1 Combined circuit matrix models and symbolic performance models for syn- thesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 8.3.2 Reduced circuit matrices for fast performance evaluation . . . . . . . . . . 117 Bibliography 120 A Simulated Annealing Library for Circuit Synthesis 129 A.1 Generic SA optimizer description . . . . . . . . . . . . . . . . . . . . . . . . . . 129 A.2 Optimization results achieved through the SA library . . . . . . . . . . . . . . . . 130 A.2.1 Holder table Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 A.2.2 Cross in tray function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 A.2.3 Crown cross function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 A.2.4 Bukin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 A.2.5 Bird function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 A.2.6 Egg holder function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 A.2.7 Giunta function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 A.2.8 Styblinski-Tang function . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 A.2.9 Chichinadze function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 A.2.10 McCormick function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 A.2.11 Zettle function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 A.2.12 Levy function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 viii [...]... of analog circuits When matrix models are used in optimization based synthesis, partial model evaluation is done to speed up the matrix computation in successive iterations 2.2 Motivation Performance estimation of analog circuits can use either system level models or performance level models It is known that the relation between performance parameters such as UGF, PM and device sizes is extremely nonlinear... synthesis techniques depend on fast and reliable estimation of circuit performance In this chapter we discuss the concept of circuit matrix models and their application in predicting the circuit performance Compared to the traditional performance macromodels, circuit matrix models offer increased performance estimation accuracy Moreover a circuit matrix model captures the behavior of a circuit and can thus... Introduction to Circuit Matrix Models Any linear (or linearized) circuit can be represented mathematically using the Modified Nodal Analysis (MNA) formulation [41, 42] Using MNA, the components of a circuit and their interconnections are expressed in a matrix form Such a matrix is called the system matrix or the circuit matrix The circuit matrix is represented as follows: (G + sC)x = B; y = LT x here G: conductance... application of hashing and nearest neighbor detection in problems such as recursive matrix determinant computation and performance variation estimation due to variations in the nominal design point values Chapter 8 concludes the dissertation and presents some directions for future work related to this topic 16 Chapter 2 Circuit Matrix Models for Accurate Performance Estimation Automated analog circuit synthesis. .. reliant on the designer has produced the second class of synthesis methods which are based on optimization Optimization based synthesis: These methods use robust optimization algorithms to develop parametric optimization tools for analog synthesis No a-priory knowledge is necessary for this category of tools making them adaptable and attractive to any class of circuits The synthesis flow for optimization based. .. Optimiza6 tion based synthesis methods can be classified based on the class of evaluators they use Design evaluators may belong to one of the following classes: • Numerical simulation based • Partial simulation techniques • Numerical model based Numerical simulation based: Simulation based methods rely on a numerical simulator, usually the ubiquitous SPICE program, to evaluate design solutions Using spice... efforts in that direction Several interesting research directions have been under investigation for the circuit sizing problem Most of the circuit sizing techniques fall into two broad categories: 4 • Knowledge based synthesis • Optimization based synthesis Knowledge based synthesis: These methods largely rely on the domain-knowledge of experienced analog designers in the development on synthesis tools The... optimization based procedures have gained preference for automatic synthesis of analog circuits In the presence of multiple alternatives in implementation, the question arises as to what makes a good optimization based technique? Some of the desirable properties of 9 Alternatives for Analog Circuit Synthesis Sizing variable topologies Sizing a pre-determined topology Optimization based Full Simulation Simulation-Lite... of synthesis methods, the focus is on the sizing problem Topology selection and circuit sizing are considered separately The topology is chosen either based on heuristics or may be application based The circuit synthesis problem is then defined as, given a circuit topology find device dimensions such that the target specifications are satisfied This problem, known as the circuit sizing problem, itself is... for evaluation guarantees that the design solution obtained is highly accurate Additionally, since numerical analysis is used for circuit evaluation manual derivation of performance equations are not required Out of the various methods available for synthesis, the simulation methods achieves the best accuracy with limited set up time DELIGHT.SPICE [13], one of the earliest optimization based methods, . Circuit Matrix Models to estimate the performance of analog circuits. Using these models the entire a.c. behavior of the circuit is captured. With the use of matrix models, the limitation that a circuit. . . . . 15 2 Circuit Matrix Models for Accurate Performance Estimation 17 2.1 Introduction to Circuit Matrix Models . . . . . . . . . . . . . . . . . . . . . . . . 17 2.2 Motivation . . . . focus is on the sizing problem. Topology selection and circuit sizing are considered separately. The topology is chosen either based on heuristics or may be application based. The circuit synthesis