21st Century Manufacturing Episode 2 Part 1 ppsx

'94 Semiconductor Manufacturing Chap. 5 Siwafer 8OO·C-l,200·C Siwafer 1f O.Ol-1.0I-lmSi02 <hi Ftpre5.17 Simplified viewsof the oxidation equipment and process (from Semiconductor Device Fundamentals by Pierret, © 1996.Reprinted by permission of Prentice-Hall, Inc., Upper Saddle River, NJ). However, dry oxygen is again preferred for growing the gate oxide's Si0 2 because it gives better Si to Si0 2 interface properties. Rapid thermal oxidation (RTO) allows short time oxidation at suitably high temperatures (Campbell, 1996). 5.10.3 Creating Photomasks The CAD files containing the desired circuit patterns are transferred to a set of pho- tographic plates or photomasks. To do this, the CAD files are first fed into apattern generator-a computer controlled exposure machine. The generator uses flash expo- sure to transfer the IC pattern onto a light-sensitive plate known as the mask. This step is similar to photographic developing. The generator flashes onto the plate a large series of rectangles that correspond to the circuit diagram. The plate is covered in an emulsion/photoresist material, which deliberately breaks down under the exposure. Then, once the exposed resist is sloughed off, the plate is transparent just in those areas that correspond to the circuit. 5.10.4 Photolithography: Projecting the Mask Pattern onto theWBfer Many steps follow to transfer the pattern in each photomask to the wafer. The wafer surface is coated with light-sensitive photoresist material. Typically, photoresist liquid is poured onto the center of the round wafer, which is spun at 1,000 to 5,000 rpm in order to produce a uniform, thin adhesion. The thickness of the film can be controlled by altering liquid viscosity and spinning speed. The photoresist is dried in a warm nitrogen or plain air oven. Photolithography is shown in Figures 5.18 through 5.20. In the early days of IC manufacture, contact and proximity printing were used (Wolf and Tauber, 1986). In such methods the photomask was in contact with, or very close to. the wafer. -Quartztube -Insertionrod <Resistance-heated furnace Siw~feT5 [...]... Table 5.7 for a 20 0 mm wafer, a wafer around the Year 19 95 Final cost including Type Die yield Dice per wafer Good chips MIPS 4600 0,4787 357 17 1 PowerPC 603 HP 71 x 0 Digital 210 64A SuperSPARCl60 0.4495 0 . 21 02 0 .25 35 0 .14 92 3 21 14 4 Cost per good die ($) 18 . 71 testing packing ($) 32. 45 23 .53 45. 51 12 8 27 10 3. 62 18 1.55 15 4 39 10 1.95 15 7.08 14 28 2.35 318 . 31 94 5 .13 Management of Technology 21 3 So for one... package Semiconductor Manufacturing 2' 2 Chap 5 Table 5.5 includes examples: TABLE 5.5 Package and Test Costs (Courtesy of MIPS Technologies) Package type Pin count Package cost ($) Test time (sec) TeSI cost per hour ($) POFP PQFP CeramicPGA CeramicPGA CeramicPGA CeramicPGA CeramicPGA . 603 0.4495 HP 71 x 0 0 . 21 02 Digital 210 64A 0 .25 35 SuperSPARCl60 0 .14 92 357 3 21 12 8 15 4 94 17 1 14 4 27 39 14 18 . 71 23 .53 10 3. 62 10 1.95 28 2.35 32. 45 45. 51 1 81. 55 15 7.08 318 . 31 5 .13 Management of Technology 21 3 So. < ;22 0 12 10 300 PQFP <300 20 10 320 CeramicPGA <300 30 10 320 CeramicPGA <400 4<) 12 34<) CeramicPGA <450 50 13 360 CeramicPGA <500 60 14 380 CeramicPGA >500 70 15 400 The. (mm 2 ) Pins Estimated wafer cost ($) Package MIPS 4600 77 20 8 3 .20 0 POFP PowerPC600 85 24 <J 3,400 POFP HP 71 XO 19 6 504 2, 800 CeramicPGA Digit.a 12 1 064A 16 6 4 31 4,000 CeramicPGA SuperSPARC/60 25 6