204 Semiconductor Manufacturing Chap. 5 Vacuum chilwber Cathode shield Anode Argon inlet Cathode (sourcemateriaI) High voltage ~ To vacuum pump figure 5.28 Sputtering for the interconnect layers (from Introduction to Microelecrric Fab,kotwn by Jaeger, © 1988. Reprinted by permission of Prentice- Hall, Inc., Upper Saddle River, NJ) /Wafer Fipe 5.29 Hot filament evaporation (from Semiconductor Device Fundamentals by Pierret, © 1996. Reprinted by permission of Prentice- Hall, Iac., Upper Saddle River, NJ). I To vacuum pump The e-beam method can cause wafer damaging x-rays. In general practice all these evaporation techniques are less favored in today's commercial tabs. Sput- tering is used for its superior topological coverage and moderate pressure requirements. After the last layer of metal is patterned, a final passivation layer is deposited in order to protect the [C from contamination and damage. Small openings are then etched through the layer to expose square aluminum bonding pads, from which wires will be attached to the package. Wafers Heater Evaporating "material 5.11 Back-End Processing Methods 205 5.11 BACK·END PROCESSING METHODS 5.11.1 Summary Wafers are electronically tested for functionality and separated into individual dice. Each die is set into a chosen package, wire-bonded to the outer perimeter of the package, and finally tested ready for assembly onto a printed circuit board (PCB). This segment of semiconductor production iscalled back-end processing. Figure 5.30 provides an overview of these back-end steps for one of the most common package types, the dual-in-line package. The single IC is shown on the front right side. It is set onto the base with epoxy or a metal alloy.The wire bonds (shown darker) run from bonding pads on the Ie to the lead frame of the package. The lead frame connections go through to the Jcleads or gull-wings that subsequently are attached to the PCB. The outer cover (labeled molding compound) completes the package. 5.11.2 Testing and Separation IC designers include special test dice on the wafer that are subjected to all the same oxidation, etching, layering, and doping processes asthe desired Ie. These special test dice are monitored as much as possible after each of the processing steps described earlier. At the very end of wafer production these test dice are put through an addi- tional series of computer-controlled tests in which fine,needlelike probes contact the aluminum bonding pads of the test dice. If this first check shows that the processing parameters were within proper limits, then each die is tested for functionality. Dice that need to be rejected are marked with an ink spot. After preliminary testing is completed, each die is separated from the wafer, usually by a diamond saw.In this process the wafer is held down on a sticky sheet of Mylar and the diamond saw is used either to saw between the dice completely Molding compound FigureS.30 Thedual-in-linepackage (DIP) (from Manufacturing Engineering and Technology 3/e by Kalpakjian, © 1995.Reprinted bypermission of Prentice-Hall, Inc., Upper Saddle River,NJ). Bond wires -t Die Lead frame Die-support paddl. Spot plate 2.8 Semiconductor Manufacturing Chap. 5 through the wafer or to scribe the wafer and provide continuous notches. In the latter approach. the wafer can he turned upside down on a soft pad. A lightly pressurized roller passes across the back of the wafer, and controlled cracks separate the dice. This method is related to the <100> wafer growing direction. In this orientation, nat- ural cleavage planes run normal to the through thickness direction and to the die separation lines on the wafer surface. Once all the dice are separated, any inked chips are discarded, while the remaining chips are inspected visually, under a microscope, for defects. The die yield from basic wafer production, wafer testing, die separation, and retesting is considered in the next main section. 5.11.3 Attachment, Wire Bonding, and Packaging The good dice are then seated into a desired die package. The bottom of the die is secured with a metal-filled epoxy, or with a 96% gold-4% silicon eutectic alloy that melts and then solidifies in the range 390°Cto 420°Cto secure the die to the surface. Wrre bonding makes the electrical contacts between the top of the die and the surrounding lead frame of the package. Figure 5.31shows the delicate wires running from the bonding pads (typically 100 to 125microns in size) to the frame of the pro- tective package. Of the methods available to attach the thin wires to the bonding pads, thermosonic bonding has emerged as the most efficient method of attachment. In thermosonic wire bonding, delicate,25 micron, gold or aluminum wires are pressure- welded to the pads with a blunt indenter. The bond ismade secure by simultaneously heating the substrate to 150°Cand ultrasonically vibrating the joint. Solid-state welding thus occurs from a combination of pressure, vibration, and warm-plastic deformation of the soft gold or aluminum. Thermosonic bonding machines are easily automated for high-speed production. 5.11.4 Dual-in-L1ne Pacbges IDIPs) The package and packaging material chosen for a chip depend on the Ie's size,number of extemallcads, power and heat dissipation requirements, and intended operating environment. Dual-in-line packages (DIPs) are common packaging styles. They are ~Pl'''''~ .':'~ F1pre 5.31 The DIP packaging method (from Manufacturing Enginuring and Technology 3/e byKalpakjian, © 1995.Reprinted by permission of Prentice-Hall. Inc" Upper Saddle River, NJ). -oeia wires Lead frame r.hin 5.11 Back-End Processing Methods 207 inexpensive, easy to handle, and made from a variety ofmaterials to suit the application including epoxy,plastic, metal, or ceramic. Also the DIP continues to be aworkhorse for prototype circuit design. The usual fonn factor is a plastic rectangle with the I/O leads placed at approximately 0.1inch spacings along the perimeter edges (Figure 5.31). 5.11.5 Quad Flat Packages (QFPI Quad flat packages (QFP) in either plastic or ceramic are today the most often seen commercial packages for gate arrays, standard logic cells, and microproces- sors. Such flat packs are especially favored for computer systems with several stacked printed circuit boards (PCBs), which demand low-profile chips to reduce the vertical packing space. Figure 5.32 shows the standard layout. The upper part of the figure shows that wire bonds will connect the bonding pads to the external leads at the periphery of the ceramic (or plastic) package. The lower figures show the periphery layouts including the gull wing in the center diagrams or the l-lead at bottom left. Despite the popularity of the QFP, close inspection of these dia- grams points out the next technology trend. If the spacing of the leads gets too small, an individual lead might get bent during handing, or, in later processing, solder shorts might form on the PCB between adjacent legs. Further developments to address this issue are reserved for Chapter 6. </-Lid ~Die(wirebonded 'f!!!f after die attach) '-o,re (a) ~ package (SOP) (b) Plastic quad flat pack (PQFP) F1pre 5.32 Quad fiat packaging (QFF) (adapted from Kalpakjian, 1995). Intergrated circuit Bonding wires Molded plastb Assembled Leadframe 208 Semiconductor Manufacturing Chap. 5 5.12 COST OF CHIP MAKING' 5.12.1 Overview Manufacturing involves many processing steps, and each step adds to the cost of the wafer. Therefore, although the cost of a raw unprocessed wafer isonly $15 for a200- mm wafer, the final processed wafer often costs several thousand dollars after about 100 processing steps.The wafer costs depend on the number of masks used, the com- plexity of the circuits, and the clean room requirements of the process. The cost increases with the number of layers in a nonlinear fashion, since each additional masking layer introduces more defects and decreased yield. The cost of the wafer also increases with smaller feature sizes due to stringent requirements on lithog- raphy and process control. However, the cost per chip might then be lower due to the larger number of chips that can be "squeezed onto the real estate." Table 5.4 shows that lithography is the most expensive aspect of processing. Furthermore, to further reduce line width, lithography is the area where the greatest research effort isneeded. Lithography processes and their associated costs will thus continue to be a main focus area in the management of technology. 5.12.2 Cost of a Single IC The calculation of the cost of a single IC involves the three main costs in Equation 5.1, modified by the final integrated yield-that is, the number of good dice leaving the final testing area: Cost of an individual die on a wafer + cost of testing + cost of packaging (5.1) s Important·Throughout this section the data are ha.ed on mid_l990s costs. A~ tim" goes on, the. costs will change. Also, yields will creep toward the ideal 100% level. At the same time, newer designs of chip will experience lower yields-perhaps nearer 50%-while the manufacturing start-up problems are resolved and debugged. The yields shown in the later examples are from Patterson and Hennessy (l996b). By today's standards these are extremely low,but they would still arise in pilot plants. Dataquest's annual Market Analysis of Semiconductor Supply and PricingWorldwide, including its own "Cost Model," is one of the best sources for current data. Therefore a recent example for a 64-Mb DRAM in the year 2000 is included inAppendix 2 of this chapter (Sectiou5.l9) TABL£ 5.4 Relative Costs of Production Processes Manufucruringprocessstep Percentage of wiUer processing cost per cm 2 (clI.cludcs pllckaging. test, and design costs) Lithography Mu1tilevelmaterialsandetching Furnaces/implants Cleaning/stripping Metrology 35% 25 15 20 5 5.12 Cost of Chip Making 209 The following subsections are based on Patterson and Hennessy (1996b). The point to always keep in mind isthat the "good dice" leaving each step of the Ie fabrication process have to bear the processing costs of all the "bad dice" that were discovered and rejected alung the way. Obviously, all efforts are made to detect these bad dice as soon as possible. Nevertheless, some time, effort, and cost will have gone into ere- ating mistakes. For example: • Perhaps a complete wafer has to be rejected. Possible causes include a poorly calibrated stepper, a faulty vacuum system, chemical impurities in a CVD system, or an atmosphere control problem. Detecting this larger scale problem is the function of the test dice on the wafer. These are tested as soon as pos- sible after each processing step to avoid wasting time and resources on a wafer that might already be ruined. • Or, in a more isolated manner.perhaps a dust problem has created several bad dice on an otherwise satisfactory wafer. • Or, alternatively, during back-end processing, an otherwise good die has been misaligned and damaged. At each step some time and cost will have gone into creating these bad dice. And so this cost has to be shouldered by the good dice.Thus the final costs of a single integrated circuit are obtained by dividing Equation 5.1 by the final die yield from the final test. For each processing step, an intermediate die yield can be specified. It is usually stated as a percentage or a value between zero and one. So, in Equation 5.2, if 90% of the dice on the wafer are good dice, by multiplying the "dice per wafer" by 0.9 in the denominator, it can be seen that the cost of each die is higher than if the yield were perfect at 100% or 1. 5.12.3 The Cost of an Individual Die on a Wafer The cost of ao individual die on a perfect wafer involves three main items: • How many dice fit on a single wafer • What percentage of these actually work correctly-namely, the process die yield • An allowance for a few test dice on the wafer-not included in the following equations for simplicity Cost of die = _._costofwafe~ . (5.2) dice per wafer x die yield Step Lrcaicutate the "dice per wafer." ~[:_1W:d~~~~r]_ [.:!!"_X wafer diamete~] die area diediagonal (5.3) The second term allows for the dice around the edge of the wafer. Rings of dice at the outside lose the tip of their outside corners due to the "square peg in a round hole" problem. Strictly, this outside ring might not be exposed during lithography, thereby 2'0 Semiconductor Manufacturing Chap. 5 saving some time, but still some costs will go onto the wafer during processes such as CVD and diffusion. The preceding equations are very dependent on wafer size, prompting the move to the 300 rom wafers in the new tabs. The equation gives the following dice per wafer: • 1 square centimeter die on a 150 mm or 6 inch wafer = 138 dice • 1 square centimeter die on a 200 mm or 8 inch wafer = 269 dice • 1 square centimeter die on a 300 mm or 12 inch wafer = 635 dice Or for a larger Ie: • 2.25 square centimeter die on a 150 mm or 6 inch wafer = 56 dice • 2.25 square centimeter die on a 200 mm or 8 inch wafer = 107 dice • 2.25 square centimeter die on a 300 mm or 12 inch wafer = 269 dice However, note that this calculation gives only the maximum number of dice produced if the fab could achieve 100% yield. The next question is: How many of these are good? Step 2: calculate the "die yield." [ . d] [1 defects per unit area X die area] = Wafer yiel + Cl (5.4) where the wafer yield accounts for wafers that are so bad they need not be tested. Next, the value of a is an empirical factor corresponding to the number of masking levels and the complexity of the manufacturing process being used. Typically, in today's multilevel CMOS processes, a = 3. Factory measurements indicate that the defects per unit area lie somewhere between 0.6 and 1.2 depending on the maturity of the individual processes used. Although these data are empirical rather than analytical, the method assumes that (a) the defects are randomly distributed over the wafer and that (b) the yield is inversely proportional to the complexity of the fabrication process. as measured by the factor a obtained by collecting factory-floor data from CMOS manufacturing. So, for example, using Patterson and Hennessy's (1996b) data, if: • The wafer yield is 100% or 1 (for the sake of simplicity) • The defects per unit area are 0.8 per square centimeter • The die area is 1 square centimeter Die yield = 1 x (1 + [0.8 X 1] 13)-3 = 0.49 From these calculations, it can be concluded that the number of good 1 cm 2 dice on a 200 mm (8 inch) diameter wafer reduces from the maximum possible of 269 to a reduced figure of (269 x 0.49) = only 132. Again using 1996 data from Patterson and Hennessy (l996b, see p. 63), manu- facturing a 200 mm (8 inch) wafer in CMOS costs between $3,000 and $4,000 5.12 Cost of Chip Making 211 depending onthe complexity and brand ofthe microprocessor. Therefore, using $3,500 as the average wafer cost, the individual die cost for a 1 ern-die, with 0.8 defects per square centimeter, on an 8-inch wafer = $3,500 I (269 x 0.49) = $26.55. Before the chip is ready to be used in a computer, further costs or testing, pack- aging, retesting, and shipping must be invested. And, of course, these are just the vari· able costs of the manufacturing processes (see Equation 2.1). The fixed costs of research and development (R&D), capital expenditures, personnel, and marketing add considerably more. Note that if the die size is increased to 2.25 square centimeters, the painful result for the 200 nun wafer is (107 x 0.24) = only 25 good ones. This reduced number makes the individual costs considerably higher at $14Q-nearly five times higher. Die designers realize that they cannot easily influence the daily costs of run- ning the factory and controlling the yield from individual CMOS operations. But they can influence the die area and strive to reduce it by considering the functions that are included on the die and the number of 110 pins. 5.12.4 Additional Costs of Testing the Die after Processing and Slicing Producing the dice is one set of costs. However, the dice must be tested after the CMOS processing and subsequent slicing up procedures to ensure customer satis- faction. A few dice will be damaged just from testing. So, again, since the bad dice have to be tested before it is known they are bad, the good dice must bear this cost. Cost to test a die = .c:0stof testing per hour X average test time. die yield after the test (5.5) In Patterson and Hennessy's 1996examples, the quoted testing costs vary from $50 to $500per hour depending on the type of test needed. Testing time also varies with die complexity, from 5 to 90 seconds. Expensive microprocessors with many pins need a longer test with more expensive equipment. 5.12.5 Cost of Packaging The next set of costs involves the back-end packaging of the finished die.These costs are determined by the packaging material and its design, the number ofpins, and the die size.The cost of the packaging material depends in large part on the desired heat dissipation rate from the operating IC when it is being used in the computer. For example, in 1996 data: • A plastic quad flat pack (PQFP) that will dissipate less than 1watt of heat from a 1 crn''dle with 208 pins will cost about $2. • Alternatively, a ceramic pin grid array (PGA) might have 300 to 600 pins for a larger 2 cm 2 die dissipating much more heat, and the costs will rise to as much as $30 to $70 per package. 2'2 Semiconductor Manufacturing Chap. 5 Table 5.5 includes examples: TABLE 5.5 Package and Test Costs (Courtesy of MIPS Technologies) Package type Pin count Package cost ($) Testtime (sec) TeSI cost per hour ($) POFP <220 12 10 300 PQFP <300 20 10 320 CeramicPGA <300 30 10 320 CeramicPGA <400 4<) 12 34<) CeramicPGA <450 50 13 360 CeramicPGA <500 60 14 380 CeramicPGA >500 70 15 400 The data for die area and different packages can be seen in some recent products (Table 5.6), TABLE 5.6 Microprocessors and Characteristics for Some Products with Wafer Cost Microprocessor Die area (mm 2 ) Pins Estimated wafer cost ($) Package MIPS 4600 77 208 3.200 POFP PowerPC600 85 24<J 3,400 POFP HP71 XO 196 504 2,800 CeramicPGA Digit.a121064A 166 431 4,000 CeramicPGA SuperSPARC/60 256 293 4,000 CeramicPGA Finally, there is the cost for assembly labor, bonding pads to pins, bum-in testing, and further failure analysis. Therefore the total costs are computed in Table 5.7 for a 200 mm wafer, a wafer yield of95%,and 0: = 3: TABLE 5.7 Total Costs for Some Microprocessors around the Year 1995 Final cost including testing Type Die yield Dice per wafer Good chips Cost per good die ($) packing ($) MIPS 4600 0,4787 PowerPC 603 0.4495 HP71 x 0 0.2102 Digital21064A 0.2535 SuperSPARCl60 0.1492 357 321 128 154 94 171 144 27 39 14 18.71 23.53 103.62 101.95 282.35 32.45 45.51 181.55 157.08 318.31 5.13 Management of Technology 213 So for one example in detail, the MIPS 4600 has a die area of 77 rnm •For a95% wafer yield and alpha equal to 3,the die yield comes out to be 0.4787. •The number of dice per wafer, assuming a 200 mm wafer, is 357. Thus, the number of good chips per wafer is 171. • In Table 5.6, MIPS 4600 wafers cost $3,200 each. •From each wafer, the price for a good chip is thus $18.71. •The physical package for this chip costs $12. •There are also labor costs: the average testing-time cost per good chip is$0.833 and the average packaging-time cost is $0.907.These testing and assembly- time costs add up to $1.74. Altogether, the costs are (18.71 + 12.00 + 1.74) = $32.45. The costs for other processors are much higher. The Sun SPARC/6U is given as $31K31.Also these are manufacturing costs not retail costs. In future years, costs willbe lower-much lower! However, the basic idea will still hold that each failure makes the good dicecost more and the costs escalate with die size. 5.12.6 Conclusion: Relation to Integrated CAD/CAM It is worth summarizing with some key conclusions from these calculations. 5.12.6.1 Design • With 0: = 3, the cost of the die is a function of the fourth power of the die area. Therefore, the circuit designer's final choice of die area is dramatically impor- tant to die cost. • This die area depends on a variety of issues including the specific technology being used, the number of functions and hence transistors on the chip, and the number of pins on the border of the die. 5.12.6.2 Manufacturing The manufacturing process itself dictates the wafer cost, the wafer yield, n, the defects per unit area, and the final integrated yield after packaging and testing. In the next section, the history of the semiconductor industry reinforces the fact that design and manufacturing are of equal importance in the "best practices" for the semicon- ductor industry. 5.13 MANAGEMENT OF TECHNOLOGY 5.13.1 Historical Trends in the Business The semiconductor industry has gone through tremendous structural and technolog- ical change over the past three decades-since, say, the first 1K DRAM 1103 chip made by Intel in 1970.Once a small market dominated by a few companies in Boston, [...]... companies impames Intel NEC Motorola Hitachl Toshiba Texas Instruments Samsung Fujitsu 13.17 TABLE 29 10. 58 -, -3 -12 -21 -9 -26 -19 -20 24 -7 8. 44 8. 06 7. 98 7.09 8. 73 9.14 10. 08 7 .83 8. 33 '.20 5.54 4.51 5.27 50S-Thomson Industry totals 1995 96 growth(%) 16.94 11.31 Mitsubishi 5.19 APPENDIX 2: Cost Model 8 64~Mb DRAM (Courtesy 1996 revenue ($B) 1995 revenue ($B) 4.20 3.39 4.20 151.27 140.69 Variables in... Test Seconds Per Die) 8 A B 100.00 C 0.35 D 1650.00 E 155,494.00 F 1.00 G H 0.111 = I = (0 75*pi(AlZ) =J(DII) 18. 00 "Z*IO"6)!E 242.00 6 .81 K 120.0 =L=1I(#*1)/3600) 0. 08 M""(KIL)/I 6.00 =N=(J+M) 12 .81 =O==2.7 18" «(-H*G)*E) 73 =P==N*IOOfO 17. 48 TABLE 5.11 Assemblv Data Material cost/sorted die + package cost Number of package pins Assembly yield (%) Cost per assembled die ($) ($) Q 0. 48 R 44 S =T=(P+Q)/S*loo... Deep Uv Deep UV refined ExtremeUV X-ray SCALPEL (electron beam) (nanometers) sire (nanometers and micmn~) 365 350 (0.35 micron) 2 48 250 (0.25 micron) 193 13Q 180 (0.13 0. 18 10-20 30-100 (0.03-0.1 micron) 0.Q1~1 20-100 (0.02-0.1 micron) 80 (0. 08 micron) micron) 2 18 Semiconductor Manufacturing hr,tv"arofICprUUlIni')!1 Chap 5 ZO!4 - _ Research required ~ Development under way c::::::J Qualification/preproduction... K M 1995 Fabrication of microelectronic devices In Manufacturing Engineering and Technology, edited by Serape Kalpakjian Reading, MA: Addison Wesley Leachman, R C.,and D.A Hodges 1996 Benchmarking semiconductor manufacturing. IEEE Transactions on Semiconductor Manufacturing 9 (2):1 58- 169 Leachman, R c., and D A Hodges 19 98 Benchmarking semiconductor manufacturing Third Report, Engineering Systems Research... packaged units that pass all device specifications 5.15 REFERENCES Bohr, M.19 98 Silicon trends and limits for advanced ACM 41 (3) :80 -87 Braun, A E 1999 Aluminum August, 58- 66 Brodersen, persists DeJule, 48- 52 of the International, R W 2000 R A 1 980 Microelectronics: R 1999a Next generation DeJule, R.1999b Einspruch, Communications age dawns Semiconductor Campbell, S A 1996... Semiconductor 230 Spencer, W 1 19 98 Regents' Lecture Series, University videotape at Haas School of Business) Manufacturing of California, Chap 5 Berkeley (available on Wolf, S" and R N Tauber 1 986 Silicon processing for the VLSI era Vol I, Process technology Sunset Beach, CA: Lattice Press Zuhlehner, w., and D Huber Springer Verlag 5.16 1 982 Czochralski grown silicon crystals, Vol 8 New York: BIBLIOGRAPHY... Formula Prolil(8percent) Constructed FMV 5.20 REVIEW Adders =AB=O.15"'AA =AC=(AA+AB)*O.10 =AD=(AA+AB+AC)"'O. 08 =AE=(AA+AB+AC+AD) expense (15 percent) expense (10 percent) 3.70 2 .83 2.49 33.66 MATERIAL 1 Calculate that the final cost of a packaged Power PC603 chip is $45.51 and that the packed cost of a SuperSPARCl60 chip is 3 18. 31 Assume the 1996 data of Patterson and Hennessy (1996b) 2 What manufacturing. ..Semiconductor Manufacturing 21 Chap 5 Texas, and California, semiconductors became an intensely competitive global industry by the 198Os,with Japanese producers steadily usurping the market lead In the 1 980 s the u.s semiconductor industry's competitive slide was caused in large part by persistent manufacturing weaknesses The slide was initially blamed on... integrated design and manufacturing will persist across several companies that cover the spectrum from "IP to fab." As summarized by Macher and associates (19 98) , the fabless design studio is more a North American model with roughly 500 such companies in the United States in 19 98, while the stare-or-the-art foundries that support them are located in Asia The Taiwan Semiconductor Manufacturing Company... Guilford Press The remaking of the Us semiconductor Allgarten, S 1 983 State of the aT1:A photographic New York:TIcknor and Fields Press history of integrated circuits New Haven and Beadle, W E.,l C C Tsai, and R D Plummer, integrated circuit technology New York: Wiley eds, 1 985 Quick reference manual for silicon Hodges, D., and H Jackson 1 988 Analysis and design of digital integrated circuits, 2d ed New . 4600 0,4 787 PowerPC 603 0.4495 HP71 x 0 0.2102 Digital21064A 0.2535 SuperSPARCl60 0.1492 357 321 1 28 154 94 171 144 27 39 14 18. 71 23.53 103.62 101.95 282 .35 32.45 45.51 181 .55 157. 08 3 18. 31 5.13. (0.25 micron) 13Q 180 (0.13 0. 18 micron) 30-100 (0.03-0.1 micron) 20-100 (0.02-0.1 micron) 80 (0. 08 micron) "Siliconcsubslr3te Reduction Condenser optics Laser 2 18 Semiconductor Manufacturing Chap circuit Bonding wires Molded plastb Assembled Leadframe 2 08 Semiconductor Manufacturing Chap. 5 5.12 COST OF CHIP MAKING' 5.12.1 Overview Manufacturing involves many processing steps, and each