Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C035 Finals Page 732 24-9-2008 #39 732 Handbook of Algorithms for Physical Design Automation 12. D.O. Ou ma, D.S. Boning, J.E. Chung, W. Easter, V. Savene, S. Misra, and A . Crevasse, Characterization and modeling of oxide chemical-mechanical polishing using planarization length and pattern density concepts, IEEE Transactions on Semiconductor Manufacturing, 15(2), 232–244, 2002. 13. A. Srivastava, D. Sylvester , and D. Blaauw, Statistical Analysis and Optimization for VLSI: Timing and Power, Springer , New York, 2005. 14. W. Maly,Computer-aided designforVLSI circuit manufacturability, Proceedings of IEEE, 78(2), 356–390, Feb. 1990. 15. W. Maly and J. Deszczka, Yield estimation model for VLSI artwork evaluation, Electr onics Letters, 19(6), 226–227, 1983. 16. A.V. Ferris-Prabhu, Role of defect size distributions in yield modelling, IEEE Transactions on Electron Devices, ED-32(9), 1727–1736, 1985. 17. C.H. Stapper, Modeling of integrated circuit defect sensitivities, IBM Journal of Resear ch and Develop- ment, 27(6), 549–557, 1983. 18. G.A. Allan and A.J. Walton, Hierarchical critical area extraction with the EYE tool, in Proceedings of the IEEE Workshop Defect Fault Tolerance in VLSI Systems, pp. 28–36, No v. 1995. 19. W. Maly, H.T. Heineken, and F. Agricola, A simple new yield model, Semiconductor International, pp. 148–154, July 1994. 20. I. Bubel, W. Maly, T. Waas, P.K. Nag, H. Hartmann, D. Schmitt-Landsiedel, and S. Griep, AFFCCA: A tool for critical area analysis with circular defects and lithography deformed layout, in Proceedings of the IEEE International Workshop on Detect and Fault Tolerance in VLSI Systems, pp. 19–27, I EEE Computer Society Press, 1995. 21. H. Levinson, Principles of Lithography, 2nd edn., SPIE Press, Bellingham, WA, 2005;or Microlithography, Science and Technology, 2nd edn. K. Suzuki and B.W. Smith, Eds., C RC Press, Boca Raton, FL, 2007. 22. C.G. Willson, Organic resist materials, Introduction to Microlithography, 2nd edn., L. Thompson, C.G. Willson, and M. Bowden, Eds., American Chemical Society, Washington, DC, 1994. 23. The International Technology Road Map for Semiconductors (http://www.itrs.net/). 24. G. Moore, Cramming more component s onto integrated circuits, Electronics, 38, 114–117, 1965. 25. M. Bohr , Intel’s 65 nm Process T echnology, Intel Developer Forum, Sept. 8, 2004, available at http://www.intel.com/technology/silicon/65 nm_technology.htm or ftp://download.intel.com/technology/ silicon/IRDS002_65 nm_logic_process_100_percent.pdf. 26. F.M. Schellenberg, Resolution enhancement techniques and mask data preparation, EDA for IC Imple- mentation, Circuit Design, and Process Technology, L. Scheffer, L. Lavagno, and G. Martin, Eds., CRC Press, Boca Raton, FL, 2006. 27. B.J. Lin, I mmersion lithography and its impact on semiconductor manufacturing, Journal of Microlitho- graphy Microfabrication and Microsystems, 3, 377–395, 2004. 28. J.D. Jackson, Classical Electrodynamics, 3rd edn., J. Wiley, Ne w York, 1999. 29. A.K.K. Wong, Optical Imaging in Projection Microlithography, SPIE Press, Bellingham, WA, 2005. 30. R.N. Bracewell, The Fourier Transform and Its Application, 3rd edn., McGraw Hill, New York, 1999; or J.W. Goodman, Introduction to Fourier O ptics, 3rd edn., Roberts & Co, Greenwood Village, CO, 2005. 31. C.L. Tang, Nonlinear optics, The Handbook of Optics, Part II: Devices, Measurements, and Properties, M. Bass, editor in chief, McGraw Hill, New York, 1995. 32. J.W. Cooley and J.W. Tucky, An algorithm for the machine calculation of complex Fourier s eries, Mathematics of Computation, 19(90), 297–301, April 1965. 33. E. B righam, The Fast Fourier Transform and Its Applications, Prentice Hall, New York, 1988. 34. W.H. Press, S.A. Teukolsky, W.T. Vetterling, and B.P. Flannery, Numeri cal Recipes in C++:TheArtof Scientific Computing, 2nd edn., Cambridge University Press, New York, Feb. 2002. 35. A.K.K. Wong, Resolution Enhancement Techniques in Optical Lithography, SPIE Press, Bellingham, WA, 2001. 36. M.D. Levenson, Wavefront engineering for photolithography Physics Today, 46(7), 28–36, 1993. 37. Selected Papers on Resolution Enhancement Techniques in Optical Lithography, F.M. Schellenberg, Ed., SPIE Press, Bellingham, WA, 2004. 38. O. Otto, J.G. Garofalo, K.K. Low, C.M. Yuan, R.C. Henderson, C. Pierrat, R.L. Kostelak, S. Vaidya, and P.K. Vasudev, Automated optical proximity correction: A rules-based approach, in Optical/Laser Microlithography VII, Proceedings of SPIE, vol. 2197, p. 278–293, 1994. Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C035 Finals Page 733 24-9-2008 #40 Modeling and Computational Lithography 733 39. N. Shamma, F. Sporon-Fiedler, and E. Lin, A method for the correction of proximity effects in optical projection lithography, in Interface 91, P roceedings of the 1991 KTI Microelectronics Seminar, pp. 145– 156 San Jose, CA, 1991. 40. F.M. Schellenberg, H. Zhang, and J. Morro w, SEMATECH J111 project: OPC validation, in Optical Microlithography XI, Proceedings of SPIE, v ol. 3334, pp. 892–911, 1998. 41. N.B. Cobb, Fast optical and process proximity correction algorithms for integrated circuit manufacturing, Ph.D. Dissertation, University of California, Berkeley, California, 1998. 42. M. Rieger and J. Stirniman, Using behavior modeling for proximity correction, in Optical/Laser Microlithography VII, Proceedings of SPIE, vol. 2197, pp. 371–376, 1994. 43. W. Maurer and F.M. Schellenberg, Adv anced lithographic masks, Handbook of Photomask Manufacturing Technology, S. Rizvi, ed., CRC Press, Boca Raton, FL 2005. 44. J. Garofalo, C. Biddick, R.L. Kostelak, and S. Vaidya, Mask assisted off-axis illumination technique for random logic Journal of Vacuum Sci ence and Te chnology B, B11, 2651–2658, 1993. 45. J.F. Chen and J.A. Matthews, Mask for photolithography, US Patent No. 5,242,770 (filed Jan. 16, 1992; issued Sept. 7, 1993). 46. Handbook of Photomask Manufacturing Technology, S. Rizvi, Ed., C RC Press, Boca Raton, FL 2005. 47. B. E ynon Jr. and B. Wu, Photomask Fabrication Technology, McGraw Hill, New York, 2005. 48. Masato Shibuya, “ ” [Projection master for use with transmitted illumination], (A) 57–62052, (B) 62–50811 [Japan Patent Office Laid-open Patent Publi- cation (A) Showa 57-62052, Patent Publication (B) Showa 62–50811] (filed Sept. 30, 1980; published Apr. 14, 1982, issued Oct. 27, 1987). 49. M.D. Levenson, N.S. Visw anathan, and R.A. Simpson, Improving resolution in photolithography with a phase-shifting mask, IEEE Transactions Electr o n Devices ED-29, 1828–1836, 1982. 50. M.D. Levenson, D.S. G oodman, S. Lindse y, P.W. Bayer, and H.A.E. Santini, The phase-shifting mask II: Imaging simulations and submicrometer resist exposures, IEEE Transactions on Electr on Devices, ED-31, 753–763, 1984. 51. K. Ooi, S. Hara, and K. Koyama, Computer aided design software for designing phase shifting masks, Japanese J ournal of Applied Physics, 32, 5887–5891, 1993. 52. L.W. Liebmann, G.A. Northrop, J. Culp, L. Sigal, A. Barish, and C.A. Fonseca, Layout optimization at the pinnacle of optical lithography, in Design and Process Integr ation for Microelectronic Manufacturing, Pr oceedings of SPIE, v ol. 5042, pp. 1–14, 2003. 53. L. Liebmann, J. Lund, F.L. Heng, and I. G raur, Enabling alternating phase shifted mask designs for a full logic gate level: Design rules and design rule checking, in Proceedings of the 38th Design Automation Conference, pp. 79–84, ACM, N ew York, 2001. 54. L. Liebmann, J. Lund, F.L. Heng, and I. G raur, Enabling alternating phase shifted mask designs for a full logicgatelevel,Journal of Microlithography, Microfabrication, and Microsystems, 1, 31–42, 2002. 55. Y C. Ku, E.H. Anderson, M.L. Schattenburg, and H.I. Smith, Use of a pi-phase shifting x-ray mask to increase the intensity slope at feature edges, Journal of Vacuum Science and Technology B, B6, 150–153, 1988. 56. Y. Saito, S. Kawada, T. Yamamoto, A. Hayashi, A. Isao, and Y.Tokoro, Attenuated phase-shift mask blanks with oxide or oxinitride of Cr or MoSi absorptive shifter, in Photomask and X-Ray Mask Technology, Pr oceedings of SPIE, v ol. 2254, pp. 60–63, 1994. 57. H. Jinbo and Y. Yamashita, Improvement of phase-shifter edge line mask method, Japanese Journal of Applied Physics, 30, 2998–3003, 1991. 58. H.Y. Liu, L. Karklin, Y.T. Wang, and Y.C. Pati, Application of alternating phase-shifting masks to 140- nm gate patterning: II. Mask design and manufacturing tolerances, in Optical Microlithography XI, Pr oceedings of SPIE, v ol. 3334, pp. 2–14, 1998. 59. C. Spence, M. Plat, E. Sahouria, N . Cobb, and F. Schellenberg, Integration of optical proximity correction strategies in strong phase shifter design for poly-gate layer, in 19th Annual Symposium o n Photomask Technolo gy, Proceedings of SPIE, vol. 3873, pp 277–287, 1999. 60. C. Mack, Characterizing the process window of a double exposure dark field alternating phase shift mask, in Design, Pr ocess Integration and Characterization for Microelectronics, Proceedings of SPIE, vol. 4692, pp. 454–464, 2002. 61. A.K.K. Wong (Ed.) Modified illumination, in Resolution Enhancements Techniques in O ptical Lithogra- phy, SPIE Press, Bellingham, WA, 2001. Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C035 Finals Page 734 24-9-2008 #41 734 Handbook of Algorithms for Physical Design Automation 62. N. Shiraishi, S. Hirukawa, Y. Takeuchi, and N. Magome, New imaging technique for 64M-DRAM in Optical/Laser Microlithography V, Proceedings of SPIE, vol. 1674, pp. 741–752, 1992. 63. F.M. Schellenberg and L. Capodieci, and B. Socha, Adoption of OPC and the Impact on Design and Layout, Pr oceedings of the 38th Design Automation Conference, ACM, New York, 2001, pp. 89–92. 64. M. Burkhardt, A. Yen, C. Progler, and G. Wells, Illuminator design for printing regular contact patterns, Microelectronic Engineering, 41, 91, 1998. 65. E. Barouch, S.L. Knodle, S.A. Orszag, and M. Yeung, Illuminator optimization for projection printing, in Optical Microlithography XII, Proceedings of SPIE, vol. 3679, pp. 697–703, 1999. 66. A.E. Rosenbluth, S. Bukofsky, M. Hibbs, K. Lai, R.N. Singh, A.K. Wong, Optimum mask and source patterns for printing a given shape, Journal of Microlithography, Microfabrication, and Microsystems,1, 13–30, 2002. 67. Y. Granik, Source optimization for image fidelity and throughput, Journal of Microlithography, Microfabrication, and Microsystems, 3, 509–522, 2004. 68. Y. Granik and N. Cobb, New process models for OPC at sub-90 nm nodes, in Optical Microlithog raphy XVI, Proceedings of SPIE, vol. 5040, pp. 1166–1175, 2003. 69. J.F. C h en, J.S. Petersen, R. Socha, T. Laidig, K.E. Wampl er, K. Nakagawa, G. Hughes, S. MacDonald, and W. Ng, Binary halftone chromeless PSM technology for λ/4 optical lithography, in Optical Microlithography XIV, Proceedings of SPIE, vol. 4346, pp. 515–533, 2001. 70. D.J. Van Den B roeke, J.F. Chen, T. Laidig, S. Hsu, K.E. Wampler, R.J. Socha, and J.S. Petersen, Complex two dimensional pattern lithography using chromeless phase lithography (CPL), Journal of Microlithography, M icrofabrication, and Microsystems, 1, 229–242, 2002. 71. S.R.J. Brueck and A.M. Biswas, Extension of the 193-nm optical lithography to the 22-nm half pitch node, in Optical Microlithog raphy XVII, Proceedings of SPIE, vol. 5377, pp. 1315–1322, 2004. 72. S.R.J. Brueck, There are no fundamental limits to optical lithography International Trends in Applied Optics, A. Guenther, Ed., SPIE Press, Bellingham, WA, 2002. 73. S. Asai, I. Hanyu, and M. Takikaw a, Resolution limit for optical lithography using polarized light illumination, Japanese Journal of Applied Physics, Part I, 32, 5863–5866, 1993. 74. S.H. Jeon, B.D. Cho, K.W. Lee, S.M. Lee, K.H. Biak, C.N. Ahn, and D.G. Yim, Study on elliptical polarization illumination effects for microlithography, Journal of Vacuum Science and Technology B, B14, 4193–4198, 1996. 75. Z.M. Ma and C.A. Mack, Impact of illumination coherence and polarization on the imaging of attenuated phase shift masks, in Optical Micr olithoraphy XIV, Pr oceedings of SPIE, vol. 4346, pp. 1522–1532, 2001. 76. K. Adam and W. Maurer, Polarization effects in immersion lithography, Journal of Microlithography, Microfabrication, and Microsystems, 4, 031106, 2005. 77. R. Wang, W. Grobman, A. Reich, and M. Thompson, Polarized phase shift mask: Concept, design, and potential advantages to photolithography process and physical design, in 21st Annual BACUS Symposium on Photomask Technology, P roceedings of SPIE, vol. 4562, pp. 406–417, 2002. 78. M. Rieger and J. Stirniman, Using behavior modelling for proximity correction, in Optical/Laser Microlithography VII, Proceedings of SPIE, vol. 2197, pp. 371–376, 1994. 79. N. Cobb and Y. Granik, New concepts in OPC, in Optical Microlithography XVII, Proceedings of SPIE, vol. 5377, pp. 680–690, 2004. 80. J. Word and N. Cobb, Enhanced model based OPC for 65 nm and below, 24th Annual BACUS Symposium on Photomask Technology, Proceedings of SPIE, vol. 5567, pp. 1305–1314, 2004; J. Word, J.A. Torres, and P. LaCour, Advanced layout fragmentation and simulation schemes for model based OPC, Op tic al Microlithography XVIII, Proceedings of SPIE, vol. 5754, pp. 1159–1168, 2004. 81. N.B. Cobb and W. Maurer, Flows for model-based layout correction of mask proximity effects, in 23r d Annual BACUS Symposium on Photomask Technology, Pr oceedings of SPIE, vol. 5256, pp. 956–964, 2003. 82. M. Gesley, Pattern generation, Photomask Fabrication Technology, B. Eynor, Jr. and B. Wu, Eds., McGraw Hill, New York, 2005. 83. N. Cobb and D. Dudau, Dense OPC and verification for 45 nm, in Optical Micr olithography XIX, Pr oceedings of SPIE, v ol. 6154, p. 615401, 2006. 84. J. Kreuzer, US Patent 6,836,380 (filed Feb. 14, 2003; issued Dec. 28, 2004). 85. Litel Corporation (http://www.opticalres.com/). 86. Litel Corporation (http://www.litel.net). Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C035 Finals Page 735 24-9-2008 #42 Modeling and Computational Lithography 735 87. K.K.H. To h and A.R. Neureuther, Identifying and monitoring effects of lens aberrations in projection printing, in Optical Microlithography VI, Proceedings of SPIE, vol. 772, pp. 202–209, 1987. 88. H.H. Hopkins, On the diffraction theory of optical images, Proceedings Royal Society London Series A, 217, 408–432, 1953. 89. A.K.K. Wong, Optical Imaging in Projection Microlithography, SPIE Press, Bellingham, WA, 2005. 90. K.S. Yee,Numericalsolution of initial boundaryvalueproblems involving Maxwell’sequationsin isotropic media, IEEE Tr ansactions on Antennas and Propagation, 14, 302–307, 1966. 91. A. Ta flove and S.C. Hagness, Computaional Electrodynamics: The Finite-Differ ence Time-Domain Method, 3rd edn., Artech House, Boston, MA, 2005. 92. www.fdtd.org (For more references on t he FDTD method). 93. A. Erdmann, Modelling and simulation, Handbook of Photomask Manufacturing Technology,S.Rizvi, Ed., CRC Press, Boca Raton, FL 2005. 94. E. Palik, Handbook of Optical Constants of Solids, Vols. 1–4, Academic Press, San Diego, C A, 1991. 95. Computational Electrodynamics: The Finite Difference Time-Domain Method, 3rd edn., A. Taflove and S.C. Hagness, Eds., Artech House, Boston, MA, 2005, Chapter 7. 96. A.K.K. Wong and A.R. Neureuther, Rigorous three dimensional time-domain finite difference electro- magnetic simulation, IEEE Transactions on Semiconductor Manufacturing, 8, 419–431, 1995. 97. T.V. Pistor, Accuracy issues in the finite difference time domain simulation of photomask scattering, in Optical Microlithography XIV, Proceedings of SPIE, vol. 4346, pp. 1484–1491, 2001. 98. M.G. Moharam and T.K. Gaylord, Rigorous coupled-wave analysis of planar grating diffraction, Journal of the Optical Society of America, 71, 811, 1981. 99. A. Estroff, Y. Fan, A. Bourov, F. Cropanese, N. Lafferty, L. Zavyalova, and B. Smith, Mask Induced polarization, in Optical Microlithogr aphy XVII, Proceedings of SPIE, vol. 5377, pp. 1069–1080, 2004. 100. D. Nyyssonen, The theory of optical edge detection and imaging of thick layers, Journal of the Optical Society of America, 72, 1425, 1982. 101. C.M. Yuan, Calculation of one-dimensional lithographic aerial images using the vector theory, IEEE Transactions on Electr o n Devices, ED-40, 1604, 1993. 102. A. Erdmann, P. Evanschitzky, G. Citarella, T. Fuehner, and P. De Bisschop, Rigorous mask modeling using waveguide and FDTD methods: An assessment for typical hyper NA imaging problems, in Pho- tomask and Next-Generation Lithography Mack Technology XIII, Proceedings of SPIE, vol. 6283, 628319, pp. 1–11, 2006. 103. K. Adam and A. Neureuther, Algorithmic implementations of domain decomposition methods for the diffraction simulation of advanced photomasks, Optimal Microlitho graphy XV, Proceedings of SPIE,vol 4691, pp. 107–124, 2002; and K. Adam and A.R. Neureuther, Domain decomposition methods for the rapid electromagnetic simulation of photomask scattering, Journal of Micr olithography, Microfabrication and Microsystems, 1, 253–269, 2002. 104. K. Adam, Modeling of electromagnetic effects from mask topography at full-chip scale, in Optical Microlithography XVIII, P roceedings of SPIE, vol. 5754, pp. 498–505, 2004. 105. T.W. Ebbesen, H.J. Lezec, H.F. Ghaemi, T. Thio, and P.A. Wolff, Extraordinary optical transmission through sub-wav elength hole arrays, Nature, 391, 667–669, 1998. 106. H. Raether, Surface Plasmons, Springer , Berlin, Germany, 1988. 107. F.M. Schellenberg, K . Adam, J. Matteo, and L. Hesselink Electromagnetic phenomena in advanced photomasks, Journal of Vacuum Science and Technology , 23(6), 3106–3115, 2005. 108. A. Neureuther and C. Mack, Optical lithography modeling, Handbook of Microlithography, Micromachin- ing, and Microfabrication, Vol 1: Microlithopgraphy, P. Rai-Choudhury, Ed., SPIE Optical Engineering Press, Bellingham, WA, 1997. 109. C.A. Mack, Analytical expression for t he standing wave intensity in photoresist, Applied Optics, 25(12), 1958–1961, 1986. 110. R.A. Ferguson, C.A. Spence, E. Reichmanis, a nd L.F. Thompson, Investigation of the exposure and bake of a positive-acting resist with chemical amplification, in Advances in Resist Technology and Processing VIII, Proceedings of SPIE, vol. 1262, pp. 412–242, 1990. 111. F.H. Dill, W.P. Hornberger, P.S. Hauge, and J.M. Shaw, Characterization of positive photoresist, IEEE Transactions on, E lectron Devices, ED-22, 456–464, 1975. 112. N. Cobb, A. Zakhor, a nd E. Miloslavsky, Mathematical and CAD framework for proximity correction, i n Optical Microlithography IX, Proceedings of SPIE, vol. 2726, pp. 208–222, 1996. Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C035 Finals Page 736 24-9-2008 #43 736 Handbook of Algorithms for Physical Design Automation 113. N. Cobb, A. Zakhor, M. Reihani, F. Jahansooz, and V. Raghavan, Experimental results on optical proximity correction with variable threshold resist model, in Optical Microlitho graphy X, Proceedings of SPIE, vol. 3051, pp. 458–468, 1997. 114. A Wong, R. Ferguson, S. Mansfield, A. Molles, D. Samuels, R. Schustr, and A. Thomas, Level-specific lithography optimization for 1 Gb DRAM, IEEE Transactions on Semiconductor Manufacturing, 13(1), 76–87, 2000. 115. J. Stirniman and M. Rieger, Optimizing proximity correction for wafer f abrication processes, in 14th Annual BACUS Symposium on Photomask Technology and Management, Proceedings of SP IE, vol. 2322, pp. 239–246, 1994. 116. J.W. Bossung, Projection printing characterization, in Semiconductor Microlithography II, Proceedings of SPIE, vol. 100, pp. 80–84, 1977. 117. B.J. Lin, Partially coherent imaging in two dimensions and the theoretical limits of projection printing in microfabrication, IEEE Transactions on Electron Devices, ED-27, 931–938, 1980. 118. K.H. Kim, K. Ronse, A. Yen, and L. Van den Hove, Feasibility demonstration of 0 18 µm and 0.13 µm optical projection lithography based on CD control calculations, in 1996 Symposium on VLSI Technology, Digest of Technical Papers, pp. 186–187, 1996. 119. C. Mack. Lithography simulation in semiconductor manufacturing, in Advanced Microlithography Technologies, Proceedings of SPIE, vol. 5645, pp. 63–83, 2005. 120. S. Shang, Y. Granik, N. Cobb, W. Maurer, Y. Cui, L. Liebmann, J. Oberschmidt, R. Singh, and B. Vampatella, Failure prediction across process window for robust OPC, in Optical Microlithography XVI, Proceedings of SPIE, vol. 5040, pp. 431–440, 2003. 121. W. Maurer, Mask specifications for 193-nm lithography, in 16th Annual BACUS Symposium on Photomask Technology and Management, Pr o ceedings of SPIE, vol. 2884, pp. 562–571, 1996. 122. C. Mack, Mask linearity and the mask error enhancement f actor, Microlithography World, pp. 11–12, W inter 1999. 123. F.M. Schellenberg, V. Boksha, N. Cobb, J.C. Lai, C.H. Chen, and C. Mack, Impact of mask errors on full chip er ror budgets, in Optical Microlithography XII, Pr oceedings of SPIE, vol. 3679, pp. 261–275, 1999. 124. F.M. Schellenberg and C. Mack, MEEF in theory and practice, in 19th Annual Symposium on Photomask Technolo gy, Proceedings of SPIE, v ol 3873, pp. 189–202, 1999. 125. N. Cobb and Y. Granik, Model-based OPC using the MEEF matrix, in 22nd Annual BACUS Symposium on Photomask Technology, P roceedings of SPIE, vol. 4889, pp. 1281–1292, 2002. 126. F.M. Schellenberg, O. Toublan, N. Cobb, E. Sahouria, G. H ughes, S. MacDonald, C. West, OPC beyond 0.18 µm: OPC on PSM Gates, Optical Microlithography XIII, Proceedings of SPIE, vol. 4000, pp. 1062– 1069, 2000. 127. J.A.T. Robles, Integrated circuit layout design methodology for deep sub-wavelength processes. Ph.D. Dissertation, OGI School of Science and Engineering, Beaverton, OR, July 2005. 128. Z. Ren, W. Zhang, and J. Falbo, Computation of parasitic capacitances of an IC cell in accounting for photolithography effect, in 6th International Confer ence on Computational Electromagnetics (CEM2006) Pr oceedings, pp. 163–164, VDE Verlag, Berlin, Germany, 2006. 129. See J.A. Mucha, D.W. Hess, and E.S. Aydil, Plasma etching, Introduction to Microlithography, 2nd edn., L. Thompson, C.G. W illson, and M. Bowden, Eds., American Chemical Society, Washington, DC, 1994. Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C036 Finals Page 737 10-10-2008 #2 36 CMP Fill Synthesis: A Survey of Recent Studies Andrew B. Kahng and Kambiz Samadi CONTENTS 36.1 Chemical–Mechanical Polishing 737 36.2 Impactson Interconnect Design and Manufacturing 739 36.3 Characterization and Modeling Approaches 741 36.3.1 General CMP ProcessModels 741 36.3.2 Oxide CMP Modeling 742 36.3.3 Copper CMP Modeling 743 36.3.4 STI CMP Modeling 745 36.4 Density Analysis Methods 747 36.4.1 Fixed-Dissection Regime 748 36.4.2 Multilevel Density Analysis 748 36.5 CMP Fill Synthesis Methods 749 36.5.1 Density-Driven Fill Synthesis 749 36.5.1.1 LP-Based and Monte-Carlo-Based Methods 751 36.5.1.2 Iterated Monte-Carlo and Hierarchical Methods 752 36.5.1.3 Timing-DrivenFill Synthesis 753 36.5.2 Model-Based Fill Synthesis 754 36.5.3 Impact of CMP Fill on Interconnect Performance 754 36.5.3.1 Fill Patterns 755 36.5.3.2 CMP Fill and Interconnect Capacitance 757 36.5.4 STI Fill Insertion 758 36.6 Design Flows for Fill Synthesis 760 36.6.1 RC Extraction and Timing Closure 761 36.6.2 Impact of Spatial Variation 762 36.6.3 Topography-Aware Optical Proximity Correction 763 36.6.4 Intelligent CMP Fill Synthesis 763 36.7 Conclusion 765 References 765 36.1 CHEMICAL–MECHANICAL POLISHING Chemical–mechanical polishing (CMP) is the planarizing technique of choice to satisfy the local and global planarity constraints imposed by today’s advanced lithography methods [36,58]. As device geometries scale, there is an inevitable n eed for b etter planarization of the multilevel interconnect structures. Older planarizing methods,such as flowingoxide layers, spin-onglass (SOG), and reverse etchback (REB) can no longer meet the lithographic and other requirements of modern multilevel metallization processes [52]. 737 Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C036 Finals Page 738 10-10-2008 #3 738 Handbook of Algorithms for Physical Design Automation Pad Wafer Conditioner Slurry FIGURE 36.1 Thin film formation in SOG method. (Modified from Toan, N.N., Spin-on-glass materials and applications in advanced IC t echnologies, Ph.D. Dissertation, Universiteit Twente, Netherlands, 1999.) SOG is a method that consists of coating the surface of a particular layer with SOG materi- als. These materials can be categorized into three different groups: (1) silicate-based compounds, (2) organosilicon compounds,and (3) dopant-organiccompounds. In SOG, the silicon wafer must be cleaned before coating. The wafer is placed on a spinner and approximately 1 mL of SOG material is dropped on the center of the wafer. Then the carrier holding the wafer (Figure 36.1) is rotated at several thousand cycles per minute to create a thin layer of SOG material on the wafer. In most cases, a film thickness between 50 and 500 nm will result. Controlling the thickness is a matter of controlling the solution viscosity. Among the various techniques for planarization, the SOG method is advantageous because of the simplicity of the process, the good adhesion characteristics, and the low level of stress and shrinkage in the SOG material [67]. Implementation of the SOG technique requires thorough understanding of the glass and the stability of the remaining material, which leads to considerable variation in the practicality of this technique [52]. REB uses a second mask to etchback-raised areas to lower the pattern density.The etchback mask is created by shrinking all features on a given layout by a fixed amount called etchback bias. This results in removal of the majority of the raised material if the features are large. Selective reverse etchback uses customization of the etchback mask to reduce the amount material that is etched away [37]. Although the REB method is understood, it suffers from complexity and significant cost due to extra masking steps. It also requires a significant amount of monitoring to control the level of defects caused by the process [52]. Chemical–mechanical polishing uses both mechanical and chemical means to planarize the surface of the wafer. In a typical CMP tool, the wafer is held on a rotating holder as shown in Figure 36.2. The surface of the wafer being polished is pressed against the polishing pad (i.e., a resilient material), which is mounted on a rotating disk. In addition, a slurry composed of particles suspended in a chemical solution is deposited on the pad as the chemical abrasive. The material removal mechanism of silicon dioxide (oxide) CMP is similar to the removal found in glass polishing. First, a chemical reaction softens the deposited film surface, then a mechani- cal surface abrasion aided by slurry particles removes the material [15,36]. The chemical reaction between the slurry and the surface of the wafer creates a -form material. The new material h as weaker atomic bonds. It is therefore more easily removed during the polishing process [45]. The second step involves the removal of the weakened film surface through abrasion. The actual wear mechanism is not well understood. There is speculation that a fluid layer exerts the force necessary to remove the film surface [56]. Others speculate that the removal of the film surface is due to a complex interac- tion of particle, fluid, and pad [16]. In either case, the abrasion removal mechanism is a dynamic process that depends on surface characteristics of the pad and slurry particles, although the exact contributions of these factors are not known [36]. Compared with conventional planarization methods, CMP offers a more deterministic behavior and does not incur extra processing cost such as extra masking steps. However, CMP has its own drawback which is its dependence on layout pattern density. This dependency causes variations in Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C036 Finals Page 739 10-10-2008 #4 CMP Fill Synthesis: A Survey of Recent Studies 739 Conditioning head is not shown Polish pad Slurry Slurry feed Wafer carrier FIGURE 36.2 Typical CMP tool. (From Lee, B., Modeling for chemical–mechanical polishing for shal- low trench isolation, Ph.D. Dissertation, Department of Electrical Engineering and Computer Science, MIT, Cambridge, MA, 2002) post-CMP layout parameters (i.e., variations in interlayer dielectric [ILD] thickness, metal height, etc.), which in turn impact circuit performance. In Section 36.2, the impact of the CMP process on interconnect design is reviewed. Major planarization defects are caused by the pattern dependency of the CMP process. Among the significant defects are metal dishing and dielectric erosion, which account for approximately 50 percent of yield loss in IC fabrication processes. In Section 36.2, these defects are introduced and their impact on interconnect design is reviewed. Section 36.3 discusses several traditional a s well as recent work on oxide (dielectric), copper, and shallow trench isolation (STI) CMP characterization and modeling approaches.To increase predictability,the layout pattern density variationmust be kept to a minimum. A current solution is to insert dummy metal shapes (CMP fill features) in the layout to decrease the density variation. Different density analysis methods are reviewed in Section 36.4. In Section 36.5 the problem of how to insert the required amount of CMP fill after calculating density is discussed. Section 36.6 reviews the parts of design flow that are affected by CMP fill insertion. Finally, the conclusion is presented in Section 36.7. 36.2 IMPACTS ON INTERCONNECT DESIGN AND MANUFACTURING In the very deep-submicron VLSI regime manufacturing steps including optical exposure, resist development,and etch, and CMP have varying effects on device and interconnect features depending on local properties o f the layout. Foundry economics dictate that the process window volumes be maximized, which in turn requires that device and interconnect features be fabricated as predictably and uniformly as possible. To achieve this goal, the layout must be made uniform with respect to a certain density parameter. The physics of semiconductor p rocessing make predictable and uniform manufacturin g difficult [7,18,35,55]. In particular, the quality of post-CMP depends on the pattern density of the layer beneath a given dielectric layer. The layout pattern density is one of the dominant factors in determining the post-CMP thickness profile of the deposited film [6,9,48,63]. Pattern density can be defined as the fraction of the raised areas that affect the CMP process at a particular region on the layout. Figure 36.3 illustrates the concept of pattern density in one-dimensional and two-dimensional cases. Intuitively, the higher the pattern density the larger the contact area with the pad and the lower the pressure on raised features. High-density regions are polished more slowly than low-density regions resulting in locally planar but globally nonplanar regions [36]. Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C036 Finals Page 740 10-10-2008 #5 740 Handbook of Algorithms for Physical Design Automation Deposited film Density ~50 percent Density ~25 percent Layout feature Top–down view of layout Underlying metal Cross section of layer FIGURE 36.3 Pattern density i n one and two dimensions. (From Lee, B., Modeling f or chemical–mechanical polishing for shallow trench i solation, Ph.D. Dissertation, Department of Electrical Engineering and Computer Science, MIT, Cambridge, MA, 2002.) In the p ast decade, CMP has emerged as the p r edominant planarization technique for multilevel metallization processes. However, significant surface topography variation can still exist for some layout patterns; this impacts depth of focus in lithographywhich in turn leads to variations in critical dimension (CD). Two other major defects caused by CMP are metal dishing and oxide erosion. In the copper CMP process, metal dishing is defined as the difference between the h eight of the oxide in the spaces and that of the metal in the trenches. Oxide erosion is defined as the difference between the oxide thickness before and after CMP [69]. In this chapter, dishing and erosion refer to metal dishing and oxide erosion, respectively.Figure 36.4 shows metal dishing and oxide erosion in copper CMP process. These two phenomena impact the performance of the circuit because variation in ILD thickness profile and interconnect height lead to variations in interconnect capacitance and resistance. This variation will increase the timing uncertainty of the circuit, henceitis crucial to minimize dishing and erosion. However, due to CMP nonidealities there will always be some amount of dishing and erosion. It is important to model the effect of these variations during parasitic extraction to obtain a more accurate estimation of the circuit performance [54]. Even though pattern density is the major cause of the CMP defects, there are other factors such as slurry flow rate and pad conditioning temperature that contribute to the amount of dishing and erosion. The slurry acts as a coolant material at the interface of the pad and wafer contact and takes away a significant part of the heat through convectiveheat transfer [42,59,60,72].The dissipated heat changes the chemical kinetics and the physical properties of the polishingpad [42,59].As the amount of dissipated heat increases, the polishing pad tends to become softer that results in an increase in Oxide erosion Copper dishing Cu Cu SiO 2 FIGURE 36.4 Dishing and erosion in copper CMP process. (From Tugbawa, T., Chip-Scale modeling of pattern dependencies in copper chemical mechanical polishing processes, Ph.D. Dissertation, Department of Electrical Engineering and Computer Science, MIT, Cambridge, MA, 2002.) Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C036 Finals Page 741 10-10-2008 #6 CMP Fill Synthesis: A Survey of Recent Studies 741 the area contact at the interface. In addition,pad conditioning has a major impact on the removal rate (RR) during the CMP process, as underconditioned pads will lose their surface roughness, which eventually leads in to RR reductio n [43]. For more details on effects o f slurry flow rate and pad conditioning temperature on metal dishing and dielectric erosion reader is encouraged to look into Ref. [43]. To increase the fabrication process uniformity and predictability, the layout must be made uni- form with respect to a certain density parameter. One solution for designers and manufacturers is to use techniques like CMP fill insertion and slotting to increase and decrease the pattern density [26]. CMP fills are dummy features that do not directly contribute to the functionality of the circuit and can either be grounded or left floating. CMP fill insertion reduces the amount of dishing and erosion by increasing the pattern density uniformity. However, it is well known that CMP fill insertion can increase the coupling and total interconnect capacitance and consequently deteriorate circuit perfor- mance [38,62]. If not modeled appropriately,this can directly affect yield and time-to-market. In the next section, characterization and modeling approaches of different CMP processes are represented. 36.3 CHARACTERIZATION AND MODELING APPROACHES This section, first presents a number of early works on CMP modeling which have been reviewed in Ref. [45] and then introduces three recent works [36,47,68] on CMP characterization and modeling of oxide CMP, copper CMP, and STI CMP. 36.3.1 GENERAL CMP PROCESS MODELS The combination of the chemical and mechanical aspects of CMP makes it a complex process to model based on physical principles. Typical characterization of a CMP process requires exten- sive experimentation that must be repeated for each particular CMP process (combination of tool, consumable, and process settings). The main objective of CMP is to remove the extraneous material from the surface of the wafer and p lanarize it. The process of material removal can be described by Preston’s equation: dT dt = KP ds dt (36.1) where T is thickness of the wafer P denotes the pressure caused by polishing process s is the total distance traveled by the wafer t is the elapsed time The RR is proportional to the pressure exerted on the wafer as well as the speed in which the wafer is rotating. Any other physical considerationsare put into the constant K, which is independent of pressure and velocity. In this subsection, a few CMP models are introduced and their advantages and disadvantages are reviewed [45]. The first model is based on works by Sivaram et al. [57]. The proposed model uses Preston’s equation and considers the bending of the polishing pad. The bending of the polishing pad has a significant impact on the quality of the planarization and must be modeled in RR expression. However, this model only considers the effects of bending between two neighboring step heights on the wafer. It does not take into account the three-dimensional information of the structures, which limits its applicability. The next model proposed by the authors of Ref. [6] depends on the degree of nonplanarity. The model has two parts: an analytical expression based o n an ordinary differential equation and a more complex model which iteratively adjusts the polishing rate to the actual nonplanarity. Even though . Proceedings of SPIE, vol. 2726, pp. 208–222, 1996. Alpert /Handbook of Algorithms for Physical Design Automation AU7242_C035 Finals Page 736 24-9-2008 #43 736 Handbook of Algorithms for Physical Design Automation 113 Bellingham, WA, 2001. Alpert /Handbook of Algorithms for Physical Design Automation AU7242_C035 Finals Page 734 24-9-2008 #41 734 Handbook of Algorithms for Physical Design Automation 62. N. Shiraishi,. Alpert /Handbook of Algorithms for Physical Design Automation AU7242_C035 Finals Page 732 24-9-2008 #39 732 Handbook of Algorithms for Physical Design Automation 12. D.O. Ou ma,