Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C048 Finals Page 1012 9-10-2008 #12 1012 Index Inverter v oltage transfer characteristic, and noise margins, 680 INVERT-NAND sequence, 821 IP block, 265–268 IRL, see Irreducible re alization list Irreducible empty rooms T-junctions, 197 types of, 198 Irreducible realization list, 180, 963–964 Island-style FPGA placement, 967–968 Iso-dense bias, 706 ISPD, see International Symposium on Physical Design ISPD 2005, global placements of, 301 Itanium microprocessor clock distribution, 910 topology, 908 deskew buffer architecture of, 909 global core H-tree of, 908 regional clocks of, 909 Iterated dominance (IDOM) graph, 494 Iterated KMB (IKMB) construction, 495 Iterated 1-Steiner (I1S) heuristic, 490–492 empirical performance of, 493–494 generalization of, 494 graph generalization of, 494–495 Iterated Zelikovsky (IZEL) heuristic, 495 Iteration target acceptance rate, 316 Iterati ve floorplanning, 153 Iterative partitioning, 339 ITRS, see International Technology Roadmap for Semiconductors J Jitter , arriva l time of clock transition, 882 K Karush–Kuhn–Tucker (KKT) condition, for optimality, 95 kd tree, 57–59, 67–68 range query algorithm on, 59 for set of points on plane, 58 Kernighan–Lin heuristic, for graph b ipartitioning, 114–115 K-input LUT (K-LUT), 943–944, 958–960 Kirchhoff boundary condition, 701 Krishnamurthy’s method, 116; see also Partitioning KLFM algorithm, 841 K-LUT technology mapping in O(KVE), 959 KMB algorithm, 494 KMB graph Steiner h euristic, 518 Kou, Markowsky, and Berman (KMB) method, 494 Kraftwerk, 349, 351–352, 365–366, 370–371, 373, 437 Kruskal’s algorithm, 59, 79–80 Kuhn–Tucker condition, 537 L Lagrange multiplier, 436–437, 592 Lagrangian decomposition, see Lagrangian relaxation Lagrangian function, 94–95 Lagrangian relaxation, 591, 616–617, 799 based methodology, 475 basic procedure, 96 duality function maximization, 96–97 method, in TDP, 440–441 updating of dual parameters, 97 Lam’s algorithm, 314 Lam’s theory, 315 Laplacian matrix, 113, 118–120 Large scale integration, 139 Last-in-first-out (LIFO) scheme, 116 Latency constrained optimization, 666–667 minimization multiple-terminal net optimization, 666 two-pin net optimization, 664–666 Layout compaction, 20 Layout data structure corner stitching (see Corner stitching data structure) high level operations support, 62 parasitics computation and, 63 quad tree and variants (see Quad trees) Layout sampling, in yield analysis, 778–779 Layout synthesis as masks, 17 netlist partitioning, 15–16 standard-cell/polycell, 18 Leakage current, major components of, 46 Leakage modeling, 918–920 Lee’s algorithm, 476 Lee’s router grid expansion algorithm (see Grid expansion algorithm) speedup, 11 Left-edge algorithm, 15, 21 Legalization and placement, limits of, 420–421 LER, see Line edge roughness Library-based ASIC technology mapping, 959 Linear circuit, 34–35, 678, 920, 927 Linear conic optimization problems interior point methods for, 100–101 linear programming, 99 second-order cone programming, 99–100 semidefinite programming, 100 Linearity, 93, 703, 723, 800 Linear netlength, minimization of, 331–332 Linear placement problem, 418 cost function, analysis of, 419 dynamic programming algorithm, 419–420 notations and assumptions in, 419 Linear programming duality, 629 Linear programming formulations, 122–123; see also Mathematical partitioning formulations Linear programming problem, 93, 98, 252, 932 Linear program/programming, 89, 105, 331, 341, 424, 435–436, 438–442, 451–452, 751, 760 Linear relaxation, of global routing problem, 627 Linear time algorithm, in rectangular dual, 145 Linear-time method, for module, 173 Line edge roughness, 774 Line expansion, 11, 479 Line graph, 120–121 Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C048 Finals Page 1013 9-10-2008 #13 Index 1013 Line-search algorithms, 476 Line search directed placement, 365–366, 386, 391, 393 Liquid routing, 840, 848 Lithographic modeling contour-based EPE, 715–717 extraction and SPICE modeling, 731 mask manufacturing flow, 715 modeling fundamentals, 699–700 computation by superposition, 704–705 linearity, 703–704 Maxwell’s equations, 700–701 propagation, 701–703 RET flow and computational lithography, 713–715 RET tools, 705–706 OAI, 710–711 OPC, 706–707 polarization, 712–713 PSM, 707–710 RET combinations, 711–712 Lithographic processing, 697–699 Lithographic simulation, of single layer of IC layout, 705 Lithography-aware maze routing algorithm, 799 Lithography-aware routing, for printability, 798–800 Local area constrained (LAC), 669 Local clock buffer (LCB), 830, 909 latches cluster, 831 Local improv e ment cell mirroring and pin assignment, 414–415 linear placement and fixed orderings, 418 cost function, analysis of, 419 dynamic programming algorithm, 419–420 notations and assumptions in, 419 optimal interleaving, 417–418 reordering of cells, 415–417 Local oxidation of silicon (LOCOS), 745 Location-based clustering method, 388–389; see also Multiscale optimization, in placement Logic array blocks (LABs), 945 Logic b lock architectures lookup-tables (LUTs), 944 carry chains, 946–947 clusters, 945–946 non-LUT-based logic blocks, 947 Logic circuits components of, 55 mathematical structure representing, 56 and netlist, 56 Lognormal delay, 38–39 Longest common subsequence (LCS), 215 Lookup tables, 944, 947, 953, 958–960, 970–972 Loss-contracting algorithm (LCA), 495, 503 Low-cost low-radius tradeoff hybrid tree, 511 Lower conve x hull, 573 Low power FPGA placement and routing methods, 975 LP, see Linear program/programming LSD, see Line search directed placement LSD placers, 365–366 L-shaped routes, 604 LSI, see Lar ge scale integration LUTs, see Lookup tables M Macrocell layout, 18 Macrocell placement problems, 319 Manhattan arc, 887–888 Manhattan bounding box, 838 Manhattan distance, 477, 483 Manhattan routing tree augmentation (MRTA), 785 Manufacturability-aware routing manufacturability-aware rules, 793 manufacturability issues optical lithography, 792 random defects, 792–793 minimum spacing rule, 65-nm technology, 794 printability and lithography-aware routing fast lithography simulation, convolution lookup, 800 optical interference lookup table, 799 RADAR example, 800 random defect minimization, critical-area-aware routing channel routing, 797 redundant-via-and antenna-effect-aw a re routings, 801–802 rule-based vs. model-based approach steps in, 792 topography variations dummy fill synthesis, 794–795 Markov chain approach, 323 Mask error enhancement factor (MEEF), 727–729 Master-image style, 17 Mathematical partitioning formulations, 118–119 dynamic programming, 126 integer programming formulations, 123–124 linear programming formulations, 122–123 network flow, 124–126 quadratic programming formulation, 119–122 MaxDom Steiner points, 517 Maximal rectangle, in floorplan, 147 Maximal rectangular graph, 148 Maximal rectangular hierarchy, 147–148 Maximum-critical area rectangles (Max-CARs), 779 Maximum delay-violation Elmore routing t ree, 522, 524 Maximum envelope current (MEC), 917–918 Maximum fanoutfree cones (MFFCs), 386 Maximum flo w problem augmenting path, 83 decision version for, 84 generalizations/extensions to, 83–84 iterati ve approach for, 82–83 Maximum independent set (MIS), 449 postlayout optimization, redundant-via insertion problem, 801 Max-plus lists flexibility of, 61 operation to combine elements, 61 complexity, 62 solution to optimization problem, 60 Maze routing algorithms, 478, 481 MCM, see Multi-chip module routing MELO, see Multiple eigenvector linear orderings Memory/logic interconnect architecture, 951–952 Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C048 Finals Page 1014 9-10-2008 #14 1014 Index Method of means and me dians (MMM), 884–885 Metropolis Monte Carlo method, 312 mFAR, fixed points in, 353–357 Mikami–Tab uchi algorithm, 479–480 MiLa algorithm, 550 Miller coefficient, 679 MIMD, multiple data architecture, see Multiple instruction Mincost flow, 83–84 Min-cost max-flow method for simultaneous pin assignment and buffer planning, 657 Mincut-based method, in classical slicing floorplan design, 170 Mincut floorplacement, 297 flow, modification, 302 Mincut framework advantage of flexible whitespace allocation, 299–300 floorplacement, solving difficult instances of, 300–303 incremental placement, 305–307 optimizing Steiner wirelength, 303–305 enhancements to additional partitioning, for improving results, 293 analytical constraint generation, 294–295 fractional cut for mixed-size placement, 294, 298–299 HPWL by partitioning, 295–296 mixed-size placement in Dragon2006, 299 PATOMA AND PolarBear, 298 partitioning-based placement techniques Capo, 308 Dragon, 307 FengShui, 307 NTUPlace2, 307–308 Mincut partitioning, 113 Mincut placement, 16–17 legalization, 306 process, 305 techniques, HPWL performance of, 295 Min Flow Max Cut theorem, 125 Minimizing skew violation (MinSV), 894 Minimum-cost timing-constrained buffer i nsertion problem, 542 Minimum edge rule, 802–804 during detailed routing, 802–804 DRC correction flow, 803 65-nm technology, 803 Minimum local whitespace (minLocalWS), 300 Minimum rectilinear Steiner arborescence (MRSA), 530 Minimum spanning tree, 279, 488, 511, 563, 601 algorithms for finding, 79–80 of graph, 79 Min-ratiocut k-way partitioning, 113 MIT inductance extraction program, 870 Mixed integer linear programming, floorplanning algorithm and, 155 Mixed integer nonlinear program (MINP) floorplanner, 248 Mixed-size placement, 282 floorplacement, 296–298 MNA matrices, of coupled circuit, 42 Model-based fill insertion approach, 754 Modeling defect, in yield analysis, 778–783 Model o rder reduction methods, 927–928 Modified nodal analysis (MNA), 34, 42, 922–924, 926–927 Modules, in floorplanning algorithm, 140 Monomial function, 102 Monte Carlo approach, 751–753 Monte Carlo simulation, in yield analysis, 778–779 Montecito, dual-core Itanium 2 processor , 910 acti ve deskewing system, 911 Moore’s law, 698 Moore’s shortest path algorithm, 476 Mosaic floorplan, 187 corner block list of (see corner block list) insertion of corner block to, 188 mapping between nonslicing floorplan and, 199 TBT representation of, 196 terminologies, 194–195 MOSFET device gate capacitors, c harging and discharging of, 45 high temperature effect on dri ving strength of, 50 threshold voltage and mobility, 48 static power, 46–47 Mov able circuit element, 278 mPG, in congestion-driven placement, 463 mPL6, relaxation in, 392 MRG, see Maximal rectangular graph MRH, see Maximal rectangular hierarchy MSQT, see Multiple storage quad trees MST, see Minimum spanning tree Multibend routes, 604 Multi-chip module routing, 520 Multicommodity flow, 84, 484 problem, 633 -approximate solution in polynomial time, 634 commodities for, 633 FPTAS for, 634 and fractional packing p roblem, 634 version of, 634 Multidomain clock skew scheduling, 893 Multigrid method, 924 V-cycle, 925 Multilayer sequence pairs, 966 Multile vel density analysis, 748–749 Multilev el partitioning multilev el eigenvector partitioning, 130–131 multilev el mo ve-based partitioning, 131 ne w innovations in, 132 Multipin nets, 574 Multiple eigenvector linear orderings, 122 Multiple eigenvectors, partitioning solutions and, 122 Multiple instruction, multiple data architecture, 323 Multiple sources and sinks, 8 3 Multiple storage quad trees, 67 Multiscale algorithms, characterization of, 378–380 Multiscale formulation, of global optimization, 378–379 Multiscale optimization algorithm MG/Opt, 384–385 Multiscale optimization, in placement, 378–380 basic principles of, 380–385 characteristics of Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C048 Finals Page 1015 9-10-2008 #15 Index 1015 clustering-based approach of, 385–386 coarsening of, 386–391 interpolation, 393–394 iteration flow, 391 multiscale legalization and detailed placement, 394 relaxation, 392–393 Multisection partitioning, 340–341 Multi-vt libraries, 820 Munkres’ algorithm, see Hungarian method Mutual contraction formulation model, 389; see also Multiscale optimization, in placement MVERT, see Maximum delay-violation Elmore routing tree MVERT algorithm computational complexity of, 528 phases of, 528 N Nanometer very large scale integration (VLSI) optical lithography system, illustration of, 798 Nanometer very large scale integration (VLSI) design, 791 Negative bias temperature instability (NBTI), 48, 676 Negotiated-congestion-based algorithm, 483 Neighborhood population metric, 611 Net–cluster algorithm, 389–391; see also Multiscale optimization, in placement Net-constraint-based detailed placement, 437 Net-constraint-driven placement, steps of, 434 Net-constraint generation, in timing-driven placement, 434–437 Net half-perimeter, 279–280 Netlength constraint, 434 incremental, 435–436 single-shot, 434–435 Netlength, minimization of linear netlength minimization, 331–332 netlength definition, 328–330 objecti ve functions of, 334–335 quadratic netlength minimization, 332–334 Netlist clustering, 364 Netlist-connectivity-based, in congestion-driven placement congestion-aware logic synthesis, 449–450 metrics for structural logic synthesis, 448–449 perimeter-degree, 450–452 Netlist logic g ates, 56 Netlist partitioning into tiers, 999 Net modeling, in timing-driven placement, 424–425 Net models, 111–112 in analytical placement, 329–333 hyper-edge model, clique-edge model, and star, 278 Net wirelength model, 280 Network flow maximum flow problem augmenting path, 83 generalizations/extensions to, 83–84 iterati ve approach for, 82–83 properties, 82 Network flow, in mathematical partitioning formulations, 124–126 NHP, see Net half-perimeter NHP bounding box, 279 NLC, see Netlength constraint NMOS transistors, 876 Noise, see Coupling noise Noise analysis, 676 conservativ e filtering of nonrisky nets, 683–684 reducing pessimism in crosstalk, 684–685 logic correlations, 685–687 switching (timing)windows, 687–688 simplification of models, 681–683 aggressor driver model, 681 quiet victim model, 681–682 receiver characterization, 683 switching victim driver model, 682–683 Noise-aware design, 688–689 Noise-aware routing, 689 Noise calculation, 676–679 Noise cluster, with capacitiv e coupling, 678 Noise margin (NM), 544–545 Noise model, 661 Noise prevention, 688–689 Noise rejection curve, 680 Noncritical nets, 581 Non-Hanan interconnect synthesis, 522–528 Non-Hanan optimization, 522 Non-Hanan routing, efficacy of, 524 Noninferior solutions, 573 Noninverting buffers, 542 Nonlinear transformation, 102 Nonslicibile floorplan topologies; see also Floorplanning inherent nonslicibility, 148–149 MRH, 147–148 rectangular duals, canonical embedding of, 149–150 rectilinear modules, dualization with, 150–151 Nontree routing topologies, 529 Nonuniform wire, 589 sizing function, 593 NOR-INVERT sequence, 821 Notation, 402 NP-completeness decision problems, 84 of 3SAT, 85 NP-complete problems, 84–85, 481 NP-complete Steiner problem, 496 NTUPlace2, analytical technique, 307 O Off-axis illumination (OAI), 706, 710–711 Off-path resizing, 821 On-chip inductance, 866–868 On chip variation (OCV) analysis, in yield optimization, 786 OPC models, 725 Optical and process correction (OPC), 706, 711, 714, 725, 727, 763 Optical interference cost, 799–800 Optical lithography process, 697 Optical-lithography system, for VLSI manufacturing, 798–799 Optical proximity correction (OPC)-aware maze routing work, 799–800 Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C048 Finals Page 1016 9-10-2008 #16 1016 Index Optical system of imaging t ool, 702 Optical wave, cross-section view, 709 Optimal buffer solutions, 580 Optimal clock skew scheduling, 893 Optimal connection algorithm sink and edge, 527 Optimal interleaving technique, in local improve ment, 417–418 Optimal matching algorithm, 885 Optimal propagation speed, 594 Optimal routing graph, problem, 529 Optimal subtree, generation g raph, 577 Optimal wire sizing, 593 Optimization algorithms wire-sizing problem solving convex programming algorithm, 590 discrete optimization algorithm, 588–589 high-order moment-based algorithm, 593–594 Lagrangian relaxation-based algorithm, 590–592 nonuniform, 593 sequential quadratic programming algorithm, 592 va riational calculus-based nonuniform sizing algorithm, 592–593 Optimization concepts conve x cone, 91 convex functions, 91–92 conve x optimization problem (see Con vex optimization problem) convex sets, 90–91 Optimization problem, 120 conve x (see Convex optimization problem) dual function associated with, 94 local optimality condition for, 95 Optimize circuit performance timing-driven routing methods, 510 ORG, see Optimal routing graph Oriented slicing tree, 164–167 O-tree vs. B ∗ -tree, 227–228 perturbations, 206 relationship between placement and, 205–206 types of, 205 Otten’s algorithm, in oriented slicing tree, 167 Outline-free formulation, 240 Oxide CMP modeling, 742–743 P Package-le vel power bus model, 915 Packing floorplan representations adjacent constraint graph (see Adjacent constraint graph) bounded-sliceline grid (see Bounded-sliceline grid) B ∗ -tree (see B ∗ -tree) O-tree (see O-tree) sequence pair (see Sequence pair) transitive closure graph (see Transitive closure graph) Pairwise interchange, 13; see also Assignment problem Parallel computation technique, in analytical placement, 344 Parametric yield analysis, 775–776 Parametric yield optimization, future of, 786–787 Partial differential equations, 120, 378 Partial element equiv ale nt circuit method (PEEC), 869–870 Partially embedded routing tree topology, 561 Partition-based net-constraint placement, 436–437 Partitioning; see also Mathematical partitioning formulations define, 109 move-based methods Fiduccia–Mattheyses heuristic, 115–117 Kernighan–Lin heuristic, 114–115 simulated annealing, 117–118 multilevel multilev el eigenvector partitioning, 130–131 multilev el mov e-based partitioning, 131 ne w innovations in, 132 types of, 112–114 Partitioning-based placement for FPGAs (PPFF) placement tool, 968 Passive reduced–order interconnect macromodeling algorithm, 587 PathFinder negotiation-based algorithm, 975 Path-folding arborescence heuristic, 515 PDEs, see Partial differential equations PEKO, see Placement examples with known optimal Pentium 4 global clock distribution in, 906 spines, 906 stripes in, 907 Pentium II, global clock distribution network, 904 Pentium III, two-spine global clock distribution, 905 Perfectly matched layers (PMLs), 722 Performance impact limited fill (PIL-Fill), 753 Perimeter-degree, in congestion-driven placement, 450–452 PFA, see Path-folding arborescence heuristic PFA heuristic, graph-based, 517 Phase conflicts, 709–710 Phase-locked loop, 898, 900, 907, 910 Phase-shifting masks (PSM), 706–709 Physical synthesis techniques, 969–972 PIAF, for top-down floorplanning system, 157 Picosecond imaging for circuit analysis (PICA), 901 Piece wise concavity, 527 Pin assignment history of, 261 technique, in local impro vement, 414–415 and timing budgeting, 263–264 Pin positions and netlength, 331 Pin swapping, 821 and critical path improvement, 820–821 Pipeline routing, 980–981 Placement algorithm, 284 assignment problem (see Assignment problem) before and after legalization of, 281 bins, 306–307 block/gate/transistor-level netlist, 277 constraints in floorplan design boundary check, 200 boundary constraints, 199 CBL, 199 function of, 277, 279 general approaches, 285–286 Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C048 Finals Page 1017 9-10-2008 #17 Index 1017 IBM01 benchmark, 299 macroblock vs. ASIC, 284 modern issues in, 281–285 netlist partitioning, 296 NP-complete problem, 280 phase problem between routing and, 18, 22 primary task of, 278 problem formulation, 278–281 and routing blockages, 569–570 routing congestion measurement of, 277–278 simulated annealing, 285 simulated annealing and, 313 standard cell vs. mixed-size, 282 top-down par titioning-based (see Top-down partitioning-based placement) 3D Placement, 990–991 Placement-driven synthesis (PDS) area reco very mechanisms, 824–826 critical path optimizations, 818 cell expansion, 822 cloning, 821 dri vers and multiple objectives, 823–824 early paths fixation, 823 gate sizing, 819 high and low-vt cell, 820 incremental synthesis, 820–822 inverter processing and, 821–822 multiple-VT libraries and gate sizing, 819–820 off-path resizing, 821 shattering, 822 synthesis techniques, 823 hierarchical design, 827–830 high-performance clocking, 830 latch clustering and LCBs, 830–831 optimization and placement interaction bin-based placement model, 817–818 exact placement, 818 incremental bit map (imap) and, 818 legalization, 816 physical synthesis, phases of placement-driv en synthesis, 814–815 timing-driven placement, 816 timing histogram of, 815 power gating and leakage power reduction, 830–832 header/footer switches and, 831 macro/core coarse-grained, 832 routing recovery mechanisms, 826–827 vt recovery mechanisms, 827 Placement examples with known optimal, 421 Placement grid, 278 Placement legalization techniques flow and diffusion-based legalization, 411 single-row dynamic programming-based legalization, 412–414 tetris-based legalization, 412 PLL, see Phase-locked loop PMOS transistors, 876 Point-configuration method, in classical slicing floorplan design, 171 Point_Find, 64 Pointsets, with multiplicities, 304–305 Polarity distance, 560 Polarization, 712–713 Postroute noise repair, 689 gate sizing, buffer insertion, 689–690 hierarchical properties of design, effect of, 690 Posynomial function, 102 1.3-GHz Power4 chip, 900–901 Power dissipation dynamic power CMOS circuit, 44–45 toggling of devices, 46 short-current power, 46 static power, 46–48 Power gating using header/footer switches, 831 Power4 global clock distribution, 3D visualization, 901 Power grid design decoupling capacitance and cell modeling equi valent switching circuit, 917 P/G network, switching events, 917 worst-case current, algorithms for, 917–918 fast analysis techniques hierarchical partitioning method, 923–924 hybrid mesh/tree structure, 928 macromodels and, 923 model order reduction methods, 927–928 multigrid methods, 924–927 random walk game, 930 random walk method, 928–930 representative node, 929 shorting nodes, 927 V-cycle, multigrid method, 925 V dd power grid, voltage drop, 922 leakage modeling, 918, 920 subthreshold leakage, 919 methodology, 920 model order reduction methods, 927–928 noise metrics, 922 on-chip power buses, rules, 916 optimization decoupling capacitance allocation and sizing, 933–934 power supply pads and pins, 935–936 stages of, 932–933 topology, 934–935 wire sizing, 931–933 package and power grid modeling, 915–916 package-level power b us model, 915 random w alk method, 928–930 technology trends and challenge, 913–914 IC technology parameters, 914 tolerance analysis of circuit extraction, 920–921 variability sources, 921 uncertain work loads and power grid analysis, 930–931 wire segment, RLC π -model, 916 Power supply network, 266 plan, 266 wires, 266 Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C048 Finals Page 1018 9-10-2008 #18 1018 Index Predicti ve congestion map probabilistic congestion map, 608 Predicti ve pruning technique, 552 Pre-global clock network (PGCN), inv e rsion stages, 907 Preston equation, 741–742 PRIMA, see Passive reduced–order interconnect macromodeling algorithm Prim–Dijkstra algorithm, 560 Prim’s algorithm, 80 and Dijkstra’s algorithm, 512 Printed wiring boards, 261 Probabilistic congestion estimation, 606–607 maps, 602 Probabilistic estimation techniques, 602 Probability density function (PDF), integral of, 31 Probability of failure (POF), defect size distribution, 796–797 Process windows, tools for evaluation, 726–727 determination of, 727 Progressive routing, 619 strength and weaknesses detouring, 620 di vergence, 621 Properly t riangulated plane, 143–144 Prototyping ASIC handoff, 259 power supply network analysis, 267 process of, 266 Pruning techniques, 551 Pseudocell, define, 352 Pseudonet, define, 353 PTP, see Properly triangulated plane P-Tree algorithm, 562 algorithmic framew ork, 563–564 P-Tree Steiner tree, construction algorithm, 559 P-Tree topology space capture spatial sink locality, 565 PV-bands, 728–730 PWBs, see Printed wiring boards Q QLQT, see Quad list quad trees Q-sequence, 191–192 extended, 192–194 Quad list quad trees choice of list in, 67 leaf quads, 68 vs. MSQT, 68 Quadratic assignment problem branch-and-bound solution for, 12 Quadratic netlength optimization, 332–334 Quadratic optimization, 348–351 Quadratic phase factor , o f lens, 701 Quadratic placement multiscale model problem for, 380–382 properties of, 335–337 Quadratic programming formulation, 119–122; see also Mathematical partitioning formulations Quadratic program/programming (QP), 332, 437 Quadrisection partitioning, 339 Quad trees bisector list, 66–67 bounded, 68 hinted, 69–70 HV tree, 68–69 kd trees, 67 multiple storage, 67 quad list, 67–68 and variants, 65–66 Quarter-state sequence define, 191 extended, 192 R parenthesis tree of, 192–193 representation, 191 of room, 191 QUASAR illumination, 712 Quasi-bipartite graphs, 490, 496 R RADAR work, 800 Ramaiyer’s algorithm, 503 RAM block, 963 Random defects in yield loss, 773 yield modeling, 776–783 Randomized rounding technique, 640–641 lemma, proof of, 640–641 theorem expression, 641 Random w a lk method, 928–930 RAT, see Required arrival time RC π -model, 548 RC trees Elmore delay, 590 additi ve property, 33 between two nodes, 32 LU factorization of, 34 Reconnection point, optimal value o f, 526 Rectangle dissection compatible, 20 polar graph of, 17 slicing property, 21 Rectangular dissection, properties of, 185 Rectangular dualization method, in floorplanning, 157 Rectangular duals, 141–142; see also Floorplanning canonical embedding of, 149–150 dualizability, 142–145 slicibility of, 145–147 Rectangular floorplan, 142 Rectilinear modules filling approximation for, 236 L-shaped module, 234 partitioning of, 235–236 Rectilinear Steiner arborescence problem minimum-cost shortest paths Steiner tree, 514 Rectilinear Steiner tree (RST), 329–330, 333, 633, 855 Recursive merging and pruning, 575 Recursive partitioning approach, 343–344 Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C048 Finals Page 1019 9-10-2008 #19 Index 1019 Redundant-via-awa re routing, 801 Refracti ve index, 700 Regional clock driv er (RCD), 908 Register transfer level (RTL) synthesis tool, 958 β-Regularization methods, 841 Relaxation method, in floorplan, 153 Remov a l rate (RR), 741 Required arrival time, 522 Residual graph, 83, 331 Resistance-capacitance (RC) model, 425 Resistiv e shielding effect, 546 Resolution enhancement techniques (RET), 792, 800 Restrictiv e design rules (RDR), 792 RET flow and computational lithography, 713–715 Retraction, 10 RET tools, 705–706 Re verse etchback (REB), 737–738 Rigorous coupled wave analysis (RCWA), 723 Rip-up and reroute region, 623 routing problem A ∗ maze search, 617–618 cost functions and constraints, 618 Lagrangian relaxation, 616–617 Steiner tree construction, 617 strategies, 625 Rip-up-and-reroute schemas basic methodology, 618 iterati ve improvement schema, 621–624 progressiv e rerouting schema Gcell grid, 619 issues, 620–621 RISA routability model, 461–462 RLC lines circuits, 876–877 damping factor, 866 π-model of wire segment, 916 rise time of signals, 872 signal delays and, 874 trees, 870 RMP, see Recursi ve merging and pruning Robust optimization of circuit under process variations delay constraint, 105 robust constraint, 106–107 conve x optimization, 104 Routability analysis, 264–265 Routed connection, loop, 622 Routed wirelength (rWL), 303 Router integration in congestion-driven placement techniques, 458 Routing-based congestion estimation methods probabilistic methods, p rice, 605 Routing blockages, modeling of, 604 Routing c ongestion, 599 metrics for logic synthesis, 610–611 for technology mapping, 608–610 postrouting metrics for, 600–601 track ov e rflow, 600 Routing demand analysis for bins, bounding box, 603 for noncorner bins, 605 computation of, 602 Routing graph, 571 Routing grid graph blockages on, 618 pruned, 618 Routing in wiring layers, 12 Routing models, 402–403 Routing process, 843, 851 algorithms, 991–993 placement and, 997–998 architectures bus-based routing architectures, 948–949 pipelined interconnect architectures, 950 programmable switches, 948 segmentation, 947–948 switch blocks and connection blocks, 949–950 grid and routing graph for four-tier 3D circuit, 992 nodes on diagonal layers, 845 and versatile placement, 975 congestion-driven routing, 981 graph-based routing, 979–980 hierarchical routing, 976–977 low power routing, 980–981 SAT-based routing, 977–979 statistical timing routing, 981–982 Routing resources, fine-grain modeling of, 469 Routing speed, techniques, two-pin segments, 606 Routing-tree topology different embedded solutions, 562 nodes and edges connection, 524–525 Routing, violation control, 623 RPack, 960; see also Clustering algorithms R parenthesis tree, of Q-sequence, 192–194 RQ-sequence, 191 RSA algorithm, 515–516 Rule based fill insertion approach, 754 Runtime complexity, 73–74 S Safe whitespace, 300 SAT-based routing, 977–979 Scalability of multilevel approach, 383–384 SCAMPI, see Ad hoc look–ahead floorplanning Second-level clock-buffers (SLCBs), 910 Second-order cone programming (SOCP), 99–100, 798 Semidefinite programming (SDP) computational effort, to solve, 101 feasible regions of, 100 Sequence pair equi valence of, 228–229 perturbations, 216 placement on c hip LCS, 215 optimal packing under constraint, 214–215 positive and negative loci, 213–214 vertical-constraint graph, 215 Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C048 Finals Page 1020 9-10-2008 #20 1020 Index Sequence triplet, 231 Sequential circuit, timing diagram of, 29–30 SERT, see Steiner Elmore routing tree SERT-C algorithm, 521 Elmore delay formula, 522 SERT- C critical-sink routing tree eight-sink net, 523 SERT heuristic, execution of, 520 SERT Steiner, execution of, 521 Shallow trench isolation CMP, 775 modeling, 745–747 Shallow trench isolation (STI), 739 Shape-shifting methods, in yield analysis, 779 Shi’s algorithm, in oriented slicing tree, 165–167 Short-current power, 46 Shortest paths tree, 511 Signal integrity optimization algorithm noise aware optimization, 594–595 Signal n ets, 110 Signal source pin, 511 Signal switching, slew rate of, 543 SIMD, multiple data architecture, see Single instruction Simple placement instance, 278 Simplex algorithm, with column generation, 632–633 algorithm checks, 633 dual of linear program, 632 linear program, with matrices, 632 use of, Karmarkar algorithm, 633 Simulated annealing, 86–87 in classical slicing floorplan design, 171–172 in congestion-dri ven placement techniques A-tree router, 463 over flow (OF), 462–463 RISA routability model in, 461–462 sparse parameter, 463–464 in floorplan sizing methods, 153 formulation o f, 313 for graph partitioning, 117–118 optimal solution, 311 in TDP, 441 TimberWolf system, 314 Simulated annealing algorithm, 312 acceptance function for, 313 adva ntages of, cost f unction, 318 Simulated annealing placement algorithms, 320 configuration strategies, 320–321 multilevel methods, 321–322 parallel algorithm, 323 importance of, 324 Simulated annealing placers cost functions, 319–320 e volution of, 323 partition-based methods, 322 Simulation cutlines, selection of, 714 Simulation techniques; see also Lithographic modeling imaging system modeling, 717–720 fourth-order Zernike aberration Z 4 in pupil plane, 720 illumination systems partially coherent, i mage formulation, 718–719 lens design, 717 TCC overlap integral, 719–720 for very coherent light, 718 mask transmission function, 720 domain decompositionmethod (DDM), 723 finite-difference time domain (FDTD) method, 720–723 RCWA and waveguide techniques, 723 wafer simulation, 723–725 Simultaneous buffer insertion, 538 Simultaneous tree construction buf fer insertion P-Tree algorithm, 562–564 SP-Tree algorithm, 566 S-Tree algorithm, 564–566 tree topology, 566 Single instruction, multiple data architecture, 323 Single-layer wiring, 13–14 Single-row dynamic programming-based legalization technique, 412–414 Single sink insertion, 561 Skew, 882 sensitivity to process v ariations, 883 Slack-based netweighting, in timing-driven placement, 428–429 Slew constraint, 543 control, 688–689 degradation, 543 expression for, 34 rate, 882 scaling factor, 3 9 Slicible floorplans, 141, 145–146 four-cycle criterion for, 146–147 Slicing floorplans adva nces in, 177–182 classical design, 169 mincut-based method, 170 point-configuration based, 171 simulated annealing based, 171–172 define, 161–162 design considering placement constraints, 172 abutment constraint, 175–176 boundary constraint, 173–174 clustering constraint, 176–177 range constraint, 174–175 optimizations on area optimization, 164–168 power/area optimization, 168–169 polish expression by, 164 slicing tree in, 163–164 Slicing theorem, 146 Slicing tree completeness of, 178–179 in slicing floorplans, 163–164 Slicing-tree annealing-based floorplanning algorithm, 964 SOC, see System–on–chip Soft-errors in SRAM cells, 942 Soft processors, 953 Soukup’s fast maze algorithm, 478 SP, see Sequence pair Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C048 Finals Page 1021 9-10-2008 #21 Index 1021 Space management, 403–404 cell shifting, 410 computational geometry-based placement migration, 409–410 diffusion-based placement migration, 408 flow-based overlap remo val, 404–408 grid warping, 410–411 WSA, 408–409 Spaghetti code, 18 Spanning tree to rectilinear Steiner tree, converting, 513 Sparse parameter in congestion-driven placement techniques, 463–464 Spectrum for conventional illumination, 711 Spectrum for off-axis r ay, 710–711 Speedup techniques, 11 best candidate, 553–554 convex pruning, 552–553 explicit representation store slack and capacitance values, 554–555 predicti ve pruning, 551–552 speedup results, 550–551 Spin-on glass (SOG), 737–738 SP-Tree algorithm, 566 ST, see Sequence triplet STA, see Static timing analysis Standard breadth-first search global routers, 607 Standard cell connectivity, 110 Standard cell-dominated design, 260 Standard cells, 110, 140, 257, 259, 269, 282, 292, 294, 298, 301, 322, 368, 402, 412, 470, 837, 990 Star graph, define, 111 Star (V ) model, 329 State-of-the-art FPGA synthesis algorithms, 958–959 Static netweighting, in timing-driven placement, 427–432 Static power gate tunneling c urrent, 47 subthreshold leakage current, 46–47 Static random access memory (SRAM), 829, 913 based FPGAS, 942–943, 958 bit, 980 Static timing analysis, 425, 428 Statistical floorplanning, 251–252 Statistical learning techniques, 323 Statistical timing analysis, 981 Steiner approximation, 490, 502 heuristic, 495 ratio, 495 Steiner arborescences, 494, 513–519 Steiner candidate node, set of, 517 Steiner Elmore routing tree, 520 Steiner minimal tree (SMT), 617 problem, 487–488 Steiner node, buffer blockage, 575 Steiner tree, 627 algorithm, 490 construction research and development, 530 net model, in TDP, 442 and placement-driven synthesis (PDS), 813, 826 wirelength, 454–455 Steiner tree wirelength (StWL), 279, 303, 454 Steiner (V ) model, 329 Steiner wirelength optimization, in global-placement, 454–455 Steiner wire models and gate sizing, 819 STI, see Shallow t rench isolation STI fill insertion, 758–760; see also Chemical-mechanical polishing Stockmeyer’s algorithm, 61 in oriented slicing tree, 165 S-Tree topology space, 565 Strict aggregation and weighted aggregation, 383 Subthreshold leakage current, 46 Sum of all-pairs mincut (SAPMC), 448–449 Super-feasible region, 969–970; see also Physical synthesis Swap, 226–227; see also Adjacent constraint graph Switch blocks and connection blocks, 948 Switch matrix, critical path configurations and delay va riations, 982 Synthesis–placement interface (SPI) bins and, 817 Systematic defects, in yield loss, 773 System on chip, 424, 455, 690 T Tabu-search, 962 Taylor expansion, third-order, 547 TBS, see Twin binary sequence TBTs, see Twin binary trees TCG, see Transitive closure graph TCG-S construction from placement, 221–223 packing scheme for, 223 perturbations, 223–224 TCG, SP, and, 221 TDP, see Timing–driven placement Technology CAD (TCAD) tools, 696 65-nm technology, context-dependent minimum spacing rule, 794, 804 Technology mapping, and clustering, 958–961 Tetris-based legalization technique, 412 Three-dimensional (3D) circuits, 985 3D floorplanning, 989 3D placement, 990–991 three-tier 3D technology , 991–992 Three-dimensional place and route (TPR) partitioning-based placement within tiers, 999–1000 partitioning circuit between tiers, 998–999 simulated annealing placement phase, 1000 tool, 998 TPR CAD tool, 997–998 Three-dimensional placement, 284 Tile graph, 277 TimberWolfSC, 319 Timing budgets, history of, 261 Timing closure, 23–24 Timing-driven buffer insertion problem, 538 [...]... placement, 843 global routing for, 843 impact of, 844 implementation of, 858 Manhattan wires and diagonal wires in, 837 Moore’s law, 836 placer for, 842 X initiative, 857 X place and route (XPR) system, 835–837, 840, 848, 858, 860 Alpert /Handbook of Algorithms for Physical Design Automation AU7242_C048 Finals Page 1024 9-10-2008 #24 1024 global routing, 843–848 history, 836 limitations of, 839 manufacturing... 448, 557 chip design, 448 circuits, 139, 509, 586 design automation community, 110, 131–132 designs, 427, 674 layouts, 487 Victim net noise injected to, 42 calculation of, 43 Virtex-II/-II Pro devices, 952 VLSI, see Very large scale integration VLSI CAD, rectilinear Steiner minimum trees, 513 VLSI circuit design, buffer scaling, 536 VLSI designs, 277 methodologies, 653 VLSI physical design automation, ... solution, 540 pruning implementation, 540 pseudocode, 540 work flow of, 540–542 Alpert /Handbook of Algorithms for Physical Design Automation AU7242_C048 Finals Page 1023 9-10-2008 #23 1023 Index van Ginneken’s dynamic programming algorithm, 557 van Ginneken style algorithm buffer insertion candidate locations, 582 van Ginneken style buffering algorithms, 548 van Ginneken-style dynamic programming algorithm,...Alpert /Handbook of Algorithms for Physical Design Automation AU7242_C048 Finals Page 1022 9-10-2008 #22 1022 Timing-driven placement, 424, 426–427 accurate net-modeling issue, 442–443 building blocks and classification of net modeling, 424–425 time analysis and metrics, 425–426 Hippocrates in, 442 hybrid net method... 440–441 LP-based formulation, 438–440 partitioning-based overlap removal, 440 simulated annealing, 441 Timing graph, in TDP, 437–438; see also Timing-driven placement Timing optimization, 475 T-junctions degenerated case modeled by, 186 kinds of, 187 noncrossing segment of, 191 possible orientations for, 194–195 of reducible and irreducible empty rooms, 197 on top and right boundaries for floorplan,... employing, 859 role of VIAS nonpreferred-direction wiring, 840 routing spacemodel and search algorithm, 849–851 Steiner trees, 855–856 system for, 840 theoretical benefits of, 837–839 Y Y architecture, 836 Yield analysis parametric, 775–776 random defect yield modeling, 776–783 Index Yield ingredient, 772 Yield loss sources of, 774–775 types of, 773 Yield optimization, methods for corner-based design analysis,... binary sequence constructing floorplan from, 197 definition of, 196 empty room insertion process, 198 transformation to floorplan, 197 Twin binary trees definition of, 194 of mosaic floorplan, 196 T-junctions, 195 transformation from floorplan to, 195 TWL, see Total wirelength Two-dimensional bin-packing problem, 965 Two-dimensional problem, solution of, 13 Two-phase flow buffer-aware Steiner tree construction... accuracy of, 547 Wirelength buffers, 558 Wirelength-radius trade-offs, 510–513 Wire-load models, 23 Wire parallel plate capacitance, 587 Wire planning, chips, 24 Wire resistance, 587 Wire retiming, 667–668 area constrained, 668–669 LAC, formulation with sets of constraints, 669 introducing, variable R(v), 667–668 retiming solution, for given clock period TCP , 667 Wire segment, delay and slew of, 31... detection of infeasibility in, 98 IR drop in, 249 purpose of, 3 synchronous, 29 timing metrics used in Elmore delay (see Elmore delay) fast timing metrics (see Fast timing metrics) static timing analysis, techniques for, 39–41 VLSI technologies, 522, 536 Voronoi deterministic method, in yield analysis, 780–782 Voronoi diagram, 86 VTR model, 725 W Wafer simulation, 723–725 Wave equation, 701 Waveforms of noise,... of reducible and irreducible empty rooms, 197 on top and right boundaries for floorplan, 194 TNS, see Total negative slack Top-down partitioning-based placement bipartitioning vs multiway partitioning, 291 cutline direction selection techniques types of, 291–292 process of, 290 terminal propagation and inessential nets, 291 whitespace allocation free cell addition, 292–293 Top-down placement process, . 380–385 characteristics of Alpert /Handbook of Algorithms for Physical Design Automation AU7242_C048 Finals Page 1015 9-10-2008 #15 Index 1015 clustering-based approach of, 385–386 coarsening of, 386–391 interpolation,. interconnect architecture, 951–952 Alpert /Handbook of Algorithms for Physical Design Automation AU7242_C048 Finals Page 1014 9-10-2008 #14 1014 Index Method of means and me dians (MMM), 884–885 Metropolis. 11, 479 Line graph, 120–121 Alpert /Handbook of Algorithms for Physical Design Automation AU7242_C048 Finals Page 1013 9-10-2008 #13 Index 1013 Line-search algorithms, 476 Line search directed