Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C011 Finals Page 222 29-9-2008 #21 222 Handbook of Algorithms for Physical Design Automation overlapped with the rectangle defined by the two closest corners of b i and b j , and finally to b j (b i ), for which it is considered as b i ⊥ b j (b j ⊥ b i ). Given a placement, − can be extracted as follows. We first extract the module on the bottom-left corner. At each iteration, we extract the left-most unvisited module b with all the modules below b having been extracted. The process repeats until no module is left. Figure 11.18a through f illustrate the procedure to extract a − from the placement of Figure 11.24a. We first extract the module b a on the bottom-left corner (Figure 11.18a), and then b b because it is the left-module with all the modules below b b having been extract(Figure11.18b).This process continuesuntilnomoduleis left, resulting in − =abcdegf . After extracting − , we can construct C h and C v based on − . For each module b i in − ,we introduce a node n i with the weight being b i ’s width (height) in C h (C v ). Also, for each module b i before b j in − , we introduce an edge (n i , n j ) in C h (C v ) if b i b j (b i ⊥ b j ). As shown in Figure 11.18b and g, for the first two modules b a , b b in − , we introduce the nodes n a and n b in C h (C v ) and assign the (a) a b c d f g e a b c d f g e a b c d f g e a b c d f g e a b c d f g e a b c d f g e (b) (c) (d) (e) (f) n c n b n a C h C v n g n d n e n d n e n g n f n c n b n a n f 3.5 2 2 3 1.5 5 1 1.5 2.5 3.5 2 1.5 1.5 2 (g) Γ_ : a b c d e g f FIGURE 11.18 (a–f) Process to extract a − from the placement and (g) resulting TCG-S. (From Lin, J M. and Chang, Y W., IEEE Trans. Comput. Aided Des. Integr. Circuits Syst ., 23, 968, 2004. With permission.) Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C011 Finals Page 223 29-9-2008 #22 Packing Floorplan Representations 223 weights as their widths (heights). Also, we construct a directed edge (n a , n b ) in C v because module b a is before b b and b a ⊥ b b . The process repeats for all modules in − , resulting in the TCG-S shown in Figure 11.18g. Each TCG has seven nodes and 21 edges in total (eleven in C h and ten in C v ). Note that there exists a unique TCG-S corresponding to a placement. 11.8.2 FROM TCG-S TO A PLACEMENT Lin and Chang propose an O(m lg m)-time packing scheme for TCG-S based on − as well as a horizontal and a vertical contours R h and R v ,wherem is the number of modules. The basic idea is to process the modules based on the sequence defined in − , and then pack the current module to a corner formed by two prev iously placed modules in R h (R v ) according to the geometric relation defined in C h (C v ). 11.8.3 TCG-SPERTURBATIONS Four operations rotation, swap, reverse, and move in TCG are extended to perturb C h and C v .During each perturbation, we must maintain the three feasibility properties for C h and C v . Unlike the rotation operation, swap, reverse, and move may change the configurations of C h and C v and thus their properties. Further, we also need to maintain − to conform to the topological ordering for new C h and C v . Rotation. To rotate a module b i , we exchange the weights of the corresponding node n i in C h and C v . Because the configurations of C h and C v do not change, so does − . Figure 11.19b shows the resulting TCG-S and placement after rotating the module g shown in Figure11.19a. Notice that the new − is the same as that in Figure 11.19a. TCG-S is closed under the rotation operation, and such an operation does not change the topology of the TCG and − . Swap. Swapping n i and n j does not change the topologies of C h and C v . Therefore, we only need to exchange b i and b j in − . Figure 11.19c shows the resulting TCG-S and placement after swapping the nodes n c and n g shown in Figure 11.19b. Notice that the modules b c and b g in − in Figure 11.19c are exchanged. TCG-S is closed under the Swap operation, and such an operation takes O(1) time. Reverse. To reverse a reduction edge (n i , n j ) in one TCG, we first delete the edge (n i , n j ) from the graph, and then add the edge (n j , n i ) to the graph. To keep C h and C v feasible, for each node n k ∈ F in (n j ) ∪{n j } and n l ∈ F out (n i ) ∪{n i } in the new graph, we have to keep the edge (n k , n l ) in the new graph. If the edge does not exist in the graph, we add the edge to the graph and delete the corresponding edge (n k , n l ) (or (n l , n k )) in the other graph. To make − conform to the topological ordering of new C h and C v , we delete b i from − and insert b i after b j . For each module b k between b i and b j in − , we shall check whether the edge (n i , n k ) exists in the same graph. We do nothing if the edge (n i , n k ) does not exist in the same graph; otherwise, we delete b k from − and insert it after the most recently inserted module. Figure 11.19d shows the resulting TCG-S and placement after reversing the reduction edge (n d , n e ) of the C v in Figure 11.19c. Because there exists no module between b d and b e in − , we only need to delete b d from − and insert it after b e , and the resulting − is shown in Figure11.19d. TCG-S is closed under the reverse operation, and such an operation takes O(m) time, where m is the number of modules. Move. To move a reduction edge (n i , n j ) from a TCG G to the other G , we delete the edge from G andthenaddittoG . Similar to reverse, for each node n k ∈ F in (n i )∪{n i }and n l ∈ F out (n j )∪{n j }in G , we must move the edge (n k , n l ) to G if the corresponding edge (n k , n l ) (or (n l , n k ))isinG. Because the operation changes only the edges in C h or C v but not the topological ordering among nodes, − remains unchange d. Figure 11.19e shows the resulting TCG-S and placement a fter moving the reduction edge (n a , n e ) from C v to C h in Figure 11.19d. Notice that the resulting − is the same as that in Figure 11.19d. TCG-S is closed under the move operation, and such an operation takes O(m) time, where m is the number of modules. In particular, − remains the same after the operation. Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C011 Finals Page 224 29-9-2008 #23 224 Handbook of Algorithms for Physical Design Automation a b f g c e d 5 1.5 2.5 2 2 2 3 1.5 3.5 2 1 3.5 1.5 1.5 n f n d n g n e n c n a n c C h n d n g n b n e n a n b n f C V (d) Γ_: abgedcf a b c d e f g (b) 3.5 2 2 3 5 3.5 1.5 2 2 1 1.5 n f n e n c n d n g n a n g C h n c n b n d n a n b n f C V Γ_: abcdegf b f g c e d a 2 2 3 2 5 2 1.5 1.5 3.5 1.5 1 n f n d n g n e n c n a n c C h n d n g n b n e n a n b n f C V Γ_: abgedcf (e) a b d e f g c 3.5 2 2 5 3 1.5 2 1.5 1 3.5 2 n f n e n g n d n c n a n c C h n g n b n d n a n b n f C V (c) Γ_: abgdecf a b c d e f g (a) 3.5 2 2 3 1 5 1.5 3.5 2 1.5 2 n f n e n c n d n g n a n g C h n c n b n d n a n b n f C V Γ_: abcdegf 2.5 1.5 2.5 1.5 1.5 n e 1.5 2.5 1.5 n e 1.5 n e 1.5 2.5 3.5 FIGURE 11.19 Four types of perturbation. (a) The initial TCG-S and placement, (b) resulting TCG-S and placement after rotating the module b g shown in (a), (c) resulting TCG-S and placement after swapping the nodes n c and n g shown in (b), (d) resulting TCG-S and placement after reversing the reduction edge (n d , n e ) shown in (c), and (e) resulting TCG-S and placement after moving the reduction edge (n a , n e ) from the C v of (d) to C h . (From J M. Lin and Y W. Chang, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 23, 968, 2004. With permission.) 11.9 ADJACENT CONSTRAINT GRAPH The ACG is proposed by Zhou and Wang [8] to model general floorplans. It tries to incorporate the advantages of both the adjacency graph and the constraint graph of a floorplan: edges in an ACG are between modules close to each other, thus the physical distance of two m odules can be measured directly in the graph; the floorplan area and m odule positions can be simply found by longest path computations because an ACG is a constraint graph. The idea behind the constraint graph is simple: a node represents a module and an edge in the horizontal graph represents the “left to” relation and an edge in the vertical graph represents the “below” one. The adjacency graph, on the other hand, is an undirected graph and has one edge between each pair of adjacent modules. As an illustration, for a floorplan given in Figure 11.20a, its constraint graphs are shown in Figure 11.20b, and its adjacency graph in Figure11.20c. ACG is defined as a constraint graph that has exactly one relation (horizontal or vertical) between every pair of nodes and has no transitive edge or cross to prevent redundancy. Here, a cross is defined as a subgraph on four nodes a, b, c, d such that edges (a, b ), (c, d) are of one type (e.g., vertical edges) while (a, c), (b, c ), (a, d), (b, d) are of the other type (e.g., horizontal edges). The edges in an ACG can be grouped according to the relations they represent, called groups H and V . From the definition, there are paths between any two modules within exact one group. Figure11.20d shows the ACG of the placement in Figure 11.20a. Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C011 Finals Page 225 29-9-2008 #24 Packing Floorplan Representations 225 a b d e c H V (a) (b) (c) (d) n a n e n e n e n e n c n d n b n a n c n d n b n a n a n c n c n d n d n b n b FIGURE 11.20 (a) Floorplan, (b) constraint graph, (c) adjacency graph, and (d) ACG. (From Zhou, H. and Wang, J., Proceedings of International Conference on Computer Design, 2004. With permission.) 11.9.1 ACG PROPERTIES The directed edges in an ACG form a total order on the nodes. In other words, the nodes can be arranged in a line such that all the edges are from left to right. The nodes can be doubly linked in a linear order (the total order). Edges are all directed from left to right. Each edge keeps its two end nodes and is kept in one edge list at each end node. Each node maintains four linked lists of edges: one for incoming H edges, one for outgoing H edges, one for incoming V edges, and one for outgoing V edges. The edges in each list are ordered according to the distances between end nodes: shorter edges come first. The structure is illustrated by an example in Figure 11.21a, where edges are shown in arcs: the edges above the node line are in group H and those below are in group V. Notice that node n d has one incoming H edge from n a , one outgoing H edge to n e ,twoincoming V edges from n b and n c , and no outgoing V edge. These four lists of edges have direct geometrical meanings, each connects to constraining modules in one direction: left, right, top, or bottom. And the edge orders in the lists will be either clockwise or counterclockwise, based on how H and V edges are interpreted. For example, if the H edges are interpreted as “left to” and the V edges as “below,” the geometrical interpretation of Figure 11.21a is illustrated in Figure11.21b, where H edges are ordered counterclockwise and V edges are ordered clockwise. On the basis of the ACG data structu re, it is simple and efficient to check and eliminate crosses. The patterns of a cross in the data structure are shown in Figure 11.22. Note that any node has edges to the three other nodes. If the cross formed on n a , n b , n c , n d is minimal, that is, no other cross exists on nodes between n a and n d , the nodes n b , n c , n d are consecutive among the neighbors of n a ; that is, except n c , no node between n b and n d is conn ecting to n a . Thus, if we follow the edges of the node n a in consecutive order, an edge type pattern VHH or HVV implies a cross. We can verify that no cross exists by running the checking process on edges starting from every node. Verifying that no cross exists can be done in linear time in terms of the number of edges. Total symmetry is another property of ACG. Given an ACG data structure, it is still a valid ACG when the node order is reversed or the edge groups H and V are swapped. This symmetry comes directly from the symmetry in the geometrical relations represented. The four geometrical (a) (b) abcde a bc d e FIGURE 11.21 (a) ACG st ructure and (b) geometrical relations. (From Zhou, H. and Wang, J., Proceedings of International Conference on Computer Design, 2004. With permission.) Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C011 Finals Page 226 29-9-2008 #25 226 Handbook of Algorithms for Physical Design Automation b c da b c da FIGURE 11.22 Patterns of a cross in an ACG. (From Zhou, H. and Wang, J., Proceedings of International Conference on Computer Design, 2004. With per mission.) relations, left, right, up, and down, are symmetrical with each other. On the b asis of symmetry, every provable result concerning edges in an ACG also implies the other three dual results. It simplifies our presentation in the sequel. If a result concerning edges in an ACG is correct, the result by exchanging left and right (and forward and backward) or H and V is also correct. Given the order on nodes, the information represented by V edges is redundant to that represented by H edges. For example, in Figure11.21a, with the node order, one group of edges can be constructed from the other group to satisfy the ACG definition. However, keeping both groups of edges facilitates the maintenance and operations on ACG. For example, without one group of edges, it is very hard to check whether the other group belongs to a valid ACG. In an ACG, any two consecutive V neighbors from a given node are connected by an H edge. 11.9.2 ACG PERTURBATIONS There are two types of perturbations for ACG, appending and swap. Appending. Appending is an operation to add a new node to the left or the right of a given ACG. We only discuss appending a node to the left of an ACG, and appending a node to the right of an ACG can be done in a similar method. This operation takes constant time for adding one edge and works as follows. First, the new node is added to the left of the node linked list. Then edges from the new node to some other nodes are added iteratively. In each iteration, the closest node that does not have a relation with the new node is identified and a suitable type of edge is then added between them. Because the type pattern VHH or HVV gives a cross, once the edge type changes, it needs to keep changing. The key operation in each iteration, that is, identifying the closest node not yet having a relation with the new node, can be done in constant time. At the beginning, when no edge is on the new node, it has no relation with its right node. During the iterations, when the new node has already some edges, a relation may be implied by a path from the new node to another node. When the new node has only V edges, the first H neighborof its furthest V neighbor is the closest node not having a relation with it. When the new node has last two edges of types V, H,theremust be an H edge from the V neighbor to the H neighbor, and the closest node not having a relation with the new node is connected to the V neighbor next to that H edge. The appending process costs linear time and storage complexity is the number of added edges. Swap. Swap is an operation that exchanges the positions of two adjacent nodes in the node list. Because an ACG requires edges directed from left to right, the original edge must be removed and a new edge is added to the other group. Because edges in one group represent horizontal relations and those in the other group represent vertical relations, swap will change the geometrical relation of two modules from horizontal to vertical, or vice versa. Suppose a swap is done on nodes n a , n b and the original edge (n a , n b ) is of type H. After the swap, edge (n a , n b ) is deleted from group H and a new edge (n b , n a ) is added to group V .AllH paths through (n a , n b ) are then broken, which may leave some node pairs without any relation. On the other hand, with the new edge (n b , n a ) is added, new V paths may formed, which may make some V edges become transitive. The swap operation will repair these d amages and make the ACG valid again. First, consider the transitive edges formed Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C011 Finals Page 227 29-9-2008 #26 Packing Floorplan Representations 227 in V group. Based on the way the swap operation is d efined, the transitive edges only appear locally. When edge (n b , n a ) is swapped into group V, transitive edges may only be formed from n b ’s left V neighbors to n a or from n b to n a ’s right V neighbors. On the basis of the result, we only need to check n b ’s V left neighbors to see whether they have V edges to n a . If so, these edge s n eed to be deleted. Similarly, we will also check n a ’s V neighbors to see whether they have V edges from n b , and if so, delete them. Then, the effects of deleting edge (n a , n b ) from group H are considered. Two nodes will lose their relation if originally there is only one H path that goes through edge (n a , n b ). The repair can also be done locally. It is easy to see that a path broken by deleting (n a , n b ) can be restored by connecting b a with the node after n b or n b with the node before n a . Furthermore, the path is the only one between the two nodes if and only if the path between n a and the node after n b and the path between n b and the node before n a are the only paths. Therefore, we need only to consider n a with n b ’s right H neighbors and n b with n a ’s left H neighbors. However, before adding an H edge between two nodes, we must make sure that there is no other H path between them. For each left H neighbor of n a , we will find its right H neighbor before n a and check whether that node has n b as its V neighbor. If so, we will add an H edge from the current left neighbor of n a to n b . Similar thing can be done with n b ’s right H neighbors. It should be noted that a swap may introduce crosses in the graph. 11.10 DISCUSSIONS Like the NPE (normalized polished expression) to the skewed slicing tree [2], B ∗ -tree is equivalent to O-tree, and TCG is equivalent to SP. Nevertheless, their neighborhood structures and operations distinguish them from each other in floorplan design. 11.10.1 COMPARISONS BETWEEN O-TREES AND B ∗ -TREES B ∗ -tree is equivalent to O-tree, yet with faster operations, simpler data structures, and greater flexi- bility in handling various placement constraints (and higher scalability fo r very large-scale designs; see Refs. [16–18]. To transform an O-tree into the correspondingB ∗ -tree, we first represent the O-tree using the left- child, rig ht-sibling binary tree [19]. Figure 11.23b shows an example of the left-child, right-sibling tree representing the O-tree in Figure11.23a. Then, we delete the root and make the left child of the root as the root of the B ∗ -tree, and the resulting B ∗ -tree is obtained as shown in Figure 11.23c. Similarly, given a B ∗ -tree, we can add a root and transform the B ∗ -tree (left-child, right-sibling tree) to the corresponding O-tree. Despite the equivalence, there is an intrinsic difference between these two representations. A B ∗ -tree can directly model a two-dimensional packing in a single binary tree while an O-tree only Root Root n a n b n f n g n c n d n e n k n j n i n l n h n a n b n f n h n a n b n f n c n i n l n j n d n g n e (a) (b) (c) n k n g n c n d n e n k n j n i n l n h FIGURE 11.23 (a) O-tree modeled, (b) O-tree, by using the left-child, right-sibling binary tree, and (c) corresponding B ∗ -tree. Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C011 Finals Page 228 29-9-2008 #27 228 Handbook of Algorithms for Physical Design Automation explicitly rep resents a one-dimensiona l packing. Therefore, as mentioned earlier, only one B ∗ -tree is sufficient for floorplan design while the O-tree operates on both a horizontal and a vertical trees. Further, the operation on an O-tree is not as efficient as that on a B ∗ -tree because the O-tree is not a binary tree and needs to keep the encoded tuple (S, π). The floorplan design algorithm p resented in Ref. [10] is deterministic by perturbing an O-tree systematically. The perturbation procedure is to delete a module from the O-tree, and then insert it into the best position based on its evaluation. Owing to the irregular structure, the candidate po sitions for inserting a node are limited to the external nodes (see Figure 11.3) to facilitate the updations of the encoding tuple. Inserting a node to a position other than external positions makes the update of the encoding tuple mor e difficult and time consuming. The inflexibility might cause the O-tree to deviate from the optimal during solutio n perturbations, and th us inevitably limit the quality of a floorplan design. This inflexibility might be a major drawback of the O-tre e representation, yet it can be fixed in B ∗ -trees. Further, searching and updating the encoding tuple, which are basic operations for the primitive search, insertion, and deletion in an O-tree, all takes linear time. In contrast, the search and insertion operations in an B ∗ -tree take only constant time. 11.10.2 EQUIVALENCE OF SP AND TCG SP and TCG are equivalent, too. We can transform between TCG and SP as follows: Let the fan-in (fan-out) of a node n i , denoted by F in (n i )(F out (n i )), be the nodes n j ’s with edges (n j , n i )((n i , n j )). Given a TCG, we can obtain a sequence + by repeatedly extracting a node n i with F in (n i ) =∅ in C h and F out (n i ) =∅in C v , and then deleting the edges (n i , n j )’s ((n j , n i )’s) from C h (C v ) until no node is left in C h (C v ). Similarly, we can transform a TCG into another sequence − by repeatedly extracting the node n i with F in (n i ) =∅both in C v and C h , and then deleting the edges (n i , n j )’s from both C h and C v until no node is left in C h and C v . Given an SP = ( + , − ), we can obtain a unique TCG = (C h , C v ) from the two constraint graphs of the SP by removing the source, sink, and associated edges. For example, the SP of Figure 11.24b is equivalent to the TCG of Figure 11.24c. It is proved in Ref. [4] that there exists a one-to-one correspondence between TCG and SP. Although TCG and SP are equivalent, their properties and induced operations are significantly different. Both SP and TCG are considered very flexible representations and construct constraint graphs to evaluate their packing cost. − of an SP corresponds to the ordering for packing modules to the bottom-left direction and thus can be used for guiding module packing. However, like most existing representations, the geometric relations among modules are not transparent to the operations of SP (i.e., the effect of an operation on the change of module relation is not clear before packing), (c) n c n b n a n g n e n f n c n f n d n e n g C v n a n b n d C h 3.5 2 2 3 1.5 5 1 1.5 2.5 3.5 2 1.5 1.5 2 (a) (b) a b c d f g e (cbfedag, abcdegf ) FIGURE 11.24 (a) Placement, (b) corresponding SP of (a), and (c) corresponding TCG of (b). Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C011 Finals Page 229 29-9-2008 #28 Packing Floorplan Representations 229 and thus we need to construct constraint graphs from scratch after each perturbation to evaluate the packing cost; this deficiency makes SP harder to converge to a desired solution and to handle placement with constraints ( e.g., boundary modules, preplaced modules, etc). In contrast to SP, the geometric relations among modules are transparent to TCG as well as its operations, facilitating the convergence to a desired solution. Further, TCG supports incremental update during operations and keeps the information of boundary modules as well as the shapes and the relative positions of modules in the representation. Unlike SP, nevertheless, we need to perform extra operations to obtain the module packing sequence and an additional O(m 2 ) time to find the reduction edges in the constraint graph for some operations. For both SP and TCG, the packing scheme by applying the longest path algorithm is time consum- ing because all edges in the constraint graphs are processed, even though they are not on the longest path. As shown in C h of Figure 11.24c, if we add a source with zero weight and connect it to those nodes with zero in-degree, the x coordinate of each module can be obtained by applying the longest path algorithm o n the resulting directed acyclic graph. Therefore, we have x g = max{x a , x b , x c , x d , x e }. To reduce the number of modules considered for placing a module, the concept of a horizontal (ver- tical) contour, denoted by R h (R v ), is proposed by-Lin and Chang in Refs. [5,13]. R h (R v ) is a list of modules b i ’s for which there exists no module b j with y j ≥ y i (x j ≥ x i ) and x j ≥ x i (y j ≥ y i );thatis, R h (R v ) is a list of modules in the horizontal (vertical) contour.For the placement of Figure 11.24a, for example, R h =b c , b f and R v =b g , b d , b e , b f , b c . To place a new module, we only need to consider the bends (and thus the modules) in the contour, and thus the packing time can be improved. Suppose we h ave packed the modules b a , b b , b c , b d ,andb e based on the sequence − . Then, the resulting horizontal contour R h =b c , b e , b d . Keeping R h , we only need to traverse the contour from b e , the successor of b e (in terms of in-order search tree traversal), to the last module b d , which have a horizontal relation with b g (because there is an edge (n d , n g ) in C h ). Thus, we have x g = x d . Packing modules in this way, we only need to consider x e and x d , and can get rid of the computation for a maximum value, leading to a faster packing scheme. 11.11 3D FLOORPLAN REPRESENTATIONS Recently, dynamically reconfigurable FPGAs are developed to improve logic capacity by time- sharing mechanism. We may use 3D-space (x, y, t) to model a dynamically reconfigurable system. The x and y coordinates represent the 2D-plane of FPGA resources (spatial dimension), while the t coordinate represents the time axis (temporal dimension). Each reconfigurable unit operations (RFUOP) (or task) (the execution unit in a reconfigurable FPGA) is modeled by a rectangular box (module). We may denote each module as a 3D box with spatial dimensions x and y and the temporal dimension t. Figure 11.25a shows a program with four parts of codes mapped into RFUOPs. Because of the placement constraint, we may not load all the modules into the device at the same time. Therefore, how to place these modules into the reconfigurable unit (RFU) becomes a 3D placement problem as shown in Figure11.25b. The objective is to allocate modules to optimize the area and execution time and to satisfy specified constraints. To deal with the 3D floorplanning problem, a few 3D floorplan representations extending the 2D floorplan ones are proposed. For example, sequence triple [20] and sequence quintuple [20] are extensions of sequence pair for 2D-packing. K-tree [21], T-tree [22], and 3D-sub TCG [23] are extensions of O-tree, B ∗ -tree, and TCG for 2D-packing, respectively. In the following sections, we briefly introduce T-tree, sequence triplet, and 3D-subTCG for 3D-packing. 11.11.1 T-TREE T-trees are inspired by B ∗ -trees, allowing each node with at most three children that r epresent the dimensional relationship among modules, as shown in Figure 11.26a. The key insight why it uses a Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C011 Finals Page 230 29-9-2008 #29 230 Handbook of Algorithms for Physical Design Automation RFUOP 1 RFUOP 2 RFUOP 3 RFUOP 4 (a) (b) 4 3.5 3 2.5 2 1.5 1 0.5 0 6 5 4 3 2 1 0 0 1 2 3 4 5 Width Height RFUOP 4 RFUOP 3 RFUOP 2 RFUOP 1 Duration FIGURE 11.25 (a) Running program and (b) 3D-placement of the running program. (From Yuh, P H., Yang, C L., Chang, Y W., and Chen, H L., Proceedings of Asia and South Pacific Design Automation Conference, 2004. With permission.) ternary tree is that for a 3D space, a task v i may have at most three tasks, one in each dimension, that are adjacent to v i . That is, task v j in the X + direction of v i ,taskv k in the Y + direction of v i ,andtask v l in the T + direction of v i , as shown in Figure11.26b. Thus, to model the relationship among these tasks, we treat v i as the root and v j , v k ,andv l are the children of v i . Because we have at most three relations in the 3D space, each parent has at most three children. The T-tree represents the geometric relationships between two modules as follows. If node n j is the left child of node n i , module v j must be placed adjacent to module v i on the T + direction, i.e., t j = t i + T i . If node n k is the middle child of node n i , module v k must be placed in the Y + direction of module v i , with the t-coordinate of v k equal to that of v i , i.e., t k = t i and y k ≥ y i +H i . If node n l is the right child of node n i , module v l must be placed on the X + direction of module v i , with the t-and y-coordinates equal to those of v i , i.e., t l = t i and y l = y i . j i lk t j = t i + T i t k = t i , y k ≥ y i + H i t l = t i , y l = y i Left child Right childMiddle child (a) (b) 20 15 10 Time 5 HeightWidth 0 0 5 10 15 20 25 0 5 10 15 20 25 v I v j v k v i FIGURE 11.26 (a) Structure of a T-tree and (b) three direct relations in a 3D space. (From Yuh, P H., Yang, C L., and Chang, Y W., P roceedings of International Conference on Computer-Aided Design, 2004. With permission.) Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C011 Finals Page 231 29-9-2008 #30 Packing Floorplan Representations 231 11.11.2 SEQUENCE TRIPLET Sequence triplet ST = ( 1 , 2 , 3 ) is an extension of sequence pair. In sequence triplet, every pair of modules is assigned with a unique topology. Let the function −1 i (n) denote the position of module n in sequence i . The topology of modules a and b is assigned by the following rules: RL-topology: −1 1 (a)< −1 1 (b) and −1 2 (a)> −1 2 (b) and −1 3 (a)< −1 3 (b) → b is right of a −1 1 (a)> −1 1 (b) and −1 2 (a)> −1 2 (b) and −1 3 (a)< −1 3 (b) → b is right of a FR-topology: −1 1 (a)< −1 1 (b) and −1 2 (a)< −1 2 (b) and −1 3 (a)< −1 3 (b) → b is rear of a AB-topology: −1 1 (a)< −1 1 (b) and −1 2 (a)> −1 2 (b) and −1 3 (a)> −1 3 (b) → b is below of a To find the corresponding3D placement for a sequence triplet, we first decode it to RL-, FR-, and AB-topology according to the above rules. Similar to the packing of sequence pair, then, three con- straint graphsG RL , G FR ,andG AB are constructed.Then,all modulelocationscan be determinedbythe longest path length to corresponding nodes. As an example, Figure 11.27 illustrates the 3D-packing with the topology decoded from the sequence triplet (bac, acb, abc). 11.11.3 3D-SUBTCG 3D-subTCG contains three transitive graphs, C h , C v ,andC t . For each module v i , it introduces one node n i in each graph. If v i v j (v i ⊥ n j ), it constructs one edge (n i , n j ) in C h (C v ).Ifv i must be executed before v j , it introduces an edge (n i , n j ) in C t . Figure11.28 shows a placement with six modules b a , b b , b c , b d , b e ,andb f whose widths, heights, and durations are (5, 1, 4), (3, 5, 4), (3, 2, 3), (3, 2, 1), (2, 2, 1), and (2, 2, 3), respectively. Figure 11.29 shows the 3D-subTCG corresponding to the placement of Figure 11.28. The value associated with a node in C h (C v or C t ) gives the width (height or duration) of the corresponding module, and the edge (n i , n j ) in C h (C v or C t ) denotes the horizontal (vertical or temporal) relation of v i and v j .In Figure11.29, because module v c (v a ) is left to (below) v b (v f ), there exists an edge (n c , n b )(n a , n f ) in C h (C v ). Similarly, because module v a must be executed before task v d , there exists an edge (n a , n d ) in C t . To obtain the coordinate of each module, we apply the longest path algorithm to the three graphs in a 3D-subTCG. a b c FIGURE 11.27 3D packing of the sequence triplet (bac, acb, abc). . Alpert /Handbook of Algorithms for Physical Design Automation AU7242_C011 Finals Page 222 29-9-2008 #21 222 Handbook of Algorithms for Physical Design Automation overlapped with. (c) corresponding B ∗ -tree. Alpert /Handbook of Algorithms for Physical Design Automation AU7242_C011 Finals Page 228 29-9-2008 #27 228 Handbook of Algorithms for Physical Design Automation explicitly rep. insight why it uses a Alpert /Handbook of Algorithms for Physical Design Automation AU7242_C011 Finals Page 230 29-9-2008 #29 230 Handbook of Algorithms for Physical Design Automation RFUOP 1 RFUOP