Hardware and Computer Organization- P13 pdf

Chapter 12 342 or 1.5 mA flowing through a 1000 ohm resistor. This gives us a voltage of 1.5 volts. Thus, a digital code from 0 to $F, will give us an analog voltage out from 0 to 1.5 volts in steps of 0.1 volts. Now we’re ready to understand how real A/D converters actually work. Figure 12.13, is a simplified diagram of a 16-bit analog to digital converter. At it’s heart is a 16-bit D/A converter and a comparator. The operation of the circuit is very straightforward. We start by applying the digital code $0000 to the D/A converter. The output of the D/A converter is 0 volts. The output is applied to the minus input of the comparator. The voltage that we want to digitize is applied to the positive input of the comparator. We then add a count of 1 to the digital code and apply the 16-bit code to the D/A converter. The output voltage will increase slightly because we have 65,534 codes to go. However, we also check the output of the comparator to see if it changed from 1 to 0. When the comparator’s output changes state, then we know that the output voltage of the D/A converter is just slightly greater than the unknown voltage. When it changes state we stop counting up and the digital code at the time the comparator changes state is the digital value of the unknown analog voltage. We call this a single-ramp A/D converter because we increase the test voltage in a linear ramp until the test voltage and the unknown voltage are equal. Imagine that you were building a single ramp A/D converter as part of a computer-based data log - ging system. You would have a 16-bit I/O port as your digital output port and a single bit ( TEST) input to sample the state of the comparator output. Starting from an initialized state you would keep incrementing the digital code and sampling the TEST input until you saw the TEST input go low. The flow chart of this algorithm for the single ramp A/D is shown in Figure 12.14. The single ramp has the problem that the digitizing time is Figure 12.13: A 16-bit, single ramp analog to digital converter. 16-bit D/A Converter D0 D15 ……………… To I/O Port Vo ut Vx + – Comp. Vo ut = > Vx TEST Figure 12.14: Algorithm for the single ramp A/D converter. Initialize COUNT to zero Read TEST bit IS TEST TRUE YES COUNT = Digitized Voltage NO Increment COUNT Vx COUNT 0000 FFFF TEST = TRUE Interfacing with the Real World 343 variable. A low voltage will digitize quickly, a high voltage will take longer. Also, the algorithm of the single ramp is analogous to a linear search algorithm. We already known that a binary search is more efficient than a linear search, so as you might imagine, we could also use this circuit to do a binary progression to zero in on the unknown voltage. This is called the successive approximation A/D converter and it is the most commonly used design today. The algorithm for the successive approximation A/D converter is just as you would expect of a binary search. Instead of starting at the digital code of 0x0000, we start at 0x8000. We check to see if the comparator output is 1 or 0, and we either set the next most significant bit to 1 or to 0. Thus, the 16-bit A/D can determine the unknown voltage in 16 tests, rather than as many as 65,535. The last type of A/D converter is the voltage to frequency converter, or V/F converter. This con - verter converts the input voltage into a stream of digital pulses. The frequency of this pulse stream is proportional to the analog voltage. For example, a V/F converter can have a transfer function of 10 KHz per volt. So at 1 volt in, it has a frequency output of 10,000 Hertz. At 10 volts input, the output is 100,000 Hertz, and so on. Since we know how to accurately measure quantities related to time, it is possible to very accurately measure frequency and count pulses, we are effectively doing a voltage to time conversion. The V/F converter has one very attractive feature. It is extremely effective in filtering out noise in an input signal. Suppose that the output of the V/F converter is around 50,000 Hz. Every second, the V/F emits approximately 50,000 pulses. If we keep counting and accumulating the count, in 10 seconds we count 500,000 pulses, in 100 seconds we count 5,000,000 pulses, and so forth. On a finer scale, perhaps each second the count is sometimes slightly greater than 50,000, some - times slightly less. The longer we keep counting, the more we are averaging out the noise in our unknown voltage. Thus, if we are willing to wait long enough, and our input voltage is stable for that period of time, we can average it to a very high accuracy. Now that we understand how an analog to digital converter actually works, let’s look at a complete data logging system that we might use to measure several analog inputs. Figure 12.15 is a simplified schematic diagram of such a data logger. There are several circuit elements in Figure 12.15 that we haven’t discussed before. For the purposes of this example it isn’t necessary to go into a detailed analysis of how they work. We’ll just look at their overall operation in the context of understanding how the process of data logging takes place. The block marked ‘Signal Conditioning’ is usually a set of amplifiers or other form of signal con - verters. The purpose is to convert the analog signal from the sensor to a voltage that is in the range of the A/D converter. For example, suppose that we are trying to measure the output signal from a sensor whose output voltage range is 0 to 1 mV. If we were to feed this signal directly into an A/D converter with an input range of 0–10 volts, we would never see the output of the sensor. Thus, it is likely that we would use an analog amplifier to amplify the sensor’s signal from the range of 0 to 0.001 volts to a range of 0 to 10 volts. Presumably each analog channel has different amplification requirements, so each channel is handled individually with its own amplifier or other type of signal conditioner. The point is that we want each channel’s sensor range to be optimally matched to the input range of the A/D converter. Chapter 12 344 Notice that the data logging system is designed to monitor 8 input channels. We could connect an A/D converter to each channel, but usually that is not the most economical solution. Another analog circuit element, called an analog multiplexer, is used to sequentially connect each of the analog channels to the A/D converter. In a very real sense, the analog multiplexer is like a set of tri-state output devices connected to a common bus. Only one output at a time is allowed to be connect to the bus. The difference here is that the analog multiplexer is capable of preserving the analog voltage of its input signal. The next device is called a sample and hold module, or S/H. This takes a bit more explaining to make sense of. The S/H module allows us to digitize an analog signal that is changing with time. Previously we saw that it can take a significant amount of time to digitize an analog voltage. A single-ramp A/D might have to count up several thousand counts before it matched the unknown voltage. Through all of these examples we always assumed that the unknown analog voltage was nice and constant. Suppose for a moment that it is the sound of a violin that we are trying to faith- fully digitize. At some instant of time we want to know a voltage point on the violin’s waveform, but what is it? If the unknown voltage of the violin changes significantly during the time it takes the A/D converter to digitize it, then we may have a very large error to deal with. The S/H module solves this problem. The S/H module is like a video freeze-frame. When the digital input is in the sample position (S/H = 1) the analog output follows the digital input. When the S/H input goes low, the analog voltage is frozen in time, and the A/D converter can have a reasonable chance of accurately digitiz - ing it. To see why this is, let’s consider a simple example. Suppose that we are trying to digitize a sine wave that is oscillating at a frequency of 10 KHz. Assume that the amplitude of the sine wave is ±5 volts. Thus, Figure 12.15: Simplified schematic diagram of a computer-based data logger. Analog input Channel 1 Analog input Channel 2 Analog input Channel 3 Analog input Channel 4 Analog input Channel 5 Analog input Channel 6 Analog input Channel 7 Analog input Channel 8 Signal Conditioning Analog Multiplexer Sample and Hold S / H A/D Converter Convert Data ready/EOC Computer System Output Port 0: bit 0 Interrupt input port Output por t 0: bit 1 Channel select 0 Channel select 1 Channel select 2 Output por t 0: bit 2 Output port 0: bit 3 Output port 0: bit 4 8-bit digitized data Input port 1 D0 D7 Interfacing with the Real World 345 V(t) = 5sin(ωt) where ω is the angular frequency of the sine wave, measured in radians per second. If this is new to you, just trust me and go with the flow. The angular frequency is just 2 πf, where f is the actual frequency of the sine wave in Hertz (cycles per second). The rate of change of the voltage is just the first derivative of V(t): dV/dt = –5ωcost(ωt) = –10πfcos(ωt). The maximum rate of change of the voltage with time occurs when cos( ωt) = 1, so dV/dt(maximum) = –10πf or –31.4 × 10x10 3 . Thus, the maximum rate of change of the voltage with time is 0.314 volts per microsecond. Now, if our A/D converter requires 5 microseconds to do a single conversion, then the unknown voltage may change as much as ~1.5 volts during the time the conversion is taking place. Since this is usu- ally an unacceptable large error source, we need the S/H module to provide a stable signal to the A/D converter during the time that the conversion is taking place. We now know enough about the system to see how it functions. Let’s do a step-by-step analysis: 1. Bits 2:4 of output port 0 select the desired analog channel to connect to the S/H module. 2. The conditioned analog voltage appears at the input of the S/H module. 3. Bit 1 of output port 0 goes low and places the S/H module in hold mode. The analog input voltage to be digitized is now locked at its value the instant of time when S/H went low. 4. Bit 0 of output port 0 issues a positive pulse to the A/D converter to trigger a convert cycle to take place. 5. After the required conversion interval, the end-of-conversion signal (EOC) goes low, caus- ing an interrupt to the computer. 6. The computer goes into its ISR for the A/D converter and reads in the digital data. 7. Depending on its algorithm, it may select another channel and read another input value, or continue digitizing the same channel as before. Figure 12.16 summarizes the degree of difficulty required to build an A/D converter of arbitrary speed and accuracy. The areas labeled “SK”, although theoretically rather straightforward to do, often require application-specific knowledge. For example, a heart monitor may be relatively slow and medium accuracy, but the requirements for electrically pro- tecting the patient from any shock hazards may impose addition requirement for a designer. Figure 12.16: Graph summarizing degree of difficulty producing an A/D converter of a given accuracy and conversion rate. From Horn 3 . Conversion Rate Effective number of bits SK = Specialized Knowledge 6 8 10 12 14 16 18 20 22 24 26 1 10 100 1K 10K 100K 1M 10M 100M 1G SK DIFFICUL T DIFFICULT TO IMPOSSIBLE FAIRLY EASY SK Chapter 12 346 The Resolution of A/D and D/A Converters Before we leave the topic of analog-to-digital and digital-to-analog converters we should try to summarize our discussion of what we mean by the resolution of a converter. The discussion applies equally to the D/A converter, but is somewhat easier to explain from the perspective of the A/D converter, so that’s what we’ll do. When we try to convert an analog voltage, or current or resistance (remember Ohm’s Law?) to a corresponding digital value, we’re faced with a fundamen - tal problem. The analog voltage is a continuously variable quantity while the digital value can only be represented in discrete steps. You’re already familiar with this problem from your C++ programming classes. You know, or should know, that certain operations are potentially dangerous because they could result in errone - ous results. In programming, we call this a “round-off error”. Consider the following example: float A = 3.1415906732678; float B = 3.1415906732566; if ( A == B) {do something} else {do something else} What will it do? Unless you knew how many digits of precision you can represent with a float on your computer, you may or may not get the result you expect. We have the same problem with A/D converters. Suppose I have a precision voltage source. This is an electronic device that can provide a very stable voltage for long periods of time. Typically, special batteries, called standard cells, are used for this. Let’s say that we just spent $500 and sent our standard cell back to the National Institute for Standards and Testing in Gaithersburg, MD. After a few weeks we get the standard cell back from NIST with a calibration certificate stating that the voltage on our standard cell is +1.542324567 volts at 23 degrees, Celsius (there is a slight voltage versus temperature shift, but we can account for it ). Now we hook this cell up to our A/D converter and take a reading. What will we measure? Right now you don’t have enough information to answer that so let’s be a bit more specific: A/D range: 0 volts – +2.00 volts A/D resolution: 10 bits A/D accuracy: +/– 1/2 least significant bit (LSB) This means that over the analog input range of 0.00 to +2.00 volts, there are 1024 digital codes available to us to represent the analog voltage. We know that 0.00 volts should give us a digital value of 00 0000 0000 and that +2.00 volts should give us a digital value of 11 1111 1111, but what about everything in between? At what point does the digital code change from 0x000 to 0x001? In other words, how sensitive is our A/D converter to changes, or fluctuations, in the ana - log input voltage? Let’s try to figure this out. Since there are 1023 intervals between 0x000 and 0x3FF we can calcu - late what interval in the analog voltage corresponds 1 change of the digital voltage. Interfacing with the Real World 347 Therefore 2.00 / 1023 = 1.9550 × 10 –3 volts. Thus, every time the analog voltage changes by about 2 millivolts (mV) we should see that the digital code also chang - es by 1 unit. This value of 2 mV is also what we would call the least significant bit because this amount of voltage change would cause the LSB to change by 1. Consider Figure 12.17. The stair-step looking curve represents the transfer function for our A/D converter. It shows us how the digital code will change as a function of the analog input voltage. No - tice how we get a digital code of 0x000 up until the analog voltage rises to almost 1 mV. Since the accuracy is 1/2 of the LSB, we have a range of analog voltage cen - tered about each analog interval (vertical dotted lines). This is the region defined by the horizontal portion of the line. For example, the digital code will be $001 for an analog voltage in the range of just under 1 mV to just under 3 mV. What happens if our analog voltage is right at the switching point? Suppose it is just about 0.9775 mV? Will the digital code be $000 or $001? The answer is, “Who knows?” Sometimes it might digitize as $000 and other times it might digitize as $001. Now back to our standard cell. Recall that the voltage on our standard cell is +1.542324567 volts. What would the digital code be? Well +1.542324567 / 1.9550 × 10 –3 = 788.913, which is almost 789. In hexadecimal, 789 10 equals 0x315, so that’s the digital code that we’d probably see. Is this resolution good enough? That’s a hard question to answer unless we know the context of the question. Suppose that we’re given the task of writing a software package that will be used to control a furnace in a manufacturing plant. The process that takes place in this furnace is quite sensitive to temperature fluctuations, so we must exhibit very tight control. That is, the temperature must be held at exactly 400 degrees Celsius, +/– 0.1 degree Celsius. Now the temperature in the furnace is being monitored by a thermocouple whose voltage output is measured as follows: Voltage output @ 400 degrees Celsius = 85.000 mV Transfer function = .02 mV / degree Celsius so far, this doesn’t look too promising. But we can do some things to improve the situation. The first thing we can do is amplify the very low level voltages output by the thermocouple and raise it to something more manageable. If we use an amplifier that can amplify the input voltage by a fac - tor of 20 times (gain = 20 ) then our analog signal becomes: Voltage output @ 400 degrees Celsius ( X 20 ) = 1.7000 V Transfer function ( X 20 ) = .4 mV / degree Celsius Figure 12.17: Transfer function for a 10-bit A/D converter over a range of 0 to 2.00 volts. Accuracy is 1/2 LSB. 011 010 001 000 Analog Voltage (mV) 0 1 2 3 4 Digital Code Chapter 12 348 Now the analog voltage range is OK. Our signal is 1.7 volts at 400 degrees Celsius. This is less than the 2.00 maximum voltage of the A/D converter, so we’re not in any danger of going off scale. What about our resolution? We know that our analog signal can vary over a range of almost 2 mV before the A/D converter will detect a change. Referring back to the specifications for our amplified ther - mocouple, this means that the temperature could shift by about 5 degrees Celsius before the A/D converter could detect a variation. Since we need to control the system to better than 0.1 degree, we need to use an A/D converter with better resolution. How much better? Well, we would predict that a change in the temperature of 0.1 degree Celsius would cause a voltage change of 0.04 mV. Therefore, we’ve got to improve our resolution by a factor of 2 mV / 0.04 mV or 50 times! Is this possible? Let’s see. Suppose we decided to sell our 10-bit A/D converter on eBay and use the proceeds to buy a new one. How about a 12-bit converter? That would give us 4096 digital codes. Going from 1024 codes to 4096 codes is only a 4× improvement in resolution. We need 50X. A 16-bit A/D converter gives us 65,536 codes. This is a 64× improvement. That should work just fine! Now, we have: A/D range: 0 volts – +2.00 volts A/D resolution: 16 bits A/D accuracy: +/– 1/2 least significant bit (LSB) Our analog resolution is now 2.00 volts / 65,535 or 0.03 mV per digital code step. Since we need to be able to detect a change of 0.04 mV, this new converter should do the job for us. Summary of Chapter 12 Chapter 12 covered: • The concepts of interrupts as a method of dealing with asynchronous events, • How a computer system deals with the outside world through I/O ports • How physical quantities in the real world events are converted to a computer-compatible format and vice versa through the processes of analog-to-digital conversion and digital-to- analog conversion. • The need for an analog to digital interface device called a comparator. • How Ohm’s Law is used to establish fixed voltage points for A/D and D/A conversion. • The different types of A/D converters and their advantages and disadvantages. • How accuracy and resolution impact the A/D conversion process. Chapter 12: Endnotes 1 Glenn E. Reeves, “Priority Inversion: How We Found It, How We Fixed It,” Dr. Dobb’s Journal, November, 1999, p. 21. 2 Arnold S. Berger, A Brief Introduction to Embedded Systems with a Focus on Y2K Issues, Presented at the Electric Power Research Institute Workshop on the Year 2000 Problem in Embedded Systems, August 24–27, 1998, San Diego, CA. 3 Jerry Horn, High-Performance Mixed-Signal Design, http://www.chipcenter.com/eexpert/jhorn/jhorn015.html. 349 1. Write a subroutine in Motorola 68000 assembly language that will enable a serial UART device to transmit a string of ASCII characters according to the following specification: a. The UART is memory mapped at byte address locations $2000 and $2001. b. Writing a byte of data to address $2000 will automatically start the data transmission pro- cess and it will set the Transmitter Buffer Empty Flag (TBMT) in the STATUS register to 0. c. When the data byte has been sent, the TBMT flag automatically returns to 1, indicating that TBMT is TRUE. d. The STATUS register is memory mapped at byte address $2001. It is a READ ONLY register and the only bit of interest to you is DB0, the TBMT flag. e. The memory address of the string to be transmitted is passed into the subroutine in register A6. f. The subroutine does not return any values. g. All registers used inside the subroutine must be saved on entry and restored on return. h. All strings consist of the printable ASCII character set, 00 thru $7F, located in successive memory locations and the string is terminated by $FF. The UART is shown schematically in the figure shown below: Notes: • Remember, you are only writing a subrou- tine. There is no need to add the pseudo-ops that you would also add for a program. • You may assume that the stack is already defined. • You may use EQUates in your program source code to take advantage of symbolic names. 2. Examine the block of 68K assembly language code shown below. There is a serious error in the code. Also shown is the content of the first 32-bytes memory. a. What is the bug in the code? b. What will the processor do when the error occurs? Explain as completely as possible, given the information that you have. Exercises for Chapter 12 DATA REGISTER Shift out STATUS REGISTER Memor y address $2000 Memory address $2001 TB = TBMT FLAG X = Don’t care DB7 DB0 DB7 DB0 x x x x x x x TB Chapter 12 350 org $400 start lea $2000,A0 move.l #$00001000,D0 move.l #$0000010,D1 loop divu D1,D0 move.l D0,(A0)+ subq.b #08,D1 bpl loop end $400 Memory contents (Partial) 00000000 00 00 A0 00 00 00 04 00 00 AA 00 00 00 AA 00 00 00000010 00 AA 00 00 00 CC AA 00 00 AA 00 00 00 AA 00 00 Note: The first few vectors of the Exception Vector Table are listed below: Vector # Memory Address Description 0 $00000000 RESET: supervisor stack pointer 1 $00000004 RESET: program counter 2 $00000008 Bus Error 3 $0000000C Address Error 4 $00000010 Illegal instruction 5 $00000014 Zero Divide 6 $00000018 CHK Instruction 7 $0000001C TRAPV instruction 8 $00000020 Privilege violation 3. Assume that you have two analog-to-digital converters as shown in the table, below: Converter type Resolution (bits) Clock rate (MHz) Range (volts) Single Ramp 16 1.00 0 to +6.5535 Successive Approximation 16 1.00 0 to +6.5535 How long (time in microseconds) will it take each type of converter to digitize an analog volt- age of +1.5001 volts? 4. Assume that you may assign a priority level from 0 (lowest) to 7 (highest, NMI ) for each of the following processor interrupt events. For each of the following events, assign it a priority level and briefly describe your reason for assigning it that level. a. Keyboard strike input. b. Imminent Power failure. c. Watchdog timer. d. MODEM has data available for reading. e. A/D converter has new data available. f. 10 millisecond real time clock tick. g. Mouse click. h. Robot hand has touched solid surface. i. Memory parity error. Interfacing with the Real World 351 5. Assume that you have an 11-bit A/D converter that can digitize an analog voltage over the range of –10.28V to + 10.27volts. The output of the A/D converter is formatted as a 2’s com - plement positive or negative number, depending upon the polarity of the analog input signal. a. What is the minimum voltage that an analog input voltage could change and be guaran - teed to be detected by a change in the digital output value? b. What is the binary number that represents an analog voltage of –5.11 volts? c. Suppose that the A/D converter is connected to a microprocessor with a 16-bit wide data bus. What would the hexadecimal number be for an analog voltage of +8.96V? Hint: It is not necessary to do any rescaling of the 11-bit number to 16-bits. d. Assume that the A/D converter is a successive approximation-type A/D converter. How many samples must it take before it finally digitizes the analog voltage? e. Suppose that the A/D converter is being controlled by a 1 MHz clock signal and a sample occurs on the rising edge of every clock. How long will it take to digitize an analog voltage? 6. Assume that you are the lead software designer for a medical electronics company. Your new project is to design the some of the key algorithms for a line of portable heart monitors. In order to test some of your algorithms you set up a simple experiment with some of the prelimi - nary hardware. The monitor will use a 10-bit analog to digital converter (A/D) with an input range of 0 to 10 volts. An input voltage of 0 volts results in a binary output of 0000000000 and an input voltage of 10 volts results in a binary output of 1111111111. It digitizes the analog signal every 200 microseconds. You decide to take some data. Shown below is a list of the digitized data values (in hex). 2C8, 33B, 398, 3DA, 3FC, 3FB, 3D7, 393, 334, 2BF, 23E, 1B8, 137, 0C4, 067, 025, 003, 004, 028, 06C, 0CB, 140, 1C1, 247 Once you collect the data you want to write it out to a strip chart meter and display it so a doctor can read it. The strip chart meter has an input range of –2 volts to +2 volts. Fortunately, your hardware engineer has designed a 10-bit digital to analog (D/A) circuit such that a binary digital input value of 0000000000 cause an analog output of –2 volts and 1111111111 causes an output of +2 volts. You write a simple algorithm that sends the digitized data to the chart so you can see if everything is working properly. a. Show what the chart recorder would output by plotting the above data set on graph paper. b. Is there any periodicity to the waveform? If so, what is the period and frequency of the waveform? 7. Suppose that you have a 14-bit, successive approximation, A/D converter with a conversion time of 25 microseconds. a. What is the maximum frequency of an AC waveform that you can measure, assuming that you want to collect a minimum of 4 samples per cycle of the unknown waveform? b. Suppose that the converter can convert an input voltage over the range of –5V to +5V, what is the minimum voltage change that should be measurable by this converter? c. Suppose that you want to use this A/D converter with a particular sample and hold circuit (S/H) that has a droop rate of 1 volt per millisecond. Is this particular S/H circuit compat- ible with the A/D converter? If not, why? [...]... 64 Sigh… Processor Architectures, CISC, RISC and DSP The 68K processor and its instruction set, the 8086 processor and its instruction set are examples of the complex instruction set computer (CISC), architecture CISC is characterized by having many instructions and many addressing modes You’ve certainly seen for yourself many assembly language instructions and variations on those instructions we have... difficult to speed up because distributing and synchronizing the clock over the entire area of the chip becomes a difficult engineering task A computer with a von Neumann architecture has a single memory space that contains both the instructions and the data, see Figure 13.1 The CISC computer has a single set of busses linking the CPU and memory Instructions and data must share the same path to the CPU... for speed has been led by Intel and AMD, and today’s 3+ gigahertz processors are the Athlons and Pentiums Both CISC and RISC can get the job done Although RISC processors are very fast and efficient, the executable code images for RISC processors tend to be larger because there are fewer instructions available to the compiler Although this distinction is fading fast, CISC computers still tend to be prevalent... intensive 367 Chapter 13 Desktop computers are used for multimedia and games Workstations are used for data intensive applications such as design and simulation Embedded systems are used for games (Nintendo) and telecommunications applications (routers, bridges, switches) Motorola stopped CISC development at the 68060 and designed two new RISC architectures, ColdFire and PowerPC, to replace the 680X0... 680X0 family AMD stopped with the 586 and Intel stopped with the original Pentium The modern processors from AMD and from Intel are a merging of the RISC and CISC technologies, and have been designed to be able to take in the original Intel X86 instruction set and translate it internally to a sequence of RISC-like instructions that the native architecture can handle very rapidly As we’ve seen, RISC... involving memory operands inherently take longer than operations between internal registers We must first load the memory operand before we can use it Here’s the problem Suppose that we’re doing an arithmetic operation in which two operands are added together to produce a result The first instruction loads a memory operand into a register and the next instruction takes that register and adds it to a second... October 1980 pp 25–33 Manolis G H Kavantis, Reduced Instruction Set Computer Architectures for VLSI, The MIT Press, Cambridge, MA, 1986 David Resnick, Cray Corporation, Private Communication J.E Thornton, Design of a Computer: The Control Data 6600, Scott, Foresman and Company, Glenview, Ill, 1970 W.C Alexander and D.B Wortman, Static and Dynamic characteristics XPL Programs, pp 41–46, November 1975,... Complex Instruction Set Computer (CISC) In their quest to create more and more complex and elegant instructions and addressing modes, the CPU designers were creating more and more complex CPUs that were becoming choked by their own complexity The scientists asked the question, “Suppose we do away with all but the most necessary instructions and addressing modes Could the resultant simplicity outweigh the... Memory Data and too modest to place his name Status Status Busses on it) The Harvard architecture Busses features a separate instruction Figure 13.1: Memory architecture for the von Neumann (CISC) memory and data memory With and Harvard (RISC) architectures this type of a design, both data and instructions could be operated on independently Another subtle difference between the von Neumann and Harvard... pipeline-based computer? • All instructions are the same length • There are just a few instruction formats • Memory operands appear only in loads and stores • ALU operations are between registers What kinds of architectural decisions make CPU designers want to retire and become mimes in Boulder, Colorado? • Variable length instructions • Instructions with variable execution times • Wide variety of instructions and . special batteries, called standard cells, are used for this. Let’s say that we just spent $500 and sent our standard cell back to the National Institute for Standards and Testing in Gaithersburg,. been led by Intel and AMD, and today’s 3+ gigahertz processors are the Athlons and Pentiums. Both CISC and RISC can get the job done. Although RISC processors are very fast and efficient, the. Architectures, CISC, RISC and DSP The 68K processor and its instruction set, the 8086 processor and its instruction set are examples of the complex instruction set computer (CISC), architecture.