Hardware and Computer Organization- P10 potx

Chapter 9 252 D4=00000000 D5=00000000 D6=00000000 D7=00000000 C=1 >MOVE.L 8(A6),D0 PC=000474 SR=2000 SS=00000FE0 US=00000000 X=0 A0=00000FF8 A1=00000000 A2=00000000 A3=00000000 N=0 A4=00000000 A5=00000000 A6=00000FE0 A7=00000FE0 Z=0 D0=00000001 D1=00000FF8 D2=00000001 D3=FFFFFFFF V=0 D4=00000000 D5=00000000 D6=00000000 D7=00000000 C=0 >ADD.L (A0),D0 PC=000476 SR=2000 SS=00000FE0 US=00000000 X=0 A0=00000FF8 A1=00000000 A2=00000000 A3=00000000 N=0 A4=00000000 A5=00000000 A6=00000FE0 A7=00000FE0 Z=0 D0=000015B4 D1=00000FF8 D2=00000001 D3=FFFFFFFF V=0 D4=00000000 D5=00000000 D6=00000000 D7=00000000 C=0 >BRA.L $0000047A PC=00047A SR=2000 SS=00000FE0 US=00000000 X=0 A0=00000FF8 A1=00000000 A2=00000000 A3=00000000 N=0 A4=00000000 A5=00000000 A6=00000FE0 A7=00000FE0 Z=0 D0=000015B4 D1=00000FF8 D2=00000001 D3=FFFFFFFF V=0 D4=00000000 D5=00000000 D6=00000000 D7=00000000 C=0 >NOP PC=00047C SR=2000 SS=00000FE0 US=00000000 X=0 A0=00000FF8 A1=00000000 A2=00000000 A3=00000000 N=0 A4=00000000 A5=00000000 A6=00000FE0 A7=00000FE0 Z=0 D0=000015B4 D1=00000FF8 D2=00000001 D3=FFFFFFFF V=0 D4=00000000 D5=00000000 D6=00000000 D7=00000000 C=0 >UNLK A6 PC=00047E SR=2000 SS=00000FE4 US=00000000 X=0 A0=00000FF8 A1=00000000 A2=00000000 A3=00000000 N=0 A4=00000000 A5=00000000 A6=00000FFC A7=00000FE4 Z=0 D0=000015B4 D1=00000FF8 D2=00000001 D3=FFFFFFFF V=0 D4=00000000 D5=00000000 D6=00000000 D7=00000000 C=0 >RTS PC=000430 SR=2000 SS=00000FE8 US=00000000 X=0 A0=00000FF8 A1=00000000 A2=00000000 A3=00000000 N=0 A4=00000000 A5=00000000 A6=00000FFC A7=00000FE8 Z=0 D0=000015B4 D1=00000FF8 D2=00000001 D3=FFFFFFFF V=0 D4=00000000 D5=00000000 D6=00000000 D7=00000000 C=0 >ADDQ.L #8,SP PC=000432 SR=2000 SS=00000FF0 US=00000000 X=0 A0=00000FF8 A1=00000000 A2=00000000 A3=00000000 N=0 A4=00000000 A5=00000000 A6=00000FFC A7=00000FF0 Z=0 D0=000015B4 D1=00000FF8 D2=00000001 D3=FFFFFFFF V=0 D4=00000000 D5=00000000 D6=00000000 D7=00000000 C=0 >MOVE.L D0,D3 PC=000434 SR=2000 SS=00000FF0 US=00000000 X=0 1000 00 00 00 00 OFFC 00 00 00 00 OFF8 00 00 15 B3 OFF4 00 00 00 00 OFF0 00 00 00 00 OFEC 00 00 0F F8 OFE8 00 00 00 01 OFE4 00 00 04 30 OFE0 00 00 0F FC 1000 00 00 00 00 OFFC 00 00 00 00 OFF8 00 00 15 B3 OFF4 00 00 00 00 OFF0 00 00 00 00 OFEC 00 00 0F F8 OFE8 00 00 00 01 OFE4 00 00 04 30 OFE0 00 00 0F FC 1000 00 00 00 00 OFFC 00 00 00 00 OFF8 00 00 15 B3 OFF4 00 00 00 00 OFF0 00 00 00 00 OFEC 00 00 0F F8 OFE8 00 00 00 01 OFE4 00 00 04 30 OFE0 00 00 0F FC Advanced Assembly Language Programming Concepts 253 A0=00000FF8 A1=00000000 A2=00000000 A3=00000000 N=0 A4=00000000 A5=00000000 A6=00000FFC A7=00000FF0 Z=0 D0=000015B4 D1=00000FF8 D2=00000001 D3=000015B4 V=0 D4=00000000 D5=00000000 D6=00000000 D7=00000000 C=0 >ADDQ.L #1,D3 PC=000436 SR=2000 SS=00000FF0 US=00000000 X=0 A0=00000FF8 A1=00000000 A2=00000000 A3=00000000 N=0 A4=00000000 A5=00000000 A6=00000FFC A7=00000FF0 Z=0 D0=000015B4 D1=00000FF8 D2=00000001 D3=000015B5 V=0 D4=00000000 D5=00000000 D6=00000000 D7=00000000 C=0 >NOP PC=000438 SR=2000 SS=00000FF0 US=00000000 X=0 A0=00000FF8 A1=00000000 A2=00000000 A3=00000000 N=0 A4=00000000 A5=00000000 A6=00000FFC A7=00000FF0 Z=0 D0=000015B4 D1=00000FF8 D2=00000001 D3=000015B5 V=0 D4=00000000 D5=00000000 D6=00000000 D7=00000000 C=0 >MOVE.L (SP)+,D2 PC=00043A SR=2004 SS=00000FF4 US=00000000 X=0 A0=00000FF8 A1=00000000 A2=00000000 A3=00000000 N=0 A4=00000000 A5=00000000 A6=00000FFC A7=00000FF4 Z=1 D0=000015B4 D1=00000FF8 D2=00000000 D3=000015B5 V=0 D4=00000000 D5=00000000 D6=00000000 D7=00000000 C=0 >MOVE.L (SP)+,D3 PC=00043C SR=2004 SS=00000FF8 US=00000000 X=0 A0=00000FF8 A1=00000000 A2=00000000 A3=00000000 N=0 A4=00000000 A5=00000000 A6=00000FFC A7=00000FF8 Z=1 D0=000015B4 D1=00000FF8 D2=00000000 D3=00000000 V=0 D4=00000000 D5=00000000 D6=00000000 D7=00000000 C=0 >UNLK A6 PC=00043E SR=2004 SS=00001000 US=00000000 X=0 A0=00000FF8 A1=00000000 A2=00000000 A3=00000000 N=0 A4=00000000 A5=00000000 A6=00000000 A7=00001000 Z=1 D0=000015B4 D1=00000FF8 D2=00000000 D3=00000000 V=0 D4=00000000 D5=00000000 D6=00000000 D7=00000000 C=0 >RTS You may be curious why the last instruction is an RTS. If this pro- gram were running under an operating system, and the C compiler expects that you are, this instruction would return the control to the operating system. There’s one last matter to discuss before we leave 68000 assembly language and move on to other architectures. This is the subject of instruction set decomposition. We’ve already looked at the archi - tecture from the point of view of the instruction set, the addressing 1000 00 00 00 00 OFFC 00 00 00 00 OFF8 00 00 15 B3 OFF4 00 00 00 00 OFF0 00 00 00 00 OFEC 00 00 0F F8 OFE8 00 00 00 01 OFE4 00 00 04 30 OFE0 00 00 0F FC 1000 00 00 00 00 OFFC 00 00 00 00 OFF8 00 00 15 B3 OFF4 00 00 00 00 OFF0 00 00 00 00 OFEC 00 00 0F F8 OFE8 00 00 00 01 OFE4 00 00 04 30 OFE0 00 00 0F FC 1000 00 00 00 00 OFFC 00 00 00 00 OFF8 00 00 15 B3 OFF4 00 00 00 00 OFF0 00 00 00 00 OFEC 00 00 0F F8 OFE8 00 00 00 01 OFE4 00 00 04 30 OFE0 00 00 0F FC 1000 00 00 00 00 OFFC 00 00 00 00 OFF8 00 00 15 B3 OFF4 00 00 00 00 OFF0 00 00 00 00 OFEC 00 00 0F F8 OFE8 00 00 00 01 OFE4 00 00 04 30 OFE0 00 00 0F FC Chapter 9 254 modes and the internal register resources. Now, we’ll try to relate that back to our discussion of state machines to see how the actual encoding of the instructions takes place. The process of converting machine language back to assembly language is called disassembly. A disassembler is a program that examines the machine code in memory and attempts to convert it back to machine language. This is an extremely useful tool for debugging and, in fact, most debug - gers have a built-in disassembly feature. You may recall from our introduction to assembly language that the first word of an instruction is called the opcode word. The op-code word contains an opcode, which tells the computer (what to do), and it also contains zero, one or two effective address fields (EA). The effective address fields contain the encoded information that tell the processor how to retrieve the operands from memory. In other words, what is the effective address of the operand(s). As you already know, an operand might be an address register or a data register. The operand might be located in memory, but pointed to by the address register. Consider the form of the instructions shown below: OP Code Destination EA Source EA DB15 DB12 DB11 DB6 DB5 DB0 The op code field consists of 4 bits, DB12 through DB15. This tells the computer that the instruc- tion is a MOVE instruction. That is, move the contents of the memory location specified by the source EA to the memory location specified by the destination EA. Furthermore, the effective address field is further decomposed into a 3-bit Mode field and a 3-bit Subclass (register) field. This information is sufficient to tell the computer everything it needs to know in order to com - plete the instruction, but the op-code word itself may or may not contain all of the information necessary to complete the instruction. The computer may have to go out to memory one or more additional times to fetch additional information about the source EA or the destination EA in order to complete the instruction. This begins to make sense if we recall that the op-code word is the part of the instruction that must be decoded by the microcode-driven state machine. Once the proper state machine sequence has been established by the decoding of the op-code word, the additional fetching of operands from memory, if necessary, can proceed. For example, suppose that the source EA and destination EA are both data registers. In other words, the instruction is: MOVE.W D0,D1 Since both the source and the destination are internal registers, there is no additional information needed by the processor to execute the instruction. For this example, the instruction is the same length as the op code, 16-bits long, or one word in length. However, suppose that the instruction is: MOVE.W #$00D0,D1 Now the # sign tells us that the source EA is an immediate operand (the hexadecimal number $00D0 ) and the destination EA is still register D1. In this case, the op code word would tell us that the source is an immediate operand, but it can’t tell us what is the actual value of the immediate operand. The computer must go out to memory again and retrieve (fetch) the next word in memory after the op code word. This is the data value $00D0. If this instruction resided in memory at mem - Advanced Assembly Language Programming Concepts 255 ory location $1000, the op code word would take up word address $1000 and the operand would be at memory location $1002. The effective address field is a 6-bit wide field that is further subdivided into two, 3-bit fields called mode and register. The 3-bit wide mode field can specify one of 8 possible addressing modes and the register filed can specify one of 8 possible registers, or a subclass for the mode field. The MOVE instruction is unique in that it has two possible effective address fields. All of the other instructions that may contain an effective address field have only one possible effective address. This might seem strange to you at first, but as you’ll see, almost all of the other instructions that use two operands must involve a register and a single effective address. Let’s return our attention to the MOVE instruction. If we completely break it down to its constitu - ent parts it would look like this: 0 0 Size Destination Register Destination Mode Source Mode Source Register DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 The subclasses are only used with mode 7 addressing modes. These modes are: You may have noticed the Move to Address Register (MOVEA) instruction and wondered why we needed to create a special mnemonic for an ordinary MOVE instruction. Well first of all, address registers are extremely useful and impor - tant internal resources. Having an address register means that we can do register arithmetic and manipulate pointers. We can also compare the values in registers and make decisions based upon the address of data. The MOVEA instruction is a more standard type of instruction because there is only one effective address for the source operand. The destination operand is one of the 7 address registers. Thus, the destination mode is hard coded to be an address register. However, we needed to create a special instruction for the MOVEA operation because a word fetch on an odd byte boundary is an illegal access and the MOVEA instruction prevents this from occuring. The majority of the instructions take the form shown below. Op Code Register Op Mode Source or Destination EA DB15 DB12 DB11 DB9 DB8 DB6 DB5 DB0 The op code field would specify whether the instruction is an ADD, AND, CMP, etc. The regis- ter field specifies which of the internal registers is the source or destination of the operation. The op mode field is a new term. This specifies several one of 8 subdivisions for the instruction. For example, this field would specify if the internal register was the source or the destination of the operation and if the size was byte, word or long word. We’ll see this a bit later. Single operand instructions, such as CLR (set the contents of the destination EA to zero) have a slightly different form. Op Code Size Destination EA DB15 DB8 DB7 DB6 DB5 DB0 Mode 7 addressing Subclass Absolute word 000 Absolute long word 001 Immediate 100 PC relative with displacement 010 PC relative with index 011 Chapter 9 256 The JMP (Jump) and JSR (Jump to Subroutine) are also single operand instructions. Both place the destination EA into the program counter so that the next instruction is fetched from the new location, rather than the next instruction in the sequence. The JSR instruction will also automati - cally place the current value of the program counter onto the stack before the contents of the PC are replaced with the destination EA. Thus, the return location is saved on the stack. The branch instructions, Bcc (branch on condition code), is similar to the jump instruction in that it modifies the contents of the PC so that the next instruction may be fetched out of sequence. However, the branch instructions differ in two fundamental ways: 1. There is no effective address. A displacement value is added to the current contents of the PC so that the new value is determined as a positive or negative shift from the current value. Thus, a displacement is a relative jump, rather than an absolute jump. 2. The branch is taken only if the condition code being tested evaluates to true. 0 1 1 0 Condition Displacement DB15 DB12 DB11 DB8 DB7 DB0 The displacement field is an 8-bit value. This means that the branch can move to another locations either +127 bytes or –128 bytes away from the present location. If a greater branch is desired, then the displacement field is set to all zeroes and the next memory word is used as an immediate value for the displacement. This gives a range of +16,383 to –16,384 bytes. Thus, if the computer is executing a tight loop, then it will operate more efficiently if an 8-bit displacement is used. The 16-bit displacement allows it go further on a branch, but at a cost of an additional memory fetch operation. Earlier, I said that the branch is executed if the condition code evaluates to true. This means that we can test more than just the state of one of the flags in the CCR. The table below shows us the possible ways that a branch condition may be evaluated. CC carry clear 0100 C LS low or same 0011 C + Z CS carry set 0101 C LT less than 1101 N*V + N*V EQ equal 0111 Z MI minus 1011 N GE greater or equal 1100 N*V + N*V NE not equal 0110 Z GT greater than 1110 N*V*Z + N*V*Z PL plus 1010 N HI high 0010 C*Z VC overflow clear 1000 V LE less or equal 1111 Z + N*V + N*V VS overflow set 1001 V The reason for so many branch test conditions is that the branch instructions BGT, BGE, BLT and BLE are designed to be used with signed arithmetic operations and the branch instructions BHI, BCC, BLS and BCS are designed to be used with unsigned arithmetic operations. Some instructions, such as NOP and RTS (Return from Subroutine) take no operands and are com- pletely specified by their op code word. Earlier we discussed the role of the op mode field on how a general instruction operation may be further modified. A good example to illustrate how the op mode field works is to examine the ADD instruction and all of its variations in more detail. Consider Figure 9.3 Advanced Assembly Language Programming Concepts 257 Notice how the op mode field, contained in bits 6, 7 and 8, de- fine the format of the instruction. The ADD instruction is represen- tative of most of the “normal” instructions. Other classes of instructions require special consideration. For exam - ple, the MOVE instruction contains two effective addresses. Also, all immediate addressing mode instructions have the source oper - and addressing mode hard-coded into the instruction and thus, it is not really an effective address. This would include instructions such as add immediate ( ADDI) and subtract immediate (SUBI). Example of a Real Machine Before we move on to consider other architectures let’s do something a bit different, but still relevant to our discussion of assembly code and computer architecture. Up to now, we’ve really ignored the fact that ultimately the code we write will have to run on a real machine. Granted, memory test programs aren’t that exciting, but at least we can imagine how they might be used with actual hardware. In order to conclude our discussion of assembly language coding, let’s look at the design of an actual 68000-based system. Figures 9.4 and 9.5 are simplified schematic diagrams of the processor and memory portions of a 68K computer system. Not all the signals are shown, but that won’t take anything away from the discussion. Also, we don’t want the EE’s get - ting too upset with us. Figure 9.3 Op mode decomposition for the ADD instruction 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 0 1 n n n OP OP OP EA EA EA EA EA EA 1 1 0 1 n n n 0 0 0 EA EA EA EA EA EA 1 1 0 1 n n n 0 0 1 EA EA EA EA EA EA 1 1 0 1 n n n 0 1 0 EA EA EA EA EA EA 1 1 0 1 n n n 1 0 0 EA EA EA EA EA EA 1 1 0 1 n n n 1 0 1 EA EA EA EA EA EA 1 1 0 1 n n n 1 1 0 EA EA EA EA EA EA 1 1 0 1 n n n 0 1 1 EA EA EA EA EA EA 1 1 0 1 n n n 1 1 1 EA EA EA EA EA EA D 0 7 0 7 ADD.B <ea>,Dn ADD.W <ea>,Dn ADD.L <ea>,Dn ADD.B Dn,<ea> ADD.W Dn,<ea> ADD.L Dn,<ea> ADDA.W <ea>,An ADDA.L <ea>,An CS RO M H CS ROM L CS RAM H CS RAM L WRITE READ RESET GENERATOR 16 MHz Cloc k TO I/O ADDRESS DECODER INT7 INT6 INT5 INT4 INT3 INT2 INT1 A1 A23 D0 D1 5 A1 D15 D0 A17 A18 A19 A20 A21 A22 A23 MC68000 AS UDS LDS DTACK BERR CLK IN RESET IPL2 IPL1 IPL0 WR RAM SELECT ROM SELECT Note: Not all 68000 signals are shown Figure 9.4 Simplified schematic diagram of a 68000-based computer system. Only the 68000 CPU is shown in this figure. Chapter 9 258 Referring to the address bus of Figure 9.4, we see that that there is no address bit labeled A0. The A0 is synthesized by the state machine by activating UDS or LDS as we saw in Figure 7.6. The OR gates on the right side of the figure are actually being used as negative logic AND gates, since all of the relevant control signals are asserted LOW. The Valid Address signal in the 68K environment is called Address Strobe and is labeled AS in the diagram. This signal is routed to two places. It is used as a qualifying signal for the READ and WRITE operations and is gated through the two lower OR gates in the figure (keep thinking, “ negative logic AND gates” ) and to the ADDRESS DECODER block. You should have no trouble identifying this functional block and how it works. In a pinch, you could probably design it your - self! Thus, we will not decode an address range until the AS signal is asserted LOW, guaranteeing a valid address. The I/O decoder also decodes our I/O devices, although they aren’t shown in this figure. Since the 68K does not have separate READ and WRITE signals, we synthesize the READ signal with the NOT gate and the OR gate. We also use the OR gate and the AS signal to qualify the READ and WRITE signals, with the OR gate functioning as a negative logic AND gate. Strictly speaking this isn’t necessary because we are already qualifying the ADDRESS DECODER in the same way. Figure 9.5 Simplified schematic diagram of the memory system for the 68K computer of Figure 9.4. CS RO M H CS RAM L CS RO M L WRITE READ A1 A17 D0 D16 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 CS RAM H D8 D15 D0 D7 D0 D1 D2 D3 D4 D5 D6 D7 CS OE A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 D0 D1 D2 D3 D4 D5 D6 D7 ~CS ~OE A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 D0 D1 D2 D3 D4 D5 D6 D7 CS OE A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 D0 D1 D2 D3 D4 D5 D6 D7 CS OE WR WR RAM HIGH RAM LOW ROM HIGH ROM LOW Advanced Assembly Language Programming Concepts 259 The last block of note is the Interrupt Controller block at the bottom left hand side of the diagram. The 68K uses 3 active LOW interrupt inputs labeled IP0, IP1 and IP2. All three lines going low would signal a level 7 interrupt. We’ll study interrupts in the next chapter. The inputs to the Inter - rupt Controller are 7 active low inputs labels INT1 – INT7. If the INT7 line was brought LOW, all of the output lines would also go LOW, indicating that INT7 is a level 7 interrupt. Now, if INT6 is low ( IP0 = 1, IP1 = 0, IP2 = 0 ) and INT5 also went LOW, the outputs wouldn’t change because the Interrupt controller both decodes the interrupt inputs and prioritizes them. Figure 9.5 is the memory side of the computer. It is made up of two 128K × 8 RAM chips and two 128K x 8 ROM chips. Notice how the pairing of the devices and the two chip-select signals from the processor gives us byte writing control. The rest of this circuit should look very familiar to you. The memory system in this computer design consists of 256K bytes of ROM, located at address $000000 through $3FFFF. The RAM is located at address $100000 through address $13FFFF. This address mapping is not obvious from the simplified schematic diagrams because you do not know the details of the circuit block labeled ‘Address Decoder” in Figure 9.4. Summary of Chapter 9 Chapter 9 covered: • The advanced addressing modes of the 68K architecture and their relationship to high- level languages. • An overview of the classes of instructions of the 68K architecture. • Using the TRAP #15 instruction to simulated I/O. • How a program, written in C executes in assembly language and how the C compiler makes use of the advanced addressing modes of the 68K architecture. • How program disassembly is implemented and its relation to the architecture. • The functional blocks of a 68K-based computer system. Chapter 9: Endnotes 1 Alan Clements, 68000 Family Assembly Language, ISBN 0-534-93275-4, PWS Publishing Company, Boston, 1994, p. 704 260 1. Examine the block of assembly language code shown below. a. What is the address of the memory location where the byte, FF, is stored in the indicated instruction? b. Is this code segment relocatable? Why? org $400 start movea.w #$2000,A0 move.w #$0400,D0 move.b #$ff,($84,A0,D0) *Where does ff go? jmp start end $400 Hint: Remember that displacements involve 2’s complement numbers. Also, this instruction may also be written as: move.b #$FF,$84(A0,D0) 2. Examine the following code segment and then answer the question about the operation per- formed by the code segment. You may assume that the stack has been properly initialized. Briefly describe the effect of the highlighted instruction. What value is moved to what destina - tion? 00001000 41F9 00001018 10 START: LEA DATA+2,A0 00001006 2C50 11 MOVEA.L (A0),A6 00001008 203C 00001B00 12 MOVE.L #$00001B00,D0 0000100E 2C00 13 MOVE.L D0,D6 00001010 2D80 6846 14 MOVE.L D0,(70,A6,D6.L) 00001014 60FE 15 STOP_IT: BRA STOP_IT 00001016 00AA0040 C8300000 16 DATA: DC.L $00AA0040,$C8300000 3. Examine the following code segment and then answer the question about the operation per- formed by the code segment. You may assume that the stack has been properly initialized. Briefly describe the effect of the highlighted instruction. What is the value in register D0 after the highlighted instruction has completed? 00000400 4FF84000 START: LEA $4000,SP 00000404 3F3C1CAA MOVE.W #$1CAA,-(SP) 00000408 3F3C8000 MOVE.W #$8000,-(SP) Exercises for Chapter 9 Advanced Assembly Language Programming Concepts 261 0000040C 223C00000010 MOVE.L #16,D1 00000412 203C216E0000 MOVE.L #$216E0000,D0 00000418 E2A0 ASR.L D1,D0 0000041A 383C1000 MOVE.W #$1000,D4 0000041E 2C1F MOVE.L (SP)+,D6 00000420 C086 AND.L D6,D0 00000422 60FE STOP_HERE: BRA STOP_HERE 4. Answer the following questions in a sentence or two. a. Why do local variables go out of scope when a C++ function is exited? b. Give two reasons why variables in high level languages, such as C, must be declared be - fore they can be used? c. The 68000 assembly language instructions, LINK and UNLK would be representative of instructions that are created in order to support a high-level language. Why? 5. The following is a display of 32 bytes of memory that you might see from a “display memory” command in a debugger. What are the 3 instructions shown in this display? 00000400 06 79 55 55 00 00 AA AA 06 B9 AA AA 55 55 00 00 00000410 FF FE 06 40 AA AA 00 00 FF 00 00 00 00 00 00 00 6. Assume that you are trying to write a disassembler program for 68K instructions in memory. Register A6 points to the opcode word of the next instruction that you are trying to disassem - ble. Examine the following algorithm. Describe in words how it works. For this example, you may assume that <A6> = $00001A00 and <$00001A00> = %1101111001100001 shift EQU 12 * Shift 12 bits start LEA jmp_table,A0 *Index into the table CLR.L D0 *Zero it MOVE.W (A6),D0 *We’ll play with it here MOVE.B #shift,D1 *Shift 12 bits to the right LSR.W D1,D0 *Move the bits MULU #6,D0 *Form offset JSR 00(A0,D0) *Jump indirect with index { Other instructions } jmp_table JMP code0000 JMP code0001 JMP code0010 JMP code0011 JMP code0100 JMP code0101 JMP code0110 JMP code0111 JMP code1000 JMP code1001 JMP code1010 [...]... 32-bit number 00C80000h into DX:AX and this number is divided by 0FA0h in the CX register The quotient, 0CCCh, is stored in AX and the remainder, 0C80h, is stored in DX The Destination Index and Source Index registers, DI and SI, are used with data movement and string operations Each register has a specific purpose when indexing the source and destination operands The DI and SI pointers also differ in that... registers, and roughly correspond to the address registers of the 68K The 8086 is strictly organized as two separate and autonomous functional blocks The execution unit, or EU, handles the arithmetic and logical operations on the data and has a 6 byte first-in, first-out (FIFO) instruction queue (4 bytes on the 8088) The segment registers of the BIU are responsible for access instructions and operands from... These are: 1 Register Operand Mode: The operand is located in one of the 8 or 16 bit registers Example of Register Operand Mode instructions would be: MOV MOV INC AX,DX AL,BH AX 2 Immediate Operand Mode: The operand is part of the instruction Examples of the Immediate Operand Mode are: MOV ADD AX,0AC10h AL,0AAh There is no prefix, such as the ‘#’ sign, to indicate that the operand is an immediate The... destination operand; cleared otherwise Bits 12-15: Reserved Segment Registers The four 16-bit segment registers are part of the BIU These registers store the segment (page) value of the address of the memory operand The registers (CS, DS, ES and SS) define the segments of memory that are immediately addressable for code, or instruction fetches (CS), data reads and writes (DS and ES) and stack-based... time the MOVSB instruction executes,the contents of the DI and SI registers are automatically incremented by 1 byte Like it or not, these are powerful and compact instructions The Base Pointer and Stack Pointer (BP and SP) general-purpose registers are used in conjunction with the Stack Segment (SS) register in the BIU and point to the bottom and top of the stack, respectively Since the system stack... Stupid) and keep our eyes on the ultimate objective Since what we are trying to accomplish is a comparative understanding of modern computer architectures we will leave the issues of mastering the art of programming the i86 architecture in assembly language for another time Therefore, we will place out emphasis on learning the addressing modes and instructions of the 8086 as our primary objective and make... locations The following code snippet reads the I/O port at memory location A43Eh and places the data into the AX register MOV DX,0A43Eh IN AX,DX Unlike the 68K, the i86 family handles I/O as a separate memory space with its own set of bus signals and timing The DX register is also used for 16-bit and 32-bit multiplication and division operations As you’ve seen in a previous example, the DX register is... there are some instructions which require a second MOD AUX r/m op-code byte Figure 10.7: Format of the Operand 4 Operand Address: The operand address byte is Address Byte somewhat involved The form of the byte is shown in Figure 10.7 There are three fields, labeled mod, aux and r/m, respectively The operand address byte controls the form of the addressing of the instruction The definition of the Mod Fields... survives to this date and continues to be used as an embedded controller It is hard to estimate its impact, but there must be billions of lines of Z80 code still being used in the world The growth of the PC industry essentially tracked Intel’s continued development and ongoing refinement of the x86 architecture Intel introduced the 80286 as a follow-on CPU and IBM introduced the PC-AT computer which used... I/O from the keyboard and to the screen can easily be implemented with calls to the DOS operating through the Basic Input Output System (BIOS) of your PC This is both a blessing and a curse because in trying to write and execute 8086 programs we will be forced to have to deal with interfacing to the DOS environment itself This means learning some assembler directives that are new and are only applicable . Index registers, DI and SI, are used with data movement and string operations. Each register has a specific purpose when indexing the source and destination operands. The DI and SI pointers also. a qualifying signal for the READ and WRITE operations and is gated through the two lower OR gates in the figure (keep thinking, “ negative logic AND gates” ) and to the ADDRESS DECODER block not have separate READ and WRITE signals, we synthesize the READ signal with the NOT gate and the OR gate. We also use the OR gate and the AS signal to qualify the READ and WRITE signals, with