Hardware and Computer Organization- P3: pdf

Chapter 2 42 value around 10 ohms as the voltage on the gate, relative to the source increases. In real terms, the amount that the voltage on the gate has to vary to cause this dramatic change is exactly the voltage swing from logic 0 to logic 1. As far as our electrical circuit analogy of Figure 2.12 is concerned, this is equivalent to closing the switch as we raise the voltage on the gate. As you can see, the p-channel device behaves in a similar manner as the voltage on the gate becomes more negative then the voltage of the source. In other words, it exhibits complementary behavior. Now, we can finally put this all together and understand CMOS gates in general and Figure 2.13 in particular. Refer back to Figure 2.13. Recall that this is a NOT gate. Let’s see why. Assume that the volt - age on the gate is a logic 0. The n-type transistor is essentially an open switch. The resistance is extremely high (because V GS is nearly zero). However, the complementary device, the p-type device has a very low resistance because the voltage on the gate is much lower then the voltage of the source (–V GS is large). This is the closed switch of Figure 2.12. Thus, at the output of the gate, we see a low resistance (closed switch) to logic 1 and a high resis- tance (open switch to logic 0) and the output of the gate is logic 1. So, when the input to the gate is logic 0, the output from the gate is logic 1. You should be able to analyze the complementary situ - ation for an input of logic level 1. So, we can summarize the behavior of the CMOS NOT gate as follows. When the input is at logic 0, the output “sees” the power supply voltage, or logic 1. When the input is logic 1, the output sees the ground reference voltage, or logic 0. Figure 2.14 illustrates the electrical behavior of MOS transistors. Consider the N-channel device on the right-hand side of the graph. As the voltage on the gate, measured relative to the source (Vgs) becomes higher, or more positive, the electrical resistance between the drain and the source decreases exponentially. Conversely, when Vgs approaches zero, or becomes negative, the resistance between the drain and the source approaches infinity. Essentially, we have an open switch when Vgs is zero or negative, and almost a closed switch when Vgs is a few volts. The behavior of the P-channel device is identical to the N-channel device, except that the relative polarity of the voltages are reversed. Before we leave this topic of the electrical behavior of a CMOS gate, you might be asking yourself, “What about the situation where the voltage on the gate, relative to the source, isn’t all one way or the other, but in the middle?” In other words, what happens when the rising edge or the falling edge of the logic input to the gate is tran - sitioning between the two logic states? According to the graph in Figure 2.14, if the resistance is too high, and it isn’t too low, it is kind of like the temperature of the porridge in “Goldilocks and the Three Bears.” At that point, there is a path for the current to flow from the power supply to ground, so we do waste some energy. Fortunately, the transition between states is fast, so we don’t waste a lot of energy, but nevertheless, there is some power dissipation occurring. Figure 2.15: Power dissipation versus clock rate for various AMD processor families. From www.tomshardware.com 3 . Introduction to Digital Logic 43 Well how bad is it. Recall that a modern processor has tens of millions of CMOS gates and a large fraction of these gates are switching a billion or more times per second. Figure 2.15 should give you some idea of how bad it could be. Notice two things. First, these modern processors really run hot. In fact, they are dissipating as much heat as an ordinary 60–75 watt lightbulb. Also, in each case, as we turn up the clock and make the processors run faster, we see the power dissipation going up as well. You might also be asking another question, “Suppose we turn the clock down until it is really slow, or even stop it, will that have the reverse effect?” Absolutely, by slowing the clock, or shutting down portions of the chip, we can decrease the power requirements accordingly. This is a very important strategy in laptop computers, which have to make their batteries last for the duration of an airplane flight from New York to Los Angeles. This is also the strategy of how many other microprocessors, the kind that are used in embedded applications, can be attached to a collar around the neck of a moose and track the animal’s movements for over two years on no more power than a AAA battery. No wonder CMOS is so popular. OK, we’ve seen a NOT gate. That’s a pretty simple gate. How about something a little more complicated? Let’s do a NAND gate in CMOS. Recall that for a NAND gate, the output is 0 if all the inputs are logic 1. In Figure 2.16, we see that if all of the inputs are at logic 1, then all of the n-channel devices are turned on to the low resistance state. All of the p-channel devices are turned off, so, looking back into the device from the output, we see a low resistance path to the ground reference point (logic 0). Now, if any one of the four inputs A, B, C or D is in logic state 0, then its n-channel MOSFET is in the high-resistance state and its p-channel device is in the low- resistance state. This will effectively block the ground reference point from the output and open a low resistance path to the power supply through the corre - sponding p-channel device. Hopefully, at this point you are getting to be a little more comfortable with your burgeoning hardware skills and insights. Let’s analyze a circuit config - uration. Consider Figure 2.17. This is Figure 2.16: Schematic diagram of a CMOS, 4-input NAND gate. From Fairchild Semiconductor. 4 V CC A B C D X = ABCD A B C D A B C D Figure 2.17: The Shakespeare circuit. OR 2B C = ? NO T Chapter 2 44 often called the “Shakespeare Circuit.” You may feel free to ponder the deeper signifi- cance of the design. Note that I included this example just to prove that all comput - er designers are NOT humorless geeks. Truth Tables The last concept that we’ll discuss in this lesson is the idea of the truth table. You had a brief introduction to the truth table when we discussed the behavior of the tri-state logic gate. However, it is appropri - ate at this point in our analysis to discuss it more formally. The truth table is, as its name implies a tabular form that repre - sents the TRUE/FALSE conditions of a logical gate or system. For each of the logical gates we’ve studied so far, AND, OR, NAND, NOR and XOR, we’ve used a verbal expression to describe the function of the gate. For example, with an AND gate we say, “The output of an AND gate is 1 if and only if both inputs are 1.” This does get the logic across, but we need a better way to manipulate these gates and to design more complex systems. The method that we use is to create a truth table for the logic func - tion. Figure 2.18 shows the truth tables for the five logic gates we’ve studied so far. The NOT gate is trivial so we won’t include it here, and we’ve already seen the truth table for the tri-state gate, so it isn’t included in the figure. The truth table shows us the value of the output variable, C, for every possible value of the input variables, A and B. Since there are two independent input variables, the pair can take on any one of four possible combinations. Referring to Figure 2.18, we see that the output of the AND gate, C, is a logical 1 only when both A and B are 1. All other combinations result in C equal to 0. Likewise, the OR gate has its output equal to 1, if any one of the input variables, or both, is equal to 1. The truth table gives us a concise, graphical way to express the logical functions that we are working with. Suppose that our AND gate has three inputs, or four inputs? What does the truth table look like for that? If we have three independent input variables: A, B, and C, then the truth table would have eight possible combinations, or rows, to represent all of the possible combinations of the input variables. If we had a 3-input AND gate, only one condition out of the eight, ( A = 1, B = 1, C = 1) would product a 1 on the gate’s output. For four input variables, we would need sixteen possible entries in our truth table. Thus, in general, our truth table must have 2 N entries for a sys- tem of N independent input variables. There’s that pesky binary number system again. Figure 2.19 shows the truth tables and logic symbols for a 4-input AND gate and a 3-input OR gate. It is pos - sible to find commercially available AND, NAND, OR and NOR circuits with 5 or more inputs. There are also versions of the NAND circuit that are designed to be able to expand the number of inputs to arbitrarily large values, although there are probably not many reasons to do so. Figure 2.18: Truth table representation for the logical functions AND, OR, NAND, NOR and XOR. A B C 0 1 0 1 0 0 1 1 0 0 0 1 AN D A B C 0 1 0 1 0 0 1 1 0 1 1 1 OR A B C 0 1 0 1 0 0 1 1 1 1 1 0 NAND A B C 0 1 0 1 0 0 1 1 1 0 0 0 NO R A B C 0 1 0 1 0 0 1 1 0 1 1 0 XO R Introduction to Digital Logic 45 a b c d e f g h ? X Y Z Figure 2.20: A digital system being designed. Each of the output variables X, Y, and Z is described in a separate truth table in terms of the combinations of the all possible states of the input variables. The XOR gate is an exception because it is only defined for two inputs. While we could certainly design a circuit with, for example, 5 inputs, A through E and 1 output, f, that has the property that f = 0 if and only if all the inputs are the same, it would not be an XOR gate. It would be an arbitrary digital circuit. Consider the gray box of Figure 2.20. This is an arbitrary digital system that could be the control circuits of an elevator, a home heating and air conditioner, or fire alarm controller. Ultimately, we will be designing the circuit that is inside of the gray box as a circuit built from the logic gates that we’ve just discussed. Whatever it is, it is up to us to specify the logical relationships that each output variable has with the appropriate input variable or variables. Since the gray box has eight input variables, our truth table would have 256 entries to start with. In other words, we would design the system by first specifying the behavior of X, Y, and Z (output conditions) for each possible state of its inputs (a through h). Thus, if we were designing a heating system for a building and one of our inputs is derived from a temperature sensor that is telling us that the tem- perature in the room is lower than the temperature that we set on the thermostat, then it would be logical that this condition should trigger the appropriate output response (ignite burner in furnace). Referring to Figure 2-20, we might start out our design process by creating a spreadsheet with 256 rows in it and 11 columns. We would devote one column for each of the eight input variables and a separate column for each of the three output variables. Next, we would painstakingly fill in the table with all of the 256 possible combinations of the input variables, 00000000 through 11111111. Finally—and here’s where the real engineering starts—for each row, we would have to decide how to assign a value to the output variables. We’ll go into the process of designing these systems in much greater detail in Chapter 3. For now, let’s summa - rize this discussion by recognizing that we’ve used the truth table in two different, but related contexts: A B C D f 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 1 1 0 0 0 0 0 1 0 0 1 0 1 0 0 0 1 1 0 0 1 1 1 0 0 0 0 0 1 0 1 0 0 1 0 0 1 0 1 0 1 1 0 1 0 0 0 1 1 0 1 0 1 1 0 0 1 1 1 0 1 1 1 1 1 0 0 0 0 1 0 0 1 0 1 0 1 1 1 0 1 0 0 1 1 1 0 1 1 0 1 1 1 1 1 1 1 A B C f A 4-input AND B f C D A 3-input OR B f C Figure 2.19: Truth table and gate diagrams for a 4-input AND gate and a 3-input OR gate. Chapter 2 46 1. The truth table could be used as a tabular format for describing the logical behavior of one of the standard gates (AND, OR, NAND, NOR, XOR or TS). 2. We can specify an arbitrarily complex digital system by using the truth table to describe how we want the digital system to behave when we finally create it. Summary of Chapter 2 Here’s what we’ve accomplished: • Learned the basic logic gates, AND, OR and NOT and saw how more complex gates, such as NAND, NOR and XOR could be derived from them, and • Learned that logic values that are dynamic, or change with time, may be represented on a graph of logic level or voltage versus time. This is called a waveform. • Learned how CMOS logic gates are derived from electronic switching elements, MOSFET transistors. • Learned how to describe the logical behavior of a gate or digital circuit as a truth table. Chapter 2: Endnotes 1 http://www.dnaftb.org/dnaftb/20/concept/index.html. 2 J. Watson, An Introduction to Field Effect Transistors, published by Siliconix, Inc., Santa Clara, CA, 1970, p. 91. 3 http://www.tomshardware.com. 4 Fairchild Semiconductor Corp., Application Note 77, CMOS, The Ideal Logic Family, January, 1983. 47 1. Consider the simple AND circuit of Figure 1.14 and the OR circuit of Figure 2.5. Change the sense of the logic so that an open switch (no current flowing) is TRUE and a closed switch is FALSE. Also, change the sense of the light bulb so that the output is TRUE if the light is not shining and FALSE if it is turned on. Under these new conditions of negative logic, what logic function does each circuit represent? 2. Draw the circuit for a 2-input AND gate using CMOS transistors. Hint: use the diagram in Figure 2.16 as a starting point. 3. Construct the truth table for the following logical equations: a. F = a * b * c + b * a b. F = a * b + a * c + b * c 4. What is the effect on the signal between points A and B when the voltage at point X is raised to logic level 1? 5. Construct a truth table for a parity detection circuit. The circuit takes as its input 4 variables, a through d, and has one output, X. Input d is a control input. If d = 1, then the circuit measures odd parity; if d = 0, the circuit measures even parity. Parity is measured on inputs a, b and c. Parity is odd if there are an odd number of 1’s and parity is even if there is an even number of 1’s. For example, if d = 1 and (a, b, c) = (1, 0, 0), then X = 1 because the parity is odd. 6. Draw the truth table that corresponds to the logic gate circuit shown, right: Exercises for Chapter 2 B A X B NOR AND AN D OR XOR A B C X NOT Chapter 2 48 7. The gate circuit for the XOR function, equation a ⊕ b = X, is shown in Figure 2.8. Given that you can also express the XOR function as: a ⊕ b = ~ [~ (a * b) * ~(a * b)]. Redesign this circuit using only NAND gates. 8. Consider the circuit of Figure 2.3. Suppose that we replace the AND gate shown in the figure with (a) an OR gate and (b) and XOR gate. What would the output waveform look like for the case where input A = 0 and the case where input A = 1? 49 C H A P T E R 3 Introduction to Asynchronous Logic Objectives  Use the principles of Boolean algebra to simplify and manipulate logical equations and turn them into logical gate designs;  Create truth tables to describe the behavior of a digital system;  Use the Karnaugh map to simplify your logical designs;  Describe the physical attribute of logic signals, such as rise time, fall time and pulse width;  Express system clock signals in terms of frequency and period;  Manipulate time and frequency in terms of commonly used engineering units such as Kilo, Mega, Giga, milli, micro, and nano;  Understand the logical operation of the Type 'D' flip-flop (D-FF);  Describe how binary counters, frequency dividers, shift registers and storage registers can be built from D-FF's. Introduction Before we immerse ourselves in the rigors of logical analysis and design, it’s fair to step back, take a breath and reflect on where all of this came from. We’ve may have been given the erroneous impression that logic sprang forth from Silicon Valley with the invention of the transistor switch. We generally trace the birth of modern logical analysis to the Greek philosopher, Aristotle, who was born in 384 B.C., is generally acknowledged to be the father of modern logical thought. Thus, if we were to be com - pletely accurate (and perhaps a bit generous), we might say that Aristotle is the father of the modern digital computer. However, if we were to look at the mathematics of the gates we’ve just been introduced to, we may find it difficult to make the leap to Aristolean Logic. However, one simple example might give us a hint. The basis of Aristotle’s logic revolves around the notion of deduction. You may be more familiar with this concept from watching old Sherlock Holmes movies, but Sherlock didn’t invent the idea of deductive reasoning, Aristotle did. Aristotle proposes that a deductive argument has “things supposed,” or a premise of the argument, and what “results of necessity” is the conclusion. 1 Figure 3.1: Aristotle. Chapter 3 50 One often cited example is: 1. Humans are mortal. 2. Greeks are human. 3. Therefore, Greeks are mortal. We can convert this to a slightly different format: 1. Let A be the state of human mortality. It may be either TRUE or FALSE that human beings are mortal. 2. Let B be the state of Greeks. It may be TRUE or FALSE that natives of Greece are human beings. 3. Therefore, the only TRUE condition is that if A is TRUE AND B is TRUE then Greeks are mortal. Or, C (Greek mortality) = A * B. We can trace our ability to manipulate logical expressions to the English mathematician and logician, George Boole (1816–1864). “In 1854, Boole published an investigation into the Laws of Thought, on Which are founded the Mathematical Theories of Logic and Probabilities. Boole approached logic in a new way reducing it to a simple algebra, incorporating logic into mathematics. He pointed out the analogy between algebraic symbols and those that represent logical forms. It began the algebra of logic called Boolean algebra, which now finds application in computer construction, switching circuits etc.” 2 Boolean algebra provides us with the toolset that we need to design complex logic systems with the certainty that the circuit will perform exactly as we intended it that it should. Also, as you’ll soon see, the process of designing a digital circuit often leads to designs that are quite redundant and in need of simplification. Boolean algebra gives us the tools we need to simplify the circuit design and be confident that it will work as designed with the absolute minimum of hardware. As engineers, this is exactly the kind of analytical tool we need because we are most often tasked with producing the most cost-effective design possible. In working with digital computing systems, there are two distinctly different binary systems with which we’ll need to become familiar. Earlier in this course, we were introduced to the binary num - ber system. This is convenient, because we need for our computer to be able to operate on numbers larger than one bit in width. The other component of this is the operation of the hardware as digital system. In order to understand how the numbers are manipulated, we need to learn the principles of binary logical algebra, or Boolean algebra. Therefore, the first step in the process is to state some of the laws of Boolean algebra. In most cases, the laws should be obvious to you. In other cases, you might have to scratch your head a bit until you see that we’re dealing with logical operations on variables that can only have two possible values, and not the addition and multiplication of variables that can take on a continuum of values. Also, be aware that there is no fixed convention for representing a NOT condition, and several variant representations may apply. This is partially historical because the basic ASCII set Figure 3.2: George Boole. Introduction to Asynchronous Logic 51 of printable characters did not give us a simple way to represent a NOT variable, that is a variable with a line over it, as shown in Chapter 2, Figure 2.4. Thus, you may see several different repre - sentations of the NOT condition. For example, /A , ~A , *A and A* are all commonly used ways of representing the condition, NOT A. I will avoid using the *A and A* notations because it is too easy to confuse this with the AND symbol. However, I will occasionally use ~A and /A inter - changeably in the text for the NOT A condition if it makes the equation easier to understand. Most figures will continue to use the bar notation for the NOT condition. Sorry for the confusion. Laws of Boolean Algebra Laws of Complementation • First law of complementation: If A = 0 then A = 1 and if A = 1 then A = 0 • Second law of complementation: A * A = 0 • Third law of complementation: A + A = 1 • Law of double complementation: /(A) = //A = A Laws of Commutation • Commutation law for AND: A * B = B * A • Commutation law for OR: A + B = B + A Associative Laws • Associative law for AND: A * (B * C ) = C * ( A * B ) • Associative law for OR: A + (B + C ) = C + ( A + B ) The associative laws enable us to combine three or more variables. The law tells us that we may combine the variables in any order without changing the result of the combinations. As we’ve seen in Chapter 2, this is the law that allows us, for example, to combine two, 2-input OR gates to obtain the logical equivalent of a single 3-input OR gate. It should be noted that when we say the “logical equivalent” we are neglecting any electrical differences. As we have seen, the timing behavior of a logic gate must be taken into account in any real system. Distributive Laws • First distributive law: A * (B + C ) = ( A * B ) + ( A* C ) • Second distributive law: A + (B * C ) = ( A + B ) * ( A + C ) The distributive laws look a lot like the algebraic operations of factoring and multiplying out. Laws of Tautology • First law of tautology: A * A = A If A = 1 then A * A = 1. If A = 0, then A * A = 0. So the expression A * A reduced to A. • Second law of tautology: A + A = A If A = 1, then 1 + 1 = 1 , If A = 0, then 0 + 0 = 0. Again, the expression simply reduced to A. [...]... because they show the relationship between the AND and OR functions and the concepts of positive and negative logic Also, DeMorgan’s theorems show us that any logic function using AND gates and inverters (NOT gates) may be duplicated using OR gates and inverters Also notice that the left side of both of the above equations are just the compound logic functions NAND and NOR, respectively Before we move on,... first AND gate does not require variable A as an input, variable B and C are unchanged, so we also get x = 1 for this situation 3 Term 3: A = 0, B = 1, C = 0 The first AND gate now gives us a ‘0’ because the complement of B = 1 is B = 0 Thus, 0 AND 1 = 0 The second AND gate has A and B as its inputs Since this condition has A = 0 and B = 0 as its inputs, it is also ‘0’ The third AND gate has A = 0 and. .. the AND gate and the aggregation of the combinatorial terms using the OR gate Notice that we needed three, 2-input AND gates and one, 3-input OR gate to implement the design If we had a more complex problem we might choose to use AND and OR gates with more available inputs or use several levels of gates with fewer inputs Thus, we could create an equivalent 7-input AND gate from three, 3-input AND gates... the electrical circuit that is an AND gate would still be an AND gate if we swapped 1 and 0 in the electrical sense It wouldn’t It would be an OR gate Likewise, the OR gate would become an AND gate if we swapped 1 and 0 so that the lower voltage became a 1 and the higher voltage became a 0 You can verify this for yourself by reviewing the truth tables for the AND gate and OR gate in Lesson 1 You can... inputs, A, B, C and D and 1 output, x Assume that A and B are the control inputs, C and D are arbitrary input variables Fill in the truth table for x so that the design will implement different logic functions depending upon the state of the control inputs, A and B The functions are as shown in the following table: A 0 0 1 1 B 0 1 0 1 Output logic function of C and D (x) NAND XOR NOR AND 68 Introduction... Figure 4.1 The circuit has two inputs, A and B and two outputs, Q and Q As you’ll soon see, these outputs are always the complement of each other, but for now, we’ll just call them Q and Q According to Figure 4.1, inputs A and B and output Q are all at logic level’1’ and output Q is 71 1 1 0 A B 0 0 1 1 0 0 A Q 0 1 0 1 Q Q Figure 4.1: The Set/Reset (RS) Flip-Flop The NAND gate design of the upper circuit... terms 1 Term 1: A = 0, B = 0, C = 0 Here the NOT gates for the variables B and C invert the inputs and feed the values B = 1 and C = 1 to the first AND gate Since both inputs are ‘1’, the output of this AND gate is 1 The output of this AND gate is the input to the OR gate Since one of the inputs is ‘1’, the output is also ‘1’ and x = 1, just as required by the truth table 2 Term 2: A = 1, B = 0, C =... take the truth table for the AND gate and swap all of the 1’s with 0’s and all of the 0’s with 1’s, you end up with the truth table for the OR gate (in negative logic) Try it again for the OR gate and you’ll see that you now have an AND gate in negative logic An important point to keep in mind is that the same electronic circuit will give us the logical behavior of an AND gate if we adopt the convention... these pulses to have infinitely fast transitions from LOW to HIGH and HIGH to LOW It doesn’t hurt anything to make this assumption and it makes our diagrams easier to analyze and understand We refer to this continuous stream of pulses, such as the waveform shown in Figure 3.15, as a clock The clock is not the same as the clock in your computer that gives you the time of day The clock that we are concerned... Engineers, but we will try to understand what the clock is doing in our system Imagine that you are looking at the pendulum of an impressive old grandfather’s clock If you could start a stopwatch at the point where the pendulum just stops at one end of its travel and stop the watch when it travels to the side and returns, you would measure the period of the pendulum The grandfather’s clock uses the fact . studied so far, AND, OR, NAND, NOR and XOR, we’ve used a verbal expression to describe the function of the gate. For example, with an AND gate we say, “The output of an AND gate is 1 if and only if. Figure 2.19 shows the truth tables and logic symbols for a 4-input AND gate and a 3-input OR gate. It is pos - sible to find commercially available AND, NAND, OR and NOR circuits with 5 or more inputs accomplished: • Learned the basic logic gates, AND, OR and NOT and saw how more complex gates, such as NAND, NOR and XOR could be derived from them, and • Learned that logic values that are dynamic,