Sequential Verulog Topics part 13 docx

14.7.1 Design Specification A simple digital circuit is to be designed for the coin acceptor of an electronic newspaper vending machine.. This digital circuit can be designed by using t

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14.7 Example of Sequential Circuit Synthesis

In Section 14.4.2, An Example of RTL-to-Gates, we synthesized a combinational circuit Let us now consider an example of sequential circuit synthesis

Specifically, we will design finite state machines

14.7.1 Design Specification

A simple digital circuit is to be designed for the coin acceptor of an electronic newspaper vending machine

• Assume that the newspaper cost 15 cents (Wow! Who gives that kind of a price any more? Well, let us assume that it is a special student edition!!)

• The coin acceptor takes only nickels and dimes

• Exact change must be provided The acceptor does not return extra money

• Valid combinations including order of coins are one nickel and one dime, three nickels, or one dime and one nickel Two dimes are valid, but the acceptor does not return money

This digital circuit can be designed by using the finite state machine approach

14.7.2 Circuit Requirements

We must set some requirements for the digital circuit

• When each coin is inserted, a 2-bit signal coin[1:0] is sent to the digital circuit The signal is asserted at the next negative edge of a global clock signal and stays up for exactly 1 clock cycle

• The output of the digital circuit is a single bit Each time the total amount inserted is 15 cents or more, an output signal newspaper goes high for

exactly one clock cycle and the vending machine door is released

• A reset signal can be used to reset the finite state machine We assume synchronous reset

14.7.3 Finite State Machine (FSM)

We can represent the functionality of the digital circuit with a finite state machine

• input: 2-bit, coin[1:0]—no coin x0= 2'b00, nickel x5 = 2'b01, dime x10 = 2'b10

• output: 1-bit, newspaper—release door when newspaper = 1'b1

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• states: 4 states—s0 = 0 cents; s5 = 5 cents; s10 = 10 cents; s15 = 15 cents

The bubble diagram for the finite state machine is shown in Figure 14-10 Each arc

in the FSM is labeled with a label <input>/<output> where input is 2-bit and output

is 1-bit For example, x5/0 means transition to the state pointed to by the arc, when input is x5 (2'b01), and set the output to 0

Figure 14-10 Finite State Machine for Newspaper Vending Machine

14.7.4 Verilog Description

The Verilog RTL description for the finite state machine is shown in Example

14-6

Example 14-6 RTL Description for Newspaper Vending Machine FSM

//Design the newspaper vending machine coin acceptor

//using a FSM approach

module vend( coin, clock, reset, newspaper);

//Input output port declarations

input [1:0] coin;

input clock;

input reset;

output newspaper;

wire newspaper;

//internal FSM state declarations

wire [1:0] NEXT_STATE;

reg [1:0] PRES_STATE;

//state encodings

parameter s0 = 2'b00;

//Combinational logic

function [2:0] fsm;

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input [1:0] fsm_coin;

input [1:0] fsm_PRES_STATE;

reg fsm_newspaper;

reg [1:0] fsm_NEXT_STATE;

begin

case (fsm_PRES_STATE) s0: //state = s0

begin

if (fsm_coin == 2'b10)

begin

fsm_newspaper = 1'b0;

fsm_NEXT_STATE = s10; end

else if (fsm_coin == 2'b01) begin

else

begin

end

s5: //state = s5

begin

else if (fsm_coin == 2'b01) begin

else

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begin

fsm_NEXT_STATE = s5;

end

s10: //state = s10

begin

end

else if (fsm_coin == 2'b01)

begin

end

else

begin

end

s15: //state = s15

begin

end

endcase

fsm = {fsm_newspaper, fsm_NEXT_STATE};

end

endfunction

//Reevaluate combinational logic each time a coin

//is put or the present state changes

assign {newspaper, NEXT_STATE} = fsm(coin, PRES_STATE);

//clock the state flip-flops

//use synchronous reset

always @(posedge clock)

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begin

if (reset == 1'b1)

PRES_STATE <= s0;

else

PRES_STATE <= NEXT_STATE;

end

endmodule

14.7.5 Technology Library

We defined abc_100 technology in Section 14.4.1, RTL to Gates We will use abc_100 as the target technology library abc_100 contains the following library cells:

//Library cells for abc_100 technology

VNAND//2-input nand gate

VAND//2-input and gate

VNOR//2-input nor gate

VOR//2-input or gate

VNOT//not gate

VBUF//buffer

NDFF//Negative edge triggered D flip-flop

PDFF//Positive edge triggered D flip-flop

14.7.6 Design Constraints

Timing critical is the only design constraint we used in this design Typically, design constraints are more elaborate

14.7.7 Logic Synthesis

We synthesize the RTL description by using the specified design constraints and technology library and obtain the optimized gate-level netlist

14.7.8 Optimized Gate-Level Netlist

We use logic synthesis to map the RTL description to the abc_100 technology The optimized gate-level netlist produced is shown in Example 14-7

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Example 14-7 Optimized Gate-Level Netlist for Newspaper Vending Machine FSM

module vend ( coin, clock, reset, newspaper );

input [1:0] coin;

input clock, reset;

output newspaper;

wire \PRES_STATE[1] , n289, n300, n301, n302, \PRES_STATE243[1] , n303, n304, \PRES_STATE[0] , n290, n291, n292, n293, n294,

n295, n296, n297, n298, n299, \PRES_STATE243[0] ;

PDFF \PRES_STATE_reg[1] ( clk(clock), d(\PRES_STATE243[1] ),

clrbar( 1'b1), prebar(1'b1), q(\PRES_STATE[1] ) );

PDFF \PRES_STATE_reg[0] ( clk(clock), d(\PRES_STATE243[0] ),

clrbar( 1'b1), prebar(1'b1), q(\PRES_STATE[0] ) );

VOR U119 ( in0(n292), in1(n295), out(n302) );

VAND U118 ( in0(\PRES_STATE[0] ), in1(\PRES_STATE[1] ),

out(newspaper));

VNAND U117 ( in0(n300), in1(n301), out(n291) );

VNOR U116 ( in0(n298), in1(coin[0]), out(n299) );

VNOR U115 ( in0(reset), in1(newspaper), out(n289) );

VNOT U128 ( in(\PRES_STATE[1] ), out(n298) );

VAND U114 ( in0(n297), in1(n298), out(n296) );

VNOT U127 ( in(\PRES_STATE[0] ), out(n295) );

VAND U113 ( in0(n295), in1(n292), out(n294) );

VNOT U126 ( in(coin[1]), out(n293) );

VNAND U112 ( in0(coin[0]), in1(n293), out(n292) );

VNOR U111 ( in0(n291), in1(reset), out(\PRES_STATE243[0] ) );

VNAND U124 ( in0(\PRES_STATE[0] ), in1(n304), out(n301) );

VAND U110 ( in0(n289), in1(n290), out(\PRES_STATE243[1] ) );

VNAND U122 ( in0(n299), in1(coin[1]), out(n303) );

VOR U120 ( in0(n293), in1(coin[0]), out(n297) );

endmodule

The schematic diagram for the gate-level netlist is shown in Figure 14-11

Figure 14-11 Gate-Level Schematic for the Vending Machine

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14.7.9 Verification

Stimulus is applied to the original RTL description to test all possible

combinations of coins The same stimulus is applied to test the optimized gate-level netlist Stimulus applied to both the RTL and gate-gate-level netlist is shown in Example 14-8

Example 14-8 Stimulus for Newspaper Vending Machine FSM

module stimulus;

reg clock;

reg [1:0] coin;

reg reset;

wire newspaper;

//instantiate the vending state machine

vend vendY (coin, clock, reset, newspaper);

//Display the output

initial

begin

$display("\t\tTime Reset Newspaper\n");

$monitor("%d %d %d", $time, reset, newspaper);

end

//Apply stimulus to the vending machine

initial

begin

clock = 0;

coin = 0;

reset = 1;

#50 reset = 0;

@(negedge clock); //wait until negative edge of clock

//Put 3 nickels to get newspaper

#80 coin = 1; #40 coin = 0;

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//Put one nickel and then one dime to get newspaper

#180 coin = 1; #40 coin = 0;

#80 coin = 2; #40 coin = 0;

//Put two dimes; machine does not return a nickel to get newspaper

#180 coin = 2; #40 coin = 0;

#80 coin = 2; #40 coin = 0;

//Put one dime and then one nickel to get newspaper

#180 coin = 2; #40 coin = 0;

#80 coin = 1; #40 coin = 0;

#80 $finish;

end

//setup clock; cycle time = 40 units

always

begin

#20 clock = ~clock;

end

endmodule

The output from the simulation of RTL and the gate-level netlist is compared In our case, Example 14-9, the output is identical Thus, the gate-level netlist is verified

Example 14-9 Output of Newspaper Vending Machine FSM

Time Reset Newspaper

0 1 x

20 1 0

50 0 0

420 0 1

460 0 0

780 0 1

820 0 0

1100 0 1

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1140 0 0

1460 0 1

1500 0 0

The gate-level netlist is sent to ABC Inc., which does the layout, checks that the layout meets the timing requirements, and then fabricates the IC chip

14.8 Summary

In this chapter, we discussed the following aspects of logic synthesis with Verilog HDL:

• Logic synthesis is the process of converting a high-level description of the design into an optimized, gate-level representation, using the cells in the technology library

• Computer-aided logic synthesis tools have greatly reduced the design cycle time and have improved productivity They allow designers to write

independent, high-level descriptions and produce technology-dependent, optimized, gate-level netlists Both combinational and sequential RTL descriptions can be synthesized

• Logic synthesis tools accept high-level descriptions at the register transfer level (RTL) Thus, not all Verilog constructs are acceptable to a logic

synthesis tool We discussed the acceptable Verilog constructs and operators and their interpretation in terms of digital circuit elements

• A logic synthesis tool accepts an RTL description, design constraints, and technology library and produces an optimized gate-level netlist Translation, logic optimization, and technology mapping are the internal processes in a logic synthesis tool and are normally invisible to the user

• Functional verification of the optimized gate-level netlist is done by

applying the same stimulus to the RTL description and the gate-level netlist and comparing the output Timing is verified with timing simulation or static timing verification

• Proper Verilog coding techniques must be used to write efficient RTL

descriptions, and various design trade-offs must be evaluated Guidelines for writing efficient RTL descriptions were discussed

• Design partitioning is an important technique used to break the design into smaller blocks Smaller blocks reduce the complexity of optimization for the logic synthesis tool

• Accurate specification of design constraints is an important part of logic synthesis

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High-level synthesis tools allow the designer to write designs at an algorithmic level However, high-level synthesis is still an emerging design paradigm, and RTL remains the popular high-level description method for logic synthesis tools.

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