Vietnamese name hướng dẫn thực hành thiết kế vi mạch dùng verilog trên modelsim

LAB 1: HƯỚNG DẪN THỰC HÀNH THIẾT KẾ VI MẠCH DÙNG VERILOG TRÊN MODELSIM Pictures Figure 2: Schematic Diagram of Halfˆ Adder CITCUIE...-- - - 2 2 **ErEsEsEsEEEEErerrrrrrrkrkrererrkrkrke

VIETNAM NATIONLA UNIVERSITY, HO CHI MINH CITY UNIVERSITY OF INFORMATION TECHNOLOGY FACULTY OF COMPUTER ENGINEERING

-000 -

⁄

DIGITAL SYSTEM DESIGN WITH HDL

CE213.012.MTCL.2 LAB REPORT 1 VIETNAMESE NAME : HUONG DAN THUC HANH THIET KE VI MACH DUNG

VERILOG TREN MODELSIM

ENGLISH NAME: GUIDE TO PRACTICE DESIGNING CIRCUITS USING

VERILOG ON MODELSIM STUDENT NAME: Truong Duy Duc STUDENT ID: 21521970 Lecturer: Ta Tri Đức

Contents

IS 3

IVAiri r9 doi 0c n6 3

2 ADDER 3 2.1 HALF-ADDER 0 LH HH Họ nh nọ ĐH 3 2.2 ¡6n 00a e 3

3 HDL Code 6 Eins.cccciiiiiiddd.': 6

E7» `mñ mm 6

E2 9¬ .Ề 7

E5 .Ầ 8

4 Modeling 9 ch 0c on cố 9

“NO in na 9

5 Schematic 9 km» -:addid 9

5.2 CLAM 10

=9 ¬ ỐỐ 10

5.3 Difference between CLA _3B and CLA _ÌM s1 nh HH HH HH Hà Hà 10 6 Simulation and Evaluation 11 Su 0 11

;IU C1 11

z2 ồn .Ố 11 2/22/20) 10109) n 12

LAB 1: HƯỚNG DẪN THỰC HÀNH THIẾT KẾ VI MẠCH DÙNG VERILOG TRÊN MODELSIM

Pictures

Figure 2: Schematic Diagram of Halfˆ Adder CITCUIE - - 2 2 **ErEsEsEsEEEEErerrrrrrrkrkrererrkrkrke 4 Figure 3:True table of Full- Adder NỚNN"" 5 Figure 4: Schematic Diagram of Full- Adder CITGUIE - 5-5 - 5 St sESErErxrxrsrrsrsrsrxkrerererererke 5 Figure Š: Schematic of CLUA-3B CITCUIE - 5-5-5 2-2 3xx kExEnrxEYExExExHxTTTTT TT Hành kh rkrkp 9 Figure 6: Schematic of CLA-M GITCUIE 5-5-5 + +22 xxx TH TRE TT TT Hành Hành rhrkt 10 i00: P2913 2019 2 e Figure 8: waveform form (QU4TfUS cà hàn nàn HH HT TT HT TH TH Figure 9: waveform form MoeÏsim - 5-5-5 5-22 3xx kEErEExExEkEkETTEEEEETke ri krkrkrkeekrkrkrke

Figure 10: Transcipt with 100% pass

1 Content of Lab

Learn the basics of Verilog and the "Modelsim" practice tool Learn basic operations on modelsim

1.1 ModelSim

ModelSin is a widely-used simulation and verification tool for digital circuit design, supporting VHDL and Verilog Its features include simulation capabilities, a waveform viewer for result analysis, support for design hierarchy, advanced debugging tools, and testbench development for comprehensive design testing With integration options for other EDA tools, it facilitates a streamlined design process Available in different editions, it serves both educational and professional purposes, aiding in the development and validation of complex digital systems

1.2 Hardware Description Language

Hardware Description Language (HDL) is a specialized programming language used for designing electronic circuits and systems It allows engineers to describe the behavior and structure of digital hardware, enabling the simulation and synthesis of complex designs VHDL and Verilog are the two main types of HDL widely used in the industry HDLs provide a way to model both the behavior and structure of digital systems, from high-level architectural design to low-level circuit representation They are essential for designing and implementing integrated circuits, FPGAs, and ASICs HDLs play a crucial role in the development of modern electronic systems, providing a standardized and efficient method for describing and realizing complex hardware designs

2 ADDER

Adder circuits are useful for performing arithmetic operations in computers, especially in the arithmetic logic unit (ALU) There are two common types of adder circuits: half adders and full adders A half adder can only add two single bits and output

a sum and a carry A full adder can add three bits, including the carry from the previous operation, and output a new sum and carry By connecting multiple full adders together,

we can create a wide adder to add numbers with multiple bits

2.1 HALF-ADDER

Half adder is the simplest of all adder circuits Half adder is a combinational arithmetic circuit that adds two numbers and produces a sum bit (s) and carry bit (c) both

as output The addition of 2 bits is done using a combination circuit called a Half adder The input variables are augend and addend bits and output variables are sum & carry bits

A and B are the two input bits

LAB 1: HƯỚNG DẪN THỰC HÀNH THIẾT KẾ VI MẠCH DÙNG VERILOG TRÊN MODELSIM

True table:

Inputs Outputs

A B Sum Carry

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1 Figure I: True table of Half-Adder Schematic Diagram of Half-Adder Circuit

A

B

SUM

Carry

Figure 2: Schematic Diagram of Half-Adder Circuit

2.2 FULL-ADDER

The full adder is a little more difficult to implement than a half adder The main difference between a half adder and a full adder is that the full-adder has three inputs and two outputs The two inputs are A and B, and the third input is a carry input CIN The output carry is designated as COUT, and the normal output is designated as S

True table:

A B CIN COUT S

000 0 0

0 0 1 0 1

010 0 1

0 1 1 1 0

100 0 1

1 0 1 1 0

1 10 1 0

1 1 1 1 1 Figure 3:True table of Full-Adder Schematic Diagram of Full-Adder Circuit :

B——

Figure 4: Schematic Diagram of Full-Adder Circuit

LAB 1: HƯỚNG DẪN THỰC HÀNH THIẾT KẾ VI MẠCH DÙNG VERILOG TRÊN MODELSIM

3 HDL Code

3.1 CLA_3B

module CLA_3b(A,B,Cin,S);

input [2:0] A,B;

input Cin;

wire Cout;

output [3:0] S;

wire [2:0] G,P;

wire [1:0] C;

wire [5:0] W;

and a0(G[0],A[0].BỊ0]):

xor x0(P|0],A[0],B[0]):

and al(G[1].A[1].BỊ1):

xor xI(P[1],A[1],BỊ[1]):

and a2(G[2],A[2],BI2]);

xor x2(P[2],A[2],BI2]):

and pc0(W[0I, P[0],Cin);

or 00(C[0], W[0],G[0]);

and pel(W[1], W[0],P[1]);

and pe2(W[2],G[0],P[1]);

or ol (C[1],G[1], W[1], W[2));

and pe3(W[3],W[1],P[2));

and pc4(W[4], W[2],P[2]);

and pe5(W[5],G[1],P[2]);

or 02(Cout,G[2],W[3],W[4], WI5]);

xor s0(S[0],Cin,P[0]);

xor sl(S[1],C[0],P[1]);

xor s2(S[2],C[1],P[2]);

and s4(S[3],Cout, 1);

endmodule

3.2 CLAM_M

module CLA_M(A,B,Cin,S);

input [2:0] A,B;

input Cin;

output [3:0] S;

assign S=(A+B+Cin);

endmodule

3.3 TESTBENCH

‘timescale Ins/100ps

module CLA _testbenchQ);

reg[2:0] A,B;

reg Cin;

wire [3:0] S,mS;

initial

begin

#640 $stop;

end

initial

begin

Gen();

end

top inst0(.A(A),.B(B),.Cin(Cin),.S(S),.mS(mS));

task Gen;

begin

A<=0;

B<=0;

Cin<=0;

forever begin

#5 A<=(A+1);

if(A==3'b111) begin

#0 B<=(B+1);

if(B==3'b111) begin

#0 Cin<=(Cin+1);

end

end

if((S==mS))

#0 $display("Expected result: %d Simulation result: %d

>PASS",S,mS);

else

#0 $display("Expected result: %d Simulation result: %d

>FAIL",S,mS);

end

end

endtask

endmodule

LAB 1: HƯỚNG DẪN THỰC HÀNH THIẾT KẾ VI MẠCH DÙNG VERILOG TRÊN MODELSIM 3.4 TOP

module top(A,B,Cin,S,mS);

input [2:0] A,B;

input Cin;

output [3:0] mS,S;

CLA _M inst0(.A(A),.B(B),.Cin(Cin),.S(S));

CLA_3b inst1l(.A(A),.B(B),.Cin(Cin),.S(mS));

endmodule

4 Modeling

4.1 Structural Model

The structural model describes a system using basic components such as digital gates and adders In structural modeling, the programmer or the designer thinks about the circuit as a box or a module It is encapsulated from the outer environment In other words, it communicates with the outer environment through inputs and outputs

4.2 Behavioral Model

The structural model describes a system using basic components such as digital gates and adders In structural modeling, the programmer or the designer thinks about the circuit as a box or a module It is encapsulated from the outer environment In other words, it communicates with the outer environment through inputs and outputs

5 Schematic

5.1 CLA_3B

Al2.0IBB—T— Ê= = L3 pet et o1 s2 >

» o0 A

ad 2 1 J) „

—T | psi] |

a2

Cw wa ) >

Figure 5: Schematic of CLA-3B circuit

LAB 1: HƯỚNG DẪN THỰC HÀNH THIẾT KẾ VI MẠCH DÙNG VERILOG TRÊN MODELSIM

5.2 CLA_M

A[2 0]

B[2 0]

Cin

Figure 6: Schematic of CLA-M circuit

5.3 TOP

CLA 3b:inst1

Cin >

CLA M:inst0

Figure 7: Schematic of TOP

5.3 Difference between CLA_3B and CLA_M

Because CLA 3B 1s a structural model while CLA_M 1s a behavioral model, we will notice that the schematic of CLA_ 3B is intricately constructed using gates, clearly illustrating the internal circuitry and how it functions

On the other hand, CLA_M, as a behavioral model, highlights the circuit's functionality and performance under various conditions, without delving into its internal structure It provides valuable insights into the system's response to inputs, aiding in understanding its operational behavior

10

6 Simulation and Evaluation

6.1 Simulation

6.1.1 Waveform

& >A UO 0X3X5XIX 3 X6X 3 X5Xð6X3X2Xö6X0X7X5X t4

%>B U4 4X6X2X3X5X4Xð6X0X2X7X4X 6 X2X7X3X6X 4 X5)

%- Cin B0

# >S U4 4X9X7X4X8X7X9ðX6X5X10X8XI2XI3X6X 10 X7 X12XIOXG6)

#9 >mS U4 4X9X7X4X85X7X9ð9XöX5X1XBXI2XGX6X 10 X7X12XI0X6)

Figure 8: waveform from Quartus

Figure 9: waveform from Modelsim

The inputs are A, B, and CIN Here, A and B are 2-bit numbers, and CIN is the carry bit (1 bit) The circuit's function is to compute A+B+CIN, producing a 3-bit result C-The outputs are S and mS, which respectively represent the results of CLA_3b and CLA_M

As observed, both the results of CLA_3b and CLA_M are identical and correct according to the principles of the addition circuit

6.1.2 Transcipt

Expected result: 11 Simulation result: 11 >PASS Expected result: 6 Simulation result: 6 >PASS Expected result: 7 Simulation result: 7 >PASS Expected result: 8 Simulation result: §& >PASS Expected result: 9 Simulation result: § >PASS

Expected result: 10 Simulation result: 10 >PASS Expected result: -Simulation result: 11 >PASS Expected result: 12 Simulation result: 12 >PASS Expected result: -Simulation result: 13 >PASS

~ -

- Gà

Expected result: 7 Simulation result: 7 >PASS Expected result: 8 Simulation result: 89 >PASS Expected result: 9 Simulation result: 9 >PASS Expected result: 10 Simulation result: 10 >PASS Expected result: 12 Simulation result: 12 >PASS Expected result: 14 Simulation result: 14 >PASS Expected result: 8 Simulation result: 8 >PASS Expected result: 9% Simulation result: %9 >PASS Expected result: 10 Simulation result: 10 >PASS Expected result: 12 Simulation result: 12 >PASS Expected result: 14 Simulation result: 14 >PASS

ee

Figure 10: Transcipt with 100% pass

11

LAB 1: HƯỚNG DẪN THỰC HÀNH THIẾT KẾ VI MẠCH DÙNG VERILOG TRÊN MODELSIM

6.2 EVALUATION

Correct completion of lab requirements, circuits and results as predicted

12