Khóa luận tốt nghiệp: Ứng dụng scan compress để giảm số lượng scan IO và test time

VIETNAM NATIONAL UNIVERSITY HO CHI MINH CITYUNIVERSITY OF INFORMATION TECHNOLOGY FACULTY OF COMPUTER ENGINEERING BUI XUAN VIET ANH LE TRONG TRUNG CAPSTONE PROJECTUNG DUNG SCAN COMPRESS D

VIETNAM NATIONAL UNIVERSITY HO CHI MINH CITY

UNIVERSITY OF INFORMATION TECHNOLOGY

FACULTY OF COMPUTER ENGINEERING

BUI XUAN VIET ANH

LE TRONG TRUNG

CAPSTONE PROJECTUNG DUNG SCAN COMPRESS DE GIAM

SO LƯỢNG SCAN IO VA TEST TIME

Test cost reduction for Scan IOs and test time with scan compression

techniques in DFT

ENGINEER OF COMPUTER ENGINEERING

HO CHI MINH CITY,2021

VIETNAM NATIONAL UNIVERSITY HO CHI MINH CITY

UNIVERSITY OF INFORMATION TECHNOLOGY

FACULTY OF COMPUTER ENGINEERING

BUI XUAN VIET ANH - 15520013

LE TRONG TRUNG - 16521834

UNG DUNG SCAN COMPRESS DE GIAM

SO LƯỢNG SCAN IO VA TEST TIME

Test cost reduction for Scan IOs and test time with scan compression

techniques in DFT

ENGINEER OF COMPUTER ENGINEERING

SUPERVISOR

PhD NGUYEN MINH SON

M.S NGUYEN DUY MANH THI

HO CHI MINH CITY, 2021

THONG TIN HOI DONG CHAM KHÓA LUẬN TOT NGHIỆP

Hội đồng chấm khóa luận tốt nghiệp, thành lập theo Quyết định số

" ngây của Hiệu trưởng Trường Đại học

Công nghệ Thông tin

VIETNAM NATIONAL UNIVERSITY, SOCIALIST REPUBLIC OF VIET NAM

HO CHI MINH CITY Independence - Liberty — Happiness

UNIVERSITY OF INFORMATION

TECHNOLOGY

CAPSTONE PROJECT

Title: Ung dung scan compress để giảm số lượng scan IO và test time.

Project’s name: Test cost reduction for Scan IOs and test time with scan compression

techniques in DFT

Instructors: PhD Nguyen Minh Son

M.S Nguyen Duy Manh Thi

Duration: From Sep 21* 2020 to Jan 8° 2021

Students:

Bui Xuan Viet Anh - 15520013

Le Trong Trung - 16521834

e Overview:

The first ICs were tested with test vectors created by hand It proved very difficult to get

good coverage of potential faults, so Design for Testability (DFT) based on scan

and automatic test pattern generation (ATPG) were developed to explicitly test each gateand path in a design These techniques were very successful at creating high-qualityvectors for manufacturing test, with excellent test coverage However, as chips got biggerthe ratio of logic to be tested per pin increased dramatically, and the volume of scan testdata started causing a significant increase in test time, and required tester memory ScanCompression is a technique used to reduce the time of testing integrated circuits

e Purpose: Using Scan Compress technique to improve test time and reduce

- Experiment and evaluate parameters.

- Collect result and compare

- Write final report

e Project contents:

Step 1: Research on Scan Compress.

- Have enough knowledge about Scan Compress

- Find out how Scan Compress effect on our

Step 2: Research on Codec

- Learning about Compressor and Decompressor

- Estimate the benefit when applying Codec into Scan step

> Result: know basic architecture of Codec, find the way to use it on design

Step 3: Collect material for setting Scan environment.

- Using NAND block of SNST as sample for using Scan Compress on

- Read sample netlist (Verilog code, library, ) and research sample Scan environment.

- Define Verilog code to implement on our own block

Step 4: Experiment and evaluate parameters

- Implement Internal Scan and Compress Scan in same design

- Changing number of I/O Scan, using “compress ratio” in Compress Scan

Step 5: Collect result and compare

After trial two experiments with two difference corners on same design, we evaluate thedetail parameters between them:

- Scan Compress: have larger area overhead, more numbers of scan chain but more

importantly it makes chains shorter than Internal Scan

- Two types of Scan have almost same Test Coverage, but test time is reduced many

times

Step 6: Write final report

e Limitation:

- This is a fairly new field for us so in the presentation of specialized words certainly

cannot avoid confusing errors

- Because the data of the design is not yet finished, we do not have a license for ATPG

(TMAX tool) so the result cannot be shown in more detail

e Expected results:

- Since the scan chain length is shorter in Compress Scan, but the pin count is identical,

we get lower Test Time

- Reduce test time by 9 to 10 times

-setting Scan environment Le Trong Trung 14/11/2020

4 Experiment and evaluate | Bui Xuan Viet An! 15/11/2020

-parameters Le Trong Trung 30/11/2020

Collect result and 01/12/2020

-5 Bui Xuan Viet Anh

compare between them 14/01/2021

Bui Xuan Viet Anh | 15/12/2020

-6 Write final report

Le Trong Trung 05/01/2021

First of all, we would like to express our sincere thanks to all the teachersand students of the University of Information Technology — Vietnam NationalUniversity Ho Chi Minh city, especially the teachers of Computer Engineering,

who have facilitated us to learn a lot of knowledge and experience throughout thelearning period

In particular, we would like to sincerely thank Dr Nguyen Minh Son and

Mr Nguyen Duy Manh Thi who have guided our group very enthusiasticallythroughout the course of the project, supporting and providing us with valuable

knowledge so that our group can complete the topic well Moreover, we wouldalso like to thank our friends, colleagues who have helped us to improve our

project, to exchange and solve our problem conscientiously during implement the

thesis

Last but not least, we would like to thank our parents for always creating

favorable conditions and spiritual support throughout the course of the dissertation

Despite great efforts, our knowledge and experience are still limited, so thereport can not avoid many shortcomings We are looking forward to receivingmany comments from teachers

Once again, we would like to sincerely thank you!

Ho Chi Minh City, 24 December 2020

Students

Bui Xuan Viet Anh Le Trong Trung

THESIS SUMMARY

In recent decades, the microelectronics industry has made rapid progressthanks to its high-density, integrated lead technology The development of micro-electronic technology is favorable conditions for other industries to develop such

as Information Technology, Telecommunications Electronics, and especially inevery consumer electronic product has the contribution of microelectronic

technology

With many applications as above, the research of integrated microchiptechnology - Application-Specific Integrated Circuits (ASICs) is very necessary

for the current period especially in our country, so I have implemented the topic

“Design for Test design for signal processing chip” The topic covers the basics of

the application-oriented integrated circuit design process (System on Chip flow)

The topic delves into the research and application of DFT (Design for Test)techniques to ensure the ability to test silicon faults, also known as manufacturer-made faults for chips after they have been produced

Through the process of implementing the topic, we have understood the

basic knowledge of circuit design technology as well as related electronic knowledge The topic is done with a serious working attitude and best

micro-efforts, but this is a new field, knowledge is limited so it is impossible to avoidfaults We look forward to receiving the comments of teachers and friends to

improve the topic

TABLE OF CONTENTS

PREFACE us essssssssssssssenecssenensssneneseesesenesenenesessesesenenenesenesseseseseneasnssesseseseneaenenenes 8THESIS SUMMARY scssssssssssesesssssnssesssseenenessssseneeseneneneasseneseseseseaeaesesenenseaes 9

FIGURE LLIST 5-5-5 se SeEEtEtEtetetetrrrrrrkererrkrkrerrsrrerrree 13TABLE LIST IPEEES 15

LIST OF ABBREVIATION esssessssssessvssssesssesvevesensnsssnenseseneaessaeseneeseneseseneasenses 16

Chapter 1 INTRODUCTION ABOUT DESIGN FOR TESTABILITY (DFT)

Scan Insertion flow

.2.1 Read Design

.2.3 DET DRG sưm Đ, / đợ, L Ghi 52.4 Scan ATChif€C{UT ¿+ tt k2 re, 52.5 Insert Scan Path 5c 5c + tt v2.1 1910111210101 5

2.6 DFT DRC COV€TAB6 (11T nn HT HH Hi 5

2.7 Handoff Design + +5 1 tt 1 HH HH ty 6.2.8 Example Scan Insertion SCTipI - +2 2 +5+*+++£s£+x+zezer+ 6

Concepts in the DFT method

3.1 What is Scan Technique

3.3 Modeling silicon faults ccc ¿6+ ky 83.4 Fault Coverage, Test COVeTAE€ ĩc St, 8 °.“ 9.3.Ĩ Scam chạn -s-s- ch HH1 0101012111 11g 13

1.3.7 Scan Methods - + +2 t2 HH HH 110101012 re 141.3.8 Scan Signals and Some Problems Applying Scan Insertion 16

1.4 Automatic Test Pattern Generation ATPG -«- 21Chapter 2 SCAN COMPRESSION TECHNIQUE -5-5-=< 22

2.1 OX1) 10 6 5) be 22

2.1.1 Why we use Compression? ccccccccsesesceseseseseseneeeesesesenenseeeseee 22

2.1.2 How Compression WOrks :.ccccccssesescseseseesesescseneeeeecseseeseeeeseae 23

2.1.3 Test Compression Concepts ¿+55 c+c+csxsccsxsxcxe 23

2.2 CODEC 24

2.2.1 Compressor 25

2.2.2 Decompressor 26Chapter 3 EXPERIMENT ON DATA LAB “ORCA” =< 27

3.1 Overview design - SH HH HH HH gu 00g e 273.1.1 ORCA’s configuration lOgIC ¿+ «5+ 5+++5£+£+ztzexerseserxe 273.1.2 ORCA’s appliCafIOnS cece cS+S* Sư 283.1.3 Input and environment to run đata - ¿55s £+££*c+xcsee 28

3.2 Design Compiler and Design Vision 'T00Ì 5-<5<<=<<<<s< 313.2.1 Read a design into Design Vision -s- 55555555 c<c+xcxe 313.2.2 Tool Design Compiler and Design Vision - - 32

3.2.3 Cell name and ref name 333.2.4 Zoom into examine the schematic .34

3.3 Apply Scan Compression for data lab “OIRCA'” <«« 343.3.1 Where to apply Scan Compression? «+ cc + csee 343.3.2 How to apply Scan Compression? - + 65+ seesxreee 36

Chapter 4 RESULTS s.scssssssssssssssssssessscccsssssescscssassceseenesesscsceceessesceeeeeeseeee 374.2 Report DFT_DRC Violations < 5555555555 ss=sssseseese 38

4.3 Preview DET Ăn HH nhung gu grêp 394.3.1 Intermal Scan - 5+2 tt HH 110111 re 39

4.4 Summary T€SUÏ( s <5 5< 1S <5 5 215154 561g 4I

Chapter 5 CONCLSION 5-5-5 << *xSxEeEEEEsreeeeeeerse 43

5.1 Conclusion c-c<5Ă5 5 S4 Ỳ nh gu gee 435.2 Limitations of the topic e-eceeeesesessstseseteteesrsrsrsrse 43

5.3 Development direction of the fOpÍC 5 <5 <5 5< «<< s=ss< se 43

5.4 Improvement of our project

REFERENCES cscscsessssssesenesesesscsesenesnscsenesesenseseneseseneeseneaeneseseneseseseeseneneneees 45

Scan Insertion Process -¿- + ¿+ 1k E9 HH ni,Design before and after applying Scan [Š] - - -+‹-+-+

Non-scan Flip Flop cccccecceeeecseeeeeescseseesescsesesesesseseseseseeseseneees

Multiplexer Flip Flop cece eee 5c S1 SE 2E

Operation of two clock signals [3] -+-+<+<<++5+<<sc++

Scan Cell as Clocked Scan for Flip Flop -

-Scan Cell as Clocked -Scan for Latches - «+ ©s<++Scan chain [3]J⁄⁄ 6c ÀN Ấn

Pa Ne el a "xe "

Part-Scan [3] ác 1n TT TH HT Hàn Hư

Scan chain in a block (Partition A) [3] - -++<++<<<><s+

Clock through Clock Gating [4] ¿+ 2 2 <+<+s><<<£+c++

Clock signal via Clock Gating processed [4]

-Clock signals shifted through many logics

[4] Clock signals go through multiple processed Logics [4]

Clock signals used as data [4] cseeeeeereceeeeneteeseneeeeeUncontrollable reset signal [5] ccc eeeeseeeeeeseeeeeeneeseeeeneeeesUncontrollable Clr signal [Š] -¿- ¿+ «+5 ++£+£+x++exexsxsx

Figure 2.2 Differences between two scan mode [6] + «<< +++++x<++ 23Figure 2.3 Example for Test Cycle Savings 5 + + sesrsree 24

Figure 2.4 Codec structure [7] - -¿- + ¿+ + %4 E1 9122 E1 51 E1 1 1g re 25Figure 2.5 Compressor Logic Structure Example for 8-to-4 Compressor [7] 25

Figure 2.6 Decompressor Logic Structure Example for 4-to-8 Decompressor [7]

— 26

Figure 3.1 ORCA 1C05 FPGA Die - ¿5c St ttetrtereererrrerree 27

Figure 3.2 ORCA_ TOP structure (RTL code) - ¿5 + + ++s5++s£s<+s+++ 29Figure 3.3 Compressor structure (RTL Code) eee +s+++s<sc+c+++++++ 30

Figure 3.4 Decompressor structure (RTL code) - -‹-¿ -+++++ 31Figure 3.5 Explore the Design ccccccccccsecesescsseseseseseneeeeseseseeneeseseseeeseeeseee 32

Figure 3.6 Cell name and ref name ÏiS( - - 55525252 £+*+*+£s£+c+ezz++ 33

Figure 3.7 Zoom options in Design Vision .ccccccccsceceeeseseeseseseseeneesesesee 34Figure 3.8 ORCA_TOP module with Internal ScanIn - - 35

Figure 3.9 ORCA_TOP module with Compression Scanln - 35Figure 3.10 Command to change Scan mode - s - +5++s©s<+szs+ 36

Figure 3.11 Command to choose number of Scan Chain ‹ «+ 36

Figure 4.1 Flow chart of project

Figure 4.2 DFT_DRC

Figure 4.3 Preview_dft Internal Scan mode - - + «+ ++x++c+csx++ 39

Figure 4.4 Preview_dft Compress Scan mode -++++++<+s+s+ 39

Figure 4.5 Preview_dft Compress Scan mode ¿ ++++©+c+c+sz++s£+ 40Figure 4.6 Period of all clocks in ORCA is 100ns 40Figure 4.7 Real test cycle saving

TABLE LIST

Table 1.1 Two modes of operation of Multiplexer Latch Master-Slave [2] Table 1.2 Clocked Scan's two operating modes for latches [2] Table 4.1 Compare table of two techniques

LIST OF ABBREVIATION

ABBREVIATION FULL MEANING

ATE Automatic Test Equipment

ATPG Automatic Test Pattern Generation

BIST Built-in Self Test

DFT Design for Testability

DRC Design Rule Checks

FC Fault Coverage

FPGA Field Programmable Gate Array

FM Frequency Modulation

IC Intergrated Circuit

LSSD Level Sensitive Scan Design

ORCA Optimized Reconfigurable Cell Array

RTL Register Transfer Level

SoC System on Chip

TATR Test Application Time Reduction

TC Test Coverage

TDVR Test Data Volume Reduction

Chapter 1 ` INTRODUCTION ABOUT DESIGN FOR TESTABILITY

Scan compression was introduced in the year 2000 and has seen rapid

adoption Nearly every design’s test methodology ttoday implements this

technology, which is inserts compression logic in the scan path between the scanV/Os and the internal chains In this project, we take a critical look at the technology

to understand how scan compression has matured

It should be noted that the DFT technique only checks the fault of the designmade by manufacturing without checking the function of the chip, which means itdetermines if the produced chips have any silicon fault, where the fault is in.However, the highest fault checking capacity never reaches 100% because therewill always be positions in the design that we are not able to test

1.1.2 DFT Techniques

This section will present some DFT techniques Since these methods are

not related directly to our project, we will just show them as reference theory

1.1.2.1 Boundary Scan Techniques

Boundary Scan Design is a DFT technique that simplifies testing using astandard chip-board inspection interface This technique performs board-leveltesting by directly granting inputs and pad outputs of integrated circuits (IC) on a

printed circuit board Boundary Scan changes the input and exit pad values ofseparate IC's and adds the control logic to the input and exit pad of each Boundary

Scan IC combined into the form of a board-level scan string

Chip B Chip C

Test data output

Chip A

Chip D

Test data input 10 pads of Boundary Scan

Figure 1.1 Design using Boundary Scan DesignBoundary Scan uses scanning strings to retrieve the ports of the chips onthe board Because the scan string consists of the inputs and output pads of a chipdesign, the inputs and outputs are retrieved on the board to send and receive data.Boundary Scan Technique checks for faults that hit the source or the ground, short,open on the wire on a printed circuit board but limited to separate chips on theboard

1.1.2.2 Memory BIST Insertion Technique

Memory BIST Insertion is a DFT technique, which consists of controllogics that use different algorithms to create input test patterns, which are used tocheck for faults in memory blocks (Ram or Rom) of a design The BIST Logic isachieved according to these algorithms determined based on the information ofmemory such as configuration, size The BIST logic is written in RTL code andwill also be Synthesis as other Logics in design

BIST logic creates input test samples (based on pre-defined algorithms) to

test memory blocks, the outputs of which will be returned to BIST Logic There is

a comparative set that will perform a comparison of the output with the previouscorrect result The output of the comparer will be a pass/fail signal that says thememory block checking for errors

Test pattern BIST Test response

generator Control analysator

Figure 1.2 Design using Memory BIST

1.1.2.3 Logic BIST Insertion Technique

This technique is like memory BIST, BIST logic uses the same way but the

purpose now is to test the logical parts in the design The BIST Insertion Logictechnique uses random test sample creation to perform scan sequences in thedesign The output is also compared to the simulated signal to see if the test logicblock is at fault

The two memory and BIST logic techniques have the advantage of being

test samples created by BIST logic, the designer will not interfere with this process

But these two techniques have the disadvantage of having to add logic in the designjust to perform the test function, the design area will increase much.

1.2 Scan Insertion flow

With an RTL design, an RTL code test must be performed following DFT

laws, in practice often the process of checking RTL code by DFT rules is carriedout before Synthesis and Scan Insertion But attention only stops at the level oftesting and editing RTL code, Scan Insertion is applied only after the Gate_level

Netlist

To understand, we can divide the Scan Insertion process into stages, but thestage division is only relative because the process is carried out by the next personsmoothly through DFT software

Figure 1.4 Scan Insertion Process

Handoff Design

1.2.1 Read Design

- Read a mapped design (read_ ddc, read_verilog_)

- Scan insertion is performed on mapped designs

1.2.2 Create Test Protocol

- The Test Protocol describes how the design operates in scan mode

- Signals involved in the protocol are declared with the set_dft_signal

command

- The protocol is created by the “create_test_protocol” command

1.2.3 DFT DRC

- The dft_ drc command perform DRC checks prior to scan insertion

- DRC violations can be debugged graphically with DesignVision or fixed by

DFT Compiler with Autofix

1.2.4 Scan Architecture

- Various commands control the scan architecture (number of scan chains, how

clock domains are handled, etc.)

- The commands primarily used to control the scan architecture are the

“set_scan_configuration” and “set scan path” commands

1.2.5 Insert Scan Path

- The preview_ dft command is used to get a preview of the scan architecture

before it is actually implemented in the design

- The preview step allows for a quicker integration cycle when changes need

to be made to the scan architecture

1.2.6 DFT DRC Coverage

- DFT DRC checks can also be run after scan insertion to validate that the scan

chains trace properly

- DFT DRC can also be used to get an ATPG coverage estimate for the scan

inserted design

1.2.7 Handoff Design

- The design handoff is where files are written to disk that will be needed later

on in the design process

- Examples: design DDC, Verilog netlist, protocol file (for TetraMax), Test

Model (for Bottom-Up flows), Scandef (for backend scan chain reordering),

write_scan_def —o scanned.scandef

write —f ddc —hier —o scanned.ddc

write —f verilog —hier —o scanned.v

write_test_protocol —o scanned.spf

1.3 Concepts in the DFT method

1.3.1 What is Scan Technique

As a Technique that will be researched in the project, Scan Technique willreplace normal cells (non-scan cells) with cells with additional scanning cellfunction When performing replacement, the function of the design will not change

which means that it still works properly and fully functionally but the design that

has been made Scan Insertion will have an additional silicon fault checkingfunction after production

1.3.2 Scan Insertion Technique

Scan Insertion is the most general technique using in Design for Test It issupported by many synthesis tools (Synopsys, Cadence ) The Scan Insertiontechnique will check for faults in sequential circuits (including flip-flops) byreplacing non-scan cells with scan cells reconnect into scan registers, also known

as scan chains

Sa 1B

Sa

Before Scan After Scan

Figure 1.5 Design before and after applying Scan [5]

- The “scan_in” and “scan_enable” signal is two new signals when applying

Scan Technique

- The red bus (scan_in data) will go through all flip-flops are able to be scanned

After scanning the last flip-flop of the scan chain, scan_in will become

scan_out.

- Every flip-flop which has scan_in data are also have scan_enable data This

data is use to “turn on or off” the scan signal when it come into the flip-flop

1.3.3 Modeling silicon faults

The purpose of the Scan Insertion technique is to help the design to checkfor silicon faults, also known as manufacturer faults, common silicon faults:

- Hits the source, hits the ground

- Ruptured the silicon lines

- Silicon lines touching each other (short fault)

The above physical faults will affect the functioning of the design, we mustmodel the above faults to support the fault checking to:

- The process of creating test samples and analyzing them in the design

process will be easier

- Fault checking will be more effective

1.3.4 Fault Coverage, Test Coverage

Fault Coverage determines the aspect ratio of testable nodes on the totalnumber of nodes in a design

Number of testable node

Fault Coverage = ———Tgtainode (11)

Test Coverage is used to determine the ability to test a design's fault after

production has been produced Once all the buttons can be identified for a designand test samples created for testable nodes, chips after production will be testedfor silicon faults based on test samples Test Coverage is defined as follows:

Number of tested node

A manufactured product is a collection of millions of silicon units, so it isnecessary to achieve good results on Fault Coverage to lower the number of Chips

with faulty components delivered to customers

1.3.5 Scan Cell

The Scan Insertion process will replace the non-scan cell with the cell scan,the non-scan cell is the cell does not have scanning function but only works

properly the normal function of the cell, the cell scan is the cell can operate in two

modes: Functional and scan, but it has more scanning function in scan mode Thereare many different types of structural cell scans used:

- Scan Cell as Multiplexer flip-flop

- Scan Cell as Clocked Scan

- Scan Cell as Level Sensitive Scan Design (LSSD)

- Scan Cell as Auxiliary-Clock LSSD

1.3.5.1 Scan cell as Multiplexer flip-flop

Multiplexer uses multi-input data to be a serial shift In functional mode,the scan-enable signal is used to select the system data for the input In scan mode,the scan-enable signal is used to select the scan data for the input Scanned datacan be obtained from the input port or the output of the previous cell in the scansequence Corresponding test signals on this cell:

Figure 1.6 Non-scan Flip Flop

In Error! Reference source not found., the scan-in signals are used forscan-in test signals, the scan-enabled signals are used for scan enable test signals,

and the scan-out test signal is shared with the Q function foot (output) of flip flop

Q/Scan out D

Figure 1.8 Multiplexer Master-Slave

An important note in the operation of multiplexer cell scanning

Master-Slave latches is that the two clock signals are m-clock and s-clock are not

overlapping (nonoverlapping)

Features of Multiplexer flip flop cell scanning:

- Add a delay due to the multi-component added to the structure

- Increasing the area, a Multiplexer flip-flop D is 15% larger than the standard

D flip-flop area

- Atleast one I/O port (scan-enable)

- Pins supported asynchronous

- For clock-edge impact design

10

Table 1.1 Two modes of operation of Multiplexer Latch Master-Slave [2]

d scan_in scan_enable m_clk s_clk q qb Mode

Slave clock

(scan clock bì }

Figure 1.9 Operation of two clock signals [3]

1.3.5.2 Scan as Clocked Scan

Clocked Scan cell scanning formed from latches In functional mode, thecell operates according to the level of the clock signal, and system data is insertedinto the cell at each high pulse level In scan mode, the cell scan works on the edge

of the test clock signal and the scan data is inserted into the cell at each edge up

Test signals are required in the Clocked-Scan Cell:

Clocked-Scan cell scanning replaces a flip-flop: in Figure 1.10 scan-in port,

scan enable port are used for corresponding scan-in signals, scan enable, scan-outwhich sharing Q port

11

activated according to the clock pulse level, while in the scanning mode it isactivated according to the clock pulse edge Error! Reference source not found.

is a Clocked Scan-type cell scan replacing the default latch provided by the DFTCompiler, the pins used for functional signals and test signals are detailed in

Some characteristics to pay attention to in this type of cell scan:

Has an insignificant speed effect

Increased area due to Clocked-Scan Cell area greater than 15-30% flip-flop

12

D standard

The technical library supports both flip-flop and pins respectively for thistype of scan

This type of cell scanning can be used in partial-scan designs (to be

surveyed later), the test clock signal can maintain non-scan status for thesecell scans in the scan mode of the design

The latch is supported with clear pins and asynchronous syncing reset

Use in designs triggered by edges

Scan chain

Applying a two-stage Scan Insertion, the DFT Compiler will first identifythe sequential cells in the design and replace them with the corresponding cellscans The next segment is to connect the scanning cell in the design into astructure used in scanning mode The structure created is called a scan chain orscan path The cells in the scan series are scanned cells that can be controlled andinspected

A controllable cell is a cell where one can grant the desired value to its input

by translating the logical values that define the primary input

An observable cell is a cell where one can know its state by translated thedata

1.3.7 Scan Methods

The structure of the scan chain depends on the scanning method applied:

The full scan method and partial scan method

1.3.7.1 Full scan

Scan Output

Scan Input

Figure 1.13 Full Scan [3]

The entire scanning method will replace all sequential cells with the

corresponding cell scans in the design and will then reconnect them into scansequences This makes it possible to control and observe all the components in thedesign so that the process of creating test patterns and faults simulation insequential circuits is as simple as in combinational circuits With designs that usefull scanning, when using the Scan Insertion tool, the process of performing a fullscan for a design is done automatically at a high level, requiring little interventionfrom the designer Besides, this method will give high results for the design

1.3.7.2 Part-scan

In the full scanning method, all sequential cells will be replaced by ScanCell in the library, but not all designs can use this method because of the conditions

of time and area The part scanning method only performs the replacement of

certain components in the design with the corresponding cell scans and reconnects

to the scan sequence This method will reduce time and area conflicts with an

acceptable Test Coverage result

14