emerging nanotechnologies. test, defect tolerance, and reliability, 2008, p.411

[...]... present novel methods of test and defect tolerance for such high defect density nano-devices The proposed methods try to alleviate problems such as (1) defect identification, localization and isolation, (2) defect map generation and defect avoidance, (3) test under very high defect rates, and (4) design flow under high defect rates condition The first chapter, entitled Defect- Tolerant Logic with Nanoscale... that can be achieved for a given defect density Simulation results are presented for various nanofabric sizes, different defect densities, and for random and clustered defects The third chapter entitled “Test and Defect Tolerance for Reconfigurable Nanoscale Devices” presents a solution to dealing with issues such as storing large defect map size and per chip placement and routing In this chapter, the... pullup and 16 T Hogg and G Snider pullup crossbar AND crossbar OR crossbar inputs outputs pulldown crossbar Fig 9 Model of diode array as a set of four connected crossbars The AND and OR crossbars have configurable diode junctions, while the pullup and pulldown crossbars have configurable resistor junctions Any junction in any crossbar may be defective, though the defect rate for junctions in the pullup and. .. junctions between the nanowires and much larger, microscale, wires Thus the junction area per device is significantly larger than that for the diode junctions used in the AND and OR crossbars This increased junction area means the chance of a defective resistor is far smaller than having a defective diode Even though the AND and OR crossbars share the same junction type and could be represented with a... particularly defects Creating such circuits in spite of fabrication defects requires economic trade-offs For instance, accepting lower yields or improving fabrication could reduce defect rates, but increase production cost Algorithmic configuration strategies for defect- tolerant systems [28], discussed in this chapter, provide higher defect tolerance, but add to manufacturing cost with the additional testing and. .. implemented and can also result in longer runtimes for the compiler to identify a way to implement the circuit while avoiding the defects Furthermore, a logical formula can be written in various logically equivalent forms, e.g., (a OR b) AND c (a AND c) OR (b AND c) are logically equivalent These rewrites can involve different numbers of terms, and hence require different crossbar areas and shapes to... logical AND of k inputs One implementation is as a single k-input AND gate, i.e., using k connections to a single output wire Another implementation is to decompose 10 T Hogg and G Snider (a) (b) output output output output Fig 4 Logic gates: a 4-input AND, and the same function using 2-input AND gates Also shown is an implementation of these circuits using parts of a crossbar network the AND into... circuits for memory and logic applications However, currently feasible manufacturing technologies for molecular electronics introduce numerous defects so insisting on defect- free crossbars would give unacceptably low yields Conventional test and defect tolerance methods employed for CMOS reconfigurable devices such as FPGA are not applicable to emerging nanoscale devices due mainly to the high defect rates... novel defect avoidance methods for reconfigurable nanoscale crossbar-based devices The proposed defect tolerance methods are independent on defect map and avoid per chip placement and routing The test procedure proposed in this chapter is a builtin self-test method that tests the function implemented on a logic block instead of testing the block itself The method avoids generation of large defect map and. .. representing the desired circuit and compound crossbars; and (2) searching for an embedding or monomorphism between the circuit graph and the compound crossbar graph t u v t u v x t u v t u v x y z z perfect crossbar y x y z x y z defective crossbar Fig 10 Representing a crossbar with a graph Wires and junctions in the crossbar correspond to nodes and edges of the graph, respectively Defective junctions are . crossbar-based devices. The proposed defect tolerance methods are independent on defect map and avoid per chip placement and routing. The test procedure proposed in this chapter is a built- in self-test. a final mapping step is required to be defect- aware. Application independence of Section 1: Test and Defect Tolerance for Crossbar-Based Architectures 3 this flow minimizes the amount of per chip design. alleviate problems such as (1) defect identification, localization and isolation, (2) defect map generation and defect avoidance, (3) test under very high defect rates, and (4) design flow under high defect