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Khóa luận: Thiết kế bộ chuyển đổi tương tự số 12 bits SARADC nhằm cải thiện hiệu năng màn hình tft

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Bộ chuyển đổi tương tự sang số là bộ chuyển đổi tín hiệu tương tự sang tín hiệu số, gọi tắt là ADC ( Analog to Digital Converter). Có rất nhiều loại ADC trên thị trường, trong đó có SARADC, loại này có nhiều ưu điểm hơn các loại ADC khác, nó có độ chính xác cao và tiêu thụ điện năng thấp. Do có độ chính xác cao nên SARADC thường được dùng để cải thiện hiệu năng cho các loại màn hình cảm ứng điện trở có trên thị trường. Loại màn hình cảm ứng điện trở là loại màn hình cảm ứng đơn điểm, nhược điểm của loại màn hình này là có độ trễ khá lớn và độ chính xác không cao. SARADC hoàn toàn có thể khắc phục những nhược điểm đó trên màn hình cảm ứnng điện trở, cụ thể là màn hình TFT.

ĐẠI HỌC QUỐC GIA HÀ NỘI TRƯỜNG ĐẠI HỌC CÔNG NGHỆ Nguyễn Tuấn Anh THIẾT KẾ BỘ CHUYỂN ĐỔI TƯƠNG TỰ - SỐ 12 BITS SAR-ADC NHẰM CẢI THIỆN HIỆU NĂNG MÀN HÌNH TFT KHĨA LUẬN TỐT NGHIỆP ĐẠI HỌC HỆ CHÍNH QUY Ngành: Cơng nghệ kỹ thuật điện tử truyền thông HÀ NỘI – 2023 ĐẠI HỌC QUỐC GIA HÀ NỘI TRƯỜNG ĐẠI HỌC CÔNG NGHỆ Nguyễn Tuấn Anh THIẾT KẾ BỘ CHUYỂN ĐỔI TƯƠNG TỰ - SỐ 12 BITS SAR-ADC NHẰM CẢI THIỆN HIỆU NĂNG MÀN HÌNH TFT KHĨA LUẬN TỐT NGHIỆP ĐẠI HỌC HỆ CHÍNH QUY Ngành: Công nghệ kỹ thuật điện tử truyền thông Cán hướng dẫn: PGS.TS Mai Anh Tuấn HÀ NỘI - 2023 VIETNAM NATIONAL UNIVERSITY, HANOI UNIVERSITY OF ENGINEERING AND TECHNOLOGY Nguyen Tuan Anh DESIGN 12-BIT SUCCESSIVE-APPROXIMATION DIGITAL-TO-ANALOG CONVERTER (SAR-ADC) TOWARD AN IMPROVEMENT OF TFT DISPLAY PERFORMANCE Major: Electronics and Communications Engineering Technology Supervisor: Assoc Prof Mai Anh Tuan HA NOI - 2023 TĨM TẮT NỘI DUNG Tóm tắt: Ngày nay, giới dụng cụ đo lường khoa học, tất kết đo lường số hoá, tức chuyển đổi sang miền kĩ thuật số Đầu tương tự cảm biến cặp nhiệt điện, máy đo biến dạng, máy đo gia tốc, cảm biến lực chuyển vị, v.v., số hố cho mục đích ghi, hiển thị phân tích Máy tính kĩ thuật số tương tác với tín hiệu phổ biến nhờ chuyển đổi tương tự sang kĩ thuật số Bộ chuyển đổi tương tự sang số chuyển đổi tín hiệu tương tự sang tín hiệu số, gọi tắt ADC ( Analog to Digital Converter) Có nhiều loại ADC thị trường, có SARADC, loại có nhiều ưu điểm loại ADC khác, có độ xác cao tiêu thụ điện thấp Do có độ xác cao nên SAR-ADC thường dùng để cải thiện hiệu cho loại hình cảm ứng điện trở có thị trường Loại hình cảm ứng điện trở loại hình cảm ứng đơn điểm, nhược điểm loại hình có độ trễ lớn độ xác khơng cao SAR-ADC hồn tồn khắc phục nhược điểm hình cảm ứnng điện trở, cụ thể hình TFT Từ khóa: SAR-ADC i ABSTRACT Abstract: Today, in the world of scientific measuring instruments, almost all measurement results are digitized, i.e converted to the digital domain Analog outputs of sensors such as thermocouples, strain gauges, accelerometers, force and displacement sensors, etc., are digitized for recording, display and analysis purposes Digital computers can interact with these common signals by converting analog to digital An analog to digital converter is an analog to digital converter, referred to as ADC (Analog to Digital Converter) There are many types of ADCs on the market, including SAR-ADC, which has many advantages over other ADCs, it has high accuracy and low power consumption Due to its high accuracy, SAR-ADC is often used to improve the performance of resistive touch screens on the market Resistive touch screen type is a single-point touch screen, the disadvantage of this type of screen is that it has a large delay and is not accurate SAR-ADC can completely overcome those disadvantages on resistive touch screens, specifically TFT display Keywords: SAR-ADC ii ACKNOWLEDGMENTS First of all, I would like to express my sincere and deep gratitude to Assoc Prof Mai Anh Tuan for his dedicated guidance and advice, providing valuable experiences for me during the time of researching and carrying out my thesis I also want to express my sincere thanks to the teachers in the University of Engineering and Technology for creating opportunities for me to study and develop myself during my four years at the school, helping me acquire the basic skills to be able to complete my thesis Furthermore, having these skills prepared me to take on the world with confidence Although I have tried my best, my graduation thesis cannot avoid some shortcomings I respectfully request the teachers and friends to provide suggestions to improve my thesis Finally, I wish the teachers and everyone good health and success in their life and teaching careers, and to prepare the next generation of knowledgeable citizens for the country Thank you very much! Student Nguyen Tuan Anh iii LỜI CAM ĐOAN Tôi xin cam đoan đề tài “Thiết kế chuyển đổi tương tự - số 12bits SAR-ADC nhằm cải thiện hiệu hình TFT ” khóa luận tốt nghiệp thân thực suốt thời gian vừa qua hướng dẫn PGS.TS Mai Anh Tuấn Những số liệu kết nghiên cứu hồn tồn trung thực khơng chép người khác mà không rõ mặt tài liệu tham khảo Nếu khơng thật, tơi xin chịu hồn toàn trách nhiệm Hà Nội, ngày…tháng…năm 2023 Sinh viên Nguyễn Tuấn Anh iv CONTENTS TÓM TẮT NỘI DUNG i ABSTRACT ii ACKNOWLEDGMENTS iii LỜI CAM ĐOAN iv CONTENTS v IMAGE CATALOG viii LIST OF TABLES x PREFACE CHAPTER INTRODUCTION .4 1.1 Overview of ADC 1.1.1 History of ADC 1.1.2 Type of ADC 10 1.2 Overview of SAR-ADC 14 1.3 Overview of TFT Display .15 1.3.1 What is TFT screen? 15 1.3.2 Advantages and disadvantages of TFT screens compared to other screens 16 1.3.3 Application of TFT 17 1.4 The impact of ADC on the performance of TFT Display 18 1.5 Compare SAR ADC and conventional ADC .19 v 1.6 Objective 19 CHAPTER LITERATURE REVIEW 21 CHAPTER DESIGN .22 3.1 SAR ADC architecture and operation 22 3.2 Sample and Hold circuit 23 3.2.1 Cmos Technology 25 3.2.2 Bootstrapped sample and hold circuit 27 3.3 Digital Analog Converter circuit 29 3.3.1 Split capacitor Digital to Analog Converter 33 3.3.2 Perform 34 3.4 Comparator circuit .35 3.4.1 Comparative Criteria .39 3.5 Successive-Approximation-Register control logic block 39 3.5.1 D flip-flops with Set/Reset 41 3.5.2 Perform 41 CHAPTER RESULTS AND CONCLUSIONS 45 4.1 RESULTS 45 4.1.1 Sample and Hold .45 4.1.2 Digital to Analog converter 45 4.1.3 Comparator .46 4.1.4 SAR 47 vi 4.2 CONCLUSION .49 REFERENCES 51 vii Figure 26: SAR block simulation Successive-Approximation-Register control logic block (control logic) is required to execute the binary search algorithm in order to determine the quantization level that corresponds to the final analog input of SAR ADC Figure 27: Successive-Approximation-Register control logic block Figure- depicts the control logic framework It is made up of two rows of flipflops They are connected sequentially from D13 to D0 in the first row for the purpose of setting the output of the register from D12 to D1 equal to "1" on each positive edge of the clock signal and resetting "0" afterwards The outputs of each flip-flop are then used to operate the row two registers The second row contains 12 registers numbered D12' to D1', with each register's input Set being the output of the first row's registers, input Reset being the Sample signal, input D being the voltage of the comparator 40 block, and clock signal being the output of the next register D12' - D1' output is also output 3.5.1 D flip-flops with Set/Reset All of the flip-flops used in this design are D flip-flops with a Set/Reset signal The operation of a D flip-flop is based on the clock signal (CLK), the set signal (S), and the reset signal (R) If the Set signal is "1" and the Reset signal is "0," the output (Q) will be "1" regardless of CLK or D If, on the other hand, S equals "0" and R equals "1," Q must be "0." Figure 28: D Flip-flop circuit which uses NAND gate 3-to-1 to build up this structure Another case, if both S and R are “0”, with each positive edge of the clock signal, output Q equals D Figure- shows the D Flip-flop circuit which uses NAND gate 3-to1 to build up this structure 3.5.2 Perform During the sample phase (sample = "1"), the input Set of row one's first register (D14) and the input Reset of the other registers are connected to the sample signal; additionally, input Reset is "0" and input D is connected to ground "0." As a result, output Q13 is set to "1" while the others are set to "0." During the hold phase (sample = "0"), S = "0", R = "0", with each clock's positive edge, from Q12 to Q0 is set to "1" and reset to "0" in the next clock, so input S of D12' - D1' are "1" and equal "0" in the 41 next clock The voltage comparator is connected to Input Reset = "0" and D12' - D1' Because the next register's output is connected to the current register's input Clock (CLK) When the next register's output is "1," the output of the current register is a voltage comparator (Vcomp) The output of the final register D0 is the Done signal, which indicates when the process is complete Figure depicts the SAR control logic schematic 10 11 sampling CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK 10 CLK 11 First Row Register Outputs D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 1: First Row Register Outputs 42 10 11 sampling CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK 10 CLK 11 sampling D’9 B9 B9 B9 B9 B9 B9 B9 B9 B9 B9 D’8 0 B8 B8 B8 B8 B8 B8 B8 B8 B8 Second Row Outputs Comparator Output D’7 D’6 D’5 D’4 D’3 D’2 D’1 D’0 Vcomp 0 0 0 0 x 0 0 0 0 B9 0 0 0 0 B8 0 0 0 B7 B7 0 0 0 B6 B7 B6 0 0 B5 B7 B6 B5 0 0 B4 B7 B6 B5 B4 0 B3 B7 B6 B5 B4 B3 0 B2 B7 B6 B5 B4 B3 B2 B1 B7 B6 B5 B4 B3 B2 B1 B0 B7 B6 B5 B4 B3 B2 B1 B0 x Table 2: Second Row Outputs The SAR (Successive Approximation Register) Control Logic block is an essential part of the A/D (Analog-to-Digital) converter circuit that converts an analog input signal into a digital output signal The SAR Control Logic block operates in a feedback loop with a DAC (Digital-to-Analog Converter) to iteratively approximate the input signal and generate the resulting digital code During the A/D conversion process, the SAR Control Logic block performs a comparison between the input signal voltage and a threshold voltage generated by a DAC This comparison process determines the value of the most significant bit (MSB) of the resulting digital code After the MSB is determined, it is stored in a counter within the SAR Control Logic block, and the First Row Register Outputs are generated These signals represent the bits of the resulting number and are typically labeled as D0, D1, D2, , D(N-1), corresponding to the N-bit result The First Row Register Outputs are then fed into the next block of logic to generate the Second Row Outputs This logic block usually consists of a series of digital comparators that compare the First Row Register Outputs to a new threshold voltage (usually half of the threshold voltage used in the SAR Control Logic block) 43 The outputs of these comparators determine the value of the next bit of the resulting digital code, which is then stored in flip-flops to create the Second Row Outputs These outputs, labeled D’0, D’1, D’2, , D’(N-1), represent the final result of the A/D conversion process In summary, the SAR Control Logic block generates the First Row Register Outputs by comparing the input signal voltage to a threshold voltage and determining the value of the MSB of the resulting digital code The Second Row Outputs are then generated by comparing the First Row Register Outputs to a new threshold voltage and determining the value of the next bits of the resulting digital code Together, these outputs represent the final result of the A/D conversion process and are used in a wide variety of applications, including data acquisition, sensing, and control systems 44 CHAPTER RESULTS AND CONCLUSIONS 4.1 RESULTS 4.1.1 Sample and Hold Simulation: Figure 29: Simulation the Sample and Hold Simulation the Sample and Hold with les than Votage Input less than 1, frequency 50KHZ, simple signal=1MHZ, the output at the simple phase gave the signal Votage input to pas correctly 4.1.2 Digital to Analog converter Simulation with Vin = 600mV, Vref = 1V 45 Figure 30: Simulation DAC with Vin = 600mV, Vref = 1V Error due to imperfect capacitor 4.1.3 Comparator Simulation with Vin = 600mV, Vref = 1V Figure 31: Simulation Comparator with Vin = 600mV, Vref = 1V VDAC < => Vcomp high 46 VDAC > => Vcomp low 4.1.4 SAR Simulation with Vin = 600mV, Vref = 1V Figure 32: Simulation SAR control logic with Vin = 600mV, Vref = 1V Gradually shift from high S12-S1 with each CLK and record the value of Vcomp immediately after that Initially, we get the bits from the SAR control logic and then go through the ideal DAC to get the reconstructed signal of Vin in the following figures Simulation with Vin = 900mV, Vref = 1V 47 Figure 33: Simulation SAR control logic with Vin = 900mV, Vref = 1V Simulation with Vin = 700mV, Vref = 1V Figure 34: Simulation SAR control logic with Vin = 700mV, Vref = 1V Simulation with Vin = 600mV, Vref = 1V 48 Figure 35: Simulation SAR control logic with Vin = 600mV, Vref = 1V 4.2 CONCLUSION The thesis " Design of 12bits SAR-ADC analog-to-digital converter to improve TFT performance " has completed the set objectives and achieved the following specific results: Result: - TFT display performance optimization is a major challenge in the field of electronics and telecommunications In a TFT display, using a SAR ADC to convert analog signals to digital signals can improve system performance and reduce energy consumption - The project results show that designing a SAR ADC for TFT requires a number of factors, including sampling frequency, resolution, accuracy, and signal purity Furthermore, evaluating and comparing various designs is an important part of optimizing system performance 49 - It should be noted, however, that improving TFT screen performance is dependent not only on the SAR ADC, but also on many other factors such as the use of highquality components, as well as the proper design and layout suitable circuit - With the project's findings, it is hoped that this research will help to improve the performance of TFT screen systems in the future Future work: - Future work for the design of a SAR ADC may include further optimization of the design for improved performance and energy efficiency One potential approach is to investigate new circuit topologies and architectures that can reduce power consumption while maintaining or improving the ADC's speed and accuracy - Another area of future work could be the integration of on-chip calibration circuits, which can automatically correct for errors caused by variations in manufacturing processes, temperature, and other factors This could help to further improve the ADC's accuracy and reduce the need for external calibration - In terms of the advantages of SAR ADCs, they offer high accuracy, low power consumption, and excellent linearity They are also relatively easy to implement and can be integrated into a wide range of systems and applications - However, there are also some drawbacks to SAR ADCs that need to be addressed in future designs One of the main limitations is their relatively low sampling rates, which can limit their use in high-speed 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