Microelectronic circuit design 4th edition jaeger

Jaeger-1820037 jae80458˙FM˙i-xxvi January 22, 2010 15:50 MICROELECTRONIC CIRCUIT DESIGN i This page intentionally left blank Jaeger-1820037 jae80458˙FM˙i-xxvi January 22, 2010 21:9 Fourth Edition MICROELECTRONIC CIRCUIT DESIGN Richard C Jaeger Auburn University Travis N Blalock University of Virginia TM iii Jaeger-1820037 jae80458˙FM˙i-xxvi January 22, 2010 15:50 TM MICROELECTRONIC CIRCUIT DESIGN, FOURTH EDITION Published by McGraw-Hill, a business unit of The McGraw-Hill Companies, Inc., 1221 Avenue of the Americas, New York, c 2011 by The McGraw-Hill Companies, Inc All rights reserved Previous editions  c 2008, 2004, NY 10020 Copyright  and 1997 No part of this publication may be reproduced or distributed in any form or by any means, or stored in a database or retrieval system, without the prior written consent of The McGraw-Hill Companies, Inc., including, but not limited to, in any network or other electronic storage or transmission, or broadcast for distance learning Some ancillaries, including electronic and print components, may not be available to customers outside the United States This book is printed on recycled, acid-free paper containing 10% postconsumer waste WDQ/WDQ ISBN 978-0-07-338045-2 MHID 0-07-338045-8 Vice President & Editor-in-Chief: Marty Lange Vice President, EDP / Central Publishing Services: Kimberly Meriwether-David Global Publisher: Raghothaman Srinivasan Director of Development: Kristine Tibbetts Developmental Editor: Darlene M Schueller Senior Sponsoring Editor: Peter E Massar Senior Marketing Manager: Curt Reynolds Senior Project Manager: Jane Mohr Senior Production Supervisor: Kara Kudronowicz Senior Media Project Manager: Sandra M Schnee Design Coordinator: Brenda A Rolwes Cover Designer: Studio Montage, St Louis, Missouri Senior Photo Research Coordinator: John C Leland Photo Research: LouAnn K Wilson Compositor: MPS Limited, A Macmillan Company Typeface: 10/12 Times Roman Printer: Worldcolor All credits appearing on page or at the end of the book are considered to be an extension of the copyright page Library of Congress Cataloging-in-Publication Data Jaeger, Richard C Microelectronic circuit design / Richard C Jaeger, Travis N Blalock — 4th ed p cm ISBN 978-0-07-338045-2 Integrated circuits—Design and construction Semiconductors—Design and construction Electronic circuit design I Blalock, Travis N II Title TK7874.J333 2010 621.3815—dc22 2009049847 www.mhhe.com iv Jaeger-1820037 jae80458˙FM˙i-xxvi January 22, 2010 15:50 TO To Joan, my loving wife and partner —R i c h a r d C J a e g e r In memory of my father, Professor Theron Vaughn Blalock, an inspiration to me and to the countless students whom he mentored both in electronic design and in life —T r a v i s N B l a l o c k v Jaeger-1820037 jae80458˙FM˙i-xxvi January 22, 2010 15:50 B RI E F C O NTEN T S Preface xx PART ONE Solid State Electronics and Devices Introduction to Electronics Solid-State Electronics 42 Solid-State Diodes and Diode Circuits 74 Field-Effect Transistors 145 Bipolar Junction Transistors 217 Operational Amplifier Applications 697 Small-Signal Modeling and Linear Amplification 786 Single-Transistor Amplifiers 857 Differential Amplifiers and Operational Amplifier Design 968 16 Analog Integrated Circuit Design Techniques 1046 17 Amplifier Frequency Response 1128 18 Transistor Feedback Amplifiers and Oscillators 1228 12 13 14 15 APPENDIXES PART TWO Digital Electronics Introduction to Digital Electronics 287 Complementary MOS (CMOS) Logic Design 367 MOS Memory and Storage Circuits 416 Bipolar Logic Circuits 460 PART THREE Analog Electronics 10 Analog Systems and Ideal Operational Amplifiers 529 11 Nonideal Operational Amplifiers and Feedback Amplifier Stability 600 vi A Standard Discrete Component Values 1300 B Solid-State Device Models and SPICE Simulation Parameters 1303 C Two-Port Review 1310 Index 1313 Jaeger-1820037 jae80458˙FM˙i-xxvi January 22, 2010 15:50 C O NTE NTS Preface xx CHAPTER SOLID-STATE ELECTRONICS 42 PART ONE SOLID STATE ELECTRONIC AND DEVICES 2.1 2.2 2.3 CHAPTER INTRODUCTION TO ELECTRONICS 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 A Brief History of Electronics: From Vacuum Tubes to Giga-Scale Integration Classification of Electronic Signals 1.2.1 Digital Signals 1.2.2 Analog Signals 1.2.3 A/D and D/A Converters—Bridging the Analog and Digital Domains 10 Notational Conventions 12 Problem-Solving Approach 13 Important Concepts from Circuit Theory 15 1.5.1 Voltage and Current Division 15 Th´evenin and Norton Circuit 1.5.2 Representations 16 Frequency Spectrum of Electronic Signals 21 Amplifiers 22 1.7.1 Ideal Operational Amplifiers 23 1.7.2 Amplifier Frequency Response 25 Element Variations in Circuit Design 26 1.8.1 Mathematical Modeling of Tolerances 26 1.8.2 Worst-Case Analysis 27 1.8.3 Monte Carlo Analysis 29 1.8.4 Temperature Coefficients 32 Numeric Precision 34 Summary 34 Key Terms 35 References 36 Additional Reading 36 Problems 37 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 Solid-State Electronic Materials 44 Covalent Bond Model 45 Drift Currents and Mobility in Semiconductors 48 2.3.1 Drift Currents 48 2.3.2 Mobility 49 2.3.3 Velocity Saturation 49 Resistivity of Intrinsic Silicon 50 Impurities in Semiconductors 51 2.5.1 Donor Impurities in Silicon 52 2.5.2 Acceptor Impurities in Silicon 52 Electron and Hole Concentrations in Doped Semiconductors 52 2.6.1 n-Type Material (N D >N A ) 53 2.6.2 p-Type Material (N A >N D ) 54 Mobility and Resistivity in Doped Semiconductors 55 Diffusion Currents 59 Total Current 60 Energy Band Model 61 2.10.1 Electron–Hole Pair Generation in an Intrinsic Semiconductor 61 2.10.2 Energy Band Model for a Doped Semiconductor 62 2.10.3 Compensated Semiconductors 62 Overview of Integrated Circuit Fabrication 64 Summary 67 Key Terms 68 Reference 69 Additional Reading 69 Important Equations 69 Problems 70 CHAPTER SOLID-STATE DIODES AND DIODE CIRCUITS 74 3.1 The pn Junction Diode 75 3.1.1 pn Junction Electrostatics 75 3.1.2 Internal Diode Currents 79 vii Jaeger-1820037 jae80458˙FM˙i-xxvi viii January 22, 2010 15:50 Contents 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 The i-v Characteristics of the Diode 80 The Diode Equation: A Mathematical Model for the Diode 82 Diode Characteristics Under Reverse, Zero, and Forward Bias 85 3.4.1 Reverse Bias 85 3.4.2 Zero Bias 85 3.4.3 Forward Bias 86 Diode Temperature Coefficient 89 Diodes Under Reverse Bias 89 3.6.1 Saturation Current in Real Diodes 90 3.6.2 Reverse Breakdown 91 3.6.3 Diode Model for the Breakdown Region 92 pn Junction Capacitance 92 3.7.1 Reverse Bias 92 3.7.2 Forward Bias 93 Schottky Barrier Diode 93 Diode SPICE Model and Layout 94 Diode Circuit Analysis 96 3.10.1 Load-Line Analysis 96 3.10.2 Analysis Using the Mathematical Model for the Diode 98 3.10.3 The Ideal Diode Model 102 3.10.4 Constant Voltage Drop Model 104 3.10.5 Model Comparison and Discussion 105 Multiple-Diode Circuits 106 Analysis of Diodes Operating in the Breakdown Region 109 3.12.1 Load-Line Analysis 109 3.12.2 Analysis with the Piecewise Linear Model 109 3.12.3 Voltage Regulation 110 3.12.4 Analysis Including Zener Resistance 111 3.12.5 Line and Load Regulation 112 Half-Wave Rectifier Circuits 113 3.13.1 Half-Wave Rectifier with Resistor Load 113 3.13.2 Rectifier Filter Capacitor 114 3.13.3 Half-Wave Rectifier with RC Load 115 3.13.4 Ripple Voltage and Conduction Interval 116 3.13.5 Diode Current 118 3.13.6 Surge Current 120 3.13.7 Peak-Inverse-Voltage (PIV) Rating 120 3.13.8 Diode Power Dissipation 120 3.13.9 Half-Wave Rectifier with Negative Output Voltage 121 3.14 3.15 3.16 3.17 3.18 Full-Wave Rectifier Circuits 123 3.14.1 Full-Wave Rectifier with Negative Output Voltage 124 Full-Wave Bridge Rectification 125 Rectifier Comparison and Design Tradeoffs 125 Dynamic Switching Behavior of the Diode 129 Photo Diodes, Solar Cells, and Light-Emitting Diodes 130 3.18.1 Photo Diodes and Photodetectors 130 3.18.2 Power Generation from Solar Cells 131 3.18.3 Light-Emitting Diodes (LEDs) 132 Summary 133 Key Terms 134 Reference 135 Additional Reading 135 Problems 135 CHAPTER FIELD-EFFECT TRANSISTORS 145 4.1 4.2 4.3 4.4 4.5 4.6 Characteristics of the MOS Capacitor 146 4.1.1 Accumulation Region 147 4.1.2 Depletion Region 148 4.1.3 Inversion Region 148 The NMOS Transistor 148 Qualitative i -v Behavior of the 4.2.1 NMOS Transistor 149 4.2.2 Triode Region Characteristics of the NMOS Transistor 150 4.2.3 On Resistance 153 4.2.4 Saturation of the i -v Characteristics 154 4.2.5 Mathematical Model in the Saturation (Pinch-Off) Region 155 4.2.6 Transconductance 157 4.2.7 Channel-Length Modulation 157 4.2.8 Transfer Characteristics and Depletion-Mode MOSFETS 158 4.2.9 Body Effect or Substrate Sensitivity 159 PMOS Transistors 161 MOSFET Circuit Symbols 163 Capacitances in MOS Transistors 165 4.5.1 NMOS Transistor Capacitances in the Triode Region 165 4.5.2 Capacitances in the Saturation Region 166 4.5.3 Capacitances in Cutoff 166 MOSFET Modeling in SPICE 167 Jaeger-1820037 jae80458˙FM˙i-xxvi January 22, 2010 15:50 Contents 4.7 4.8 4.9 4.10 4.11 4.12 4.13 MOS Transistor Scaling 169 Drain Current 169 4.7.1 4.7.2 Gate Capacitance 169 4.7.3 Circuit and Power Densities 170 4.7.4 Power-Delay Product 170 4.7.5 Cutoff Frequency 171 4.7.6 High Field Limitations 171 4.7.7 Subthreshold Conduction 172 MOS Transistor Fabrication and Layout Design Rules 172 4.8.1 Minimum Feature Size and Alignment Tolerance 173 4.8.2 MOS Transistor Layout 173 Biasing the NMOS Field-Effect Transistor 176 4.9.1 Why Do We Need Bias? 176 4.9.2 Constant Gate-Source Voltage Bias 178 4.9.3 Load Line Analysis for the Q-Point 181 4.9.4 Four-Resistor Biasing 182 Biasing the PMOS Field-Effect Transistor 188 The Junction Field-Effect Transistor (JFET) 190 4.11.1 The JFET with Bias Applied 191 4.11.2 JFET Channel with Drain-Source Bias 191 4.11.3 n-Channel JFET i -v Characteristics 193 4.11.4 The p-Channel JFET 195 4.11.5 Circuit Symbols and JFET Model Summary 195 4.11.6 JFET Capacitances 196 JFET Modeling in SPICE 197 Biasing the JFET and Depletion-Mode MOSFET 198 Summary 200 Key Terms 202 References 203 Problems 204 5.3 5.4 5.5 5.6 5.7 5.8 5.9 5.10 5.11 CHAPTER BIPOLAR JUNCTION TRANSISTORS 217 5.1 5.2 Physical Structure of the Bipolar Transistor 218 The Transport Model for the npn Transistor 219 5.2.1 Forward Characteristics 220 5.2.2 Reverse Characteristics 222 5.2.3 The Complete Transport Model Equations for Arbitrary Bias Conditions 223 5.12 The pnp Transistor 225 Equivalent Circuit Representations for the Transport Models 227 The i-v Characteristics of the Bipolar Transistor 228 5.5.1 Output Characteristics 228 5.5.2 Transfer Characteristics 229 The Operating Regions of the Bipolar Transistor 230 Transport Model Simplifications 231 5.7.1 Simplified Model for the Cutoff Region 231 5.7.2 Model Simplifications for the Forward-Active Region 233 5.7.3 Diodes in Bipolar Integrated Circuits 239 5.7.4 Simplified Model for the Reverse-Active Region 240 5.7.5 Modeling Operation in the Saturation Region 242 Nonideal Behavior of the Bipolar Transistor 245 5.8.1 Junction Breakdown Voltages 246 5.8.2 Minority-Carrier Transport in the Base Region 246 5.8.3 Base Transit Time 247 5.8.4 Diffusion Capacitance 249 5.8.5 Frequency Dependence of the Common-Emitter Current Gain 250 5.8.6 The Early Effect and Early Voltage 250 Modeling the Early Effect 251 5.8.7 5.8.8 Origin of the Early Effect 251 Transconductance 252 Bipolar Technology and SPICE Model 253 5.10.1 Qualitative Description 253 5.10.2 SPICE Model Equations 254 5.10.3 High-Performance Bipolar Transistors 255 Practical Bias Circuits for the BJT 256 5.11.1 Four-Resistor Bias Network 258 5.11.2 Design Objectives for the Four-Resistor Bias Network 260 5.11.3 Iterative Analysis of the Four-Resistor Bias Circuit 266 Tolerances in Bias Circuits 266 5.12.1 Worst-Case Analysis 267 5.12.2 Monte Carlo Analysis 269 Summary 272 Key Terms 274 References 274 Problems 275 ix Jaeger-1820037 book January 16, 2010 15:55 16.9 The A741 Operational Amplifier 1097 supply Under the conditions shown, the base-emitter junction of Q will be forward-biased, and that of Q reverse-biased by a voltage of (VCC + VE E − VB E1 ) If VCC = VE E = 22 V, the reverse voltage exceeds 41 V Because of heavy doping in the emitter, the typical Zener breakdown voltage of the base-emitter junction of an npn transistor is only to V Thus, any voltage exceeding this value by more than one diode drop may destroy at least one of the transistors in the differential input pair Early IC op amps required circuit designers to add external diode protection across the input terminals, as shown Fig 16.45(b) The diodes prevent the differential input voltage from exceeding approximately 1.4 V, but this technique adds extra components and cost to the design The two resistors limit the current through the diodes The A741 described in the next section was the first commercial IC op amp to solve this problem by providing a fully protected input, as well as output, stage 16.9 THE  A741 OPERATIONAL AMPLIFIER The now classic Fairchild A741 operational-amplifier design was the first to provide a highly robust amplifier from the application engineer’s point of view The amplifier provides excellent overall characteristics (high gain, input resistance and CMRR, low output resistance, and good frequency response) while providing overvoltage protection for the input stage and short-circuit current limiting of the output stage The 741 style of amplifier design quickly became the industry standard and spawned many related designs By studying the 741 design, we will find a number of new amplifier circuit design and bias techniques 16.9.1 OVERALL CIRCUIT OPERATION Figure 16.46 is a simplified schematic of the A741 operational amplifier The three bias sources shown in symbolic form are discussed in more detail following a description of the overall circuit The op amp has two stages of voltage gain followed by a class-AB output stage In the first stage, transistors Q to Q form a differential amplifier with a buffered current mirror active load, Q to Q VCC Q8 I3 I2 220 μA 670 μA Q9 Q15 Q17 Q1 Q14 I1 18 μ A R1 VCC VCC Q7 Q10 kΩ 50 kΩ 22 Ω R4 R2 50 kΩ kΩ 40 kΩ Q16 Q12 Q11 Q6 R3 R8 Q18 R6 Q4 Q5 27 Ω Q13 Q2 Q3 R7 R5 100 Ω – VEE = –15 V REXT Input stage Second stage Output stage Figure 16.46 Overall schematic of the classic Fairchild A741 operational amplifier (the bias network appears in Fig 16.47) Jaeger-1820037 1098 book January 16, 2010 15:55 Chapter 16 Analog Integrated Circuit Design Techniques The second stage consists of emitter follower Q 10 driving common-emitter amplifier Q 11 with current source I2 and emitter-follower Q 12 as load Transistors Q 13 to Q 18 form a short-circuit protected class-AB push-pull output stage that is buffered from the second gain stage by Q 12 Practical operational amplifiers offer an offset voltage adjustment port, which is provided in the 741 through the addition of 1-k resistors R1 and R2 and an external potentiometer REXT Exercise: Reread this section and be sure you understand the function of each individual transistor in Fig 16.46 Make a table listing the function of each transistor 16.9.2 BIAS CIRCUITRY The three current sources shown symbolically in Fig 16.46 are generated by the bias circuitry in Fig 16.47 The value of the current in the two diode-connected reference transistors Q 20 and Q 22 is determined by the power supply voltage and resistor R5 : VCC + VE E − 2VB E 15 + 15 − 1.4 = 0.733 mA (16.98) = R5 39 k assuming ±15-V supplies Current I1 is derived from the Widlar source formed of Q 20 and Q 21 The output current for this design is IREF VT I1 = ln (16.99) 5000 I1 IREF = Using the reference current calculated in Eq (16.98) and iteratively solving for I1 in Eq (16.99) yields I1 = 18.4 A The currents in mirror transistors Q 23 and Q 24 are related to the reference current IREF by their emitter areas using Eq (16.13) Assuming VO = and VCC = 15 V, and neglecting the voltage drop across R7 and R8 in Fig 16.46, VEC23 = 15 + 1.4 = 16.4 V and VEC24 = 15 − 0.7 = 14.3 V Using these values with β F = 50 and V A = 60 V, the two source currents are 16.4 V 60 V = 666 A I2 = 0.75(733 A) 0.7 V + 1+ 60 V 50 14.4 V 1+ 60 V I3 = 0.25(733 A) = 216 A 0.7 V + 1+ 60 V 50 and the two output resistances are V A23 + VEC23 60 V + 16.4 V R2 = = = 115 k I2 0.666 mA 1+ V A24 + VEC24 60 V + 14.3 V = = 344 k R3 = I3 0.216 mA (16.100) (16.101) Exercise: What are the values of I REF , I , I , and I in the circuit in Fig 16.47 for VCC = VE E = 22 V? Answers: 1.09 mA, 20.0 A, 1.08 mA, 351 A Exercise: What is the output resistance of the Widlar source in Fig 16.47 operating at 18.4 A for V A = 60 V and VE E = 15 V? Answer: 18.8 M Jaeger-1820037 book January 16, 2010 15:55 16.9 The A741 Operational Amplifier 1099 VCC Q8 A Q22 IREF 0.75 A R5 −1.4 V 39 kΩ −1.4 V +VCC 0.25 A Q23 I2 IC8 Q9 v1 A A IC2 Q1 Q2 Q3 Q24 I3 +0.7 V IC3 I1 IC4 Q7 IC6 IC5 Q5 Q21 v2 Q4 2IB4 I1 Q20 IC1 vO Q6 R1 R3 R2 kΩ kΩ −VEE Figure 16.47 741 bias circuitry with voltages corresponding to VO = V kΩ –VEE 50 kΩ Figure 16.48 A741 input stage 16.9.3 dc ANALYSIS OF THE 741 INPUT STAGE The input stage of the A741 amplifier is redrawn in the schematic in Fig 16.48 As noted earlier, Q , Q , Q , and Q form a differential input stage with an active load consisting of the buffered current mirror formed by Q , Q , and Q In this input stage, there are four base-emitter junctions between inputs v1 and v2 , two from the npn transistors and, more importantly, two from the pnp transistors Therefore, (v1 − v2 ) = (VB E1 + VE B3 − VE B4 − VB E2 ) In standard bipolar IC processes, pnp transistors are formed from lateral structures in which both junctions exhibit breakdown voltages equal to that of the collector-base junction of the npn transistor This breakdown voltage typically exceeds 50 V Because most general-purpose op amp specifications limit the power supply voltages to less than ±22 V, the emitter-base junctions of Q and Q provide sufficient breakdown voltage to fully protect the input stage of the amplifier, even under a worst-case fault condition, such as that depicted in Fig 16.45(a) Q-Point Analysis In the 741 input stage in Fig 16.48, the current mirror formed by transistors Q and Q operates with transistors Q to Q to establish the bias currents for the input stage Bias current I1 represents the output of the Widlar source discussed previously (18 A) and must be equal to the collector current of Q plus the base currents of matched transistors Q and Q : I1 = IC8 + I B3 + I B4 = IC8 + 2I B4 (16.102) ∼ I1 For high current gain, the base currents are small and IC8 = The collector current of Q mirrors the collector currents of Q and Q , which are summed together in mirror reference transistor Q Assuming high current gain and ignoring the collectorvoltage mismatch between Q and Q , IC8 = IC1 + IC2 = 2IC2 (16.103) Jaeger-1820037 1100 book January 16, 2010 15:55 Chapter 16 Analog Integrated Circuit Design Techniques Combining Eqs (16.102) and (16.103) yields the ideal bias relationships for the input stage I1 IC1 = IC2 ∼ = and I1 IC3 = IC4 ∼ = (16.104) because the emitter currents of Q and Q and Q and Q must be equal The collector current of Q establishes a current equal to I1 /2 in current mirror transistors Q and Q Thus, transistors Q to Q all operate at a nominal collector current equal to one-half the value of source I1 Now that we understand the basic ideas behind the input stage bias circuit, let us perform a more exact analysis Expanding Eq (16.102) using the current mirror expression from Eq (16.13), VEC8 V A8 + 2I B4 I1 = 2IC2 VE B8 1+ + β F O8 V A8 1+ (16.105) IC2 is related to I B4 through the current gains of Q and Q : IC2 = α F2 I E2 = α F2 (β F O4 + 1)I B4 = β F O2 (β F O4 + 1)I B4 β F O2 + Combining Eqs (16.105) and (16.106), and solving for IC2 yields ⎡ ⎤−1 VEC8 + ⎥ I1 ⎢ V A8 ⎥ IC1 = + ×⎢ ⎦ β F O2 VE B8 ⎣ (β F O4 + 1) 1+ + β + β F O8 V A8 F O2 (16.106) (16.107) which is equal to the ideal value of I1 /2 but reduced by the nonideal current mirror effects from finite current gain and Early voltage The emitter current of Q must equal the emitter current of Q , and so the collector current of Q is IC4 = α F4 I E4 = α F4 IC2 β F O4 β F O2 + = IC2 α F2 β F O4 + β F O2 (16.108) The use of buffer transistor Q essentially eliminates the current gain defect in the current mirror Note from the full amplifier circuit in Fig 16.46 that the base current of transistor Q 10 , with its 50-k emitter resistor R4 , is designed to be approximately equal to the base current of Q , and VC E6 ∼ = VC E5 as well Thus, the current mirror ratio is quite accurate and IC5 = IC6 = IC3 ∼ = I1 /2 If 50-k resistor R3 were omitted, then the emitter current of Q would be equal only to the sum of the base currents of transistors Q and Q and would be quite small Because of the Q-point dependence of β F , the current gain of Q would be poor R3 increases the operating current of Q to improve its current gain, as well as to improve the dc balance and transient response of the amplifier The value of R3 is chosen to approximately match I B7 to I B10 To complete the Q-point analysis, the various collector-emitter voltages must be determined The collectors of Q and Q are one VE B below the positive power supply, whereas the emitters are one VB E below ground potential Hence, VC E1 = VC E2 = VCC − VE B9 + VB E2 ∼ = VCC (16.109) The collector and emitter of Q are approximately 2VB E above the negative power supply voltage and one VB E below ground, respectively: VEC3 = VE3 − VC3 = −0.7 V − (−VE E + 1.4 V) = VE E − 2.1 V (16.110) Jaeger-1820037 book January 16, 2010 15:55 16.9 The A741 Operational Amplifier 1101 The buffered current mirror effectively minimizes the error due to the finite current gain of the transistors, and VC E6 = VC E5 ∼ = 2VB E = 1.4 V, neglecting the small voltage drop (