PowerPoint Presentation TRƯỜNG ĐẠI HỌC BÁCH KHOA TPHCM KHOA ĐIỆN – ĐIỆN TỬ * BÁO CÁO ĐỀ TÀI THIẾT KẾ CPU 8 BIT (LC3b) GVHD Trần Hoàng Linh NHÓM Thành viên Lê Tiến Khải 1411783 Lê Huỳnh Thiện Nhân 1412[.]
TRƯỜNG ĐẠI HỌC BÁCH KHOA TPHCM KHOA ĐIỆN – ĐIỆN TỬ * _ BÁO CÁO ĐỀ TÀI THIẾT KẾ CPU BIT (LC3b) GVHD : Trần Hoàng Linh NHÓM Thành viên: Lê Tiến Khải 1411783 Lê Huỳnh Thiện Nhân 1412606 Nguyễn Thanh Nhân1412628 SƠ ĐỒ KHỐI 16 GatePC 16 GateMARMUX 16 LD.REG selMAR LD.MAR MARMUX PC selPC DR SR2 REG FILE 16 LD.PC clk rst clk clk rst SR1 rst selEAB1 16 SR2 out SR1 out LD.MDR MEMORY memWE selMDR selEAB2 11 16 EAB 16 16 B 16 IR LD.IR clk rst 16 N Z P ALUK A ALU clk rst SHF NZP GateMDR LD.CC 16 GateALU GateSHF SƠ ĐỒ CHI TIẾT GatePC GateMARMUX MAR LD.MAR 16 16 LD.PC MARMUX PC +2 PCMUX 16 111 IR[11:9] 16 WE ZEXT &LSHF1 + ADDR1MUX SR2 OUT ADDR2MUX 16 [10:0] MEMORY DR SR2 LSHF1 [7:0] DRMUX REG FILE LD.REG 16 16 16 16 16 SR1 OUT 16 SR1 SR1MUX 16 IR[8:6] IR[11:9] 16 16 SEXT [8:0] SEXT LD.MDR LD.PC LD.REG GateALU [5:0] SEXT [4:0] SEXT CONTROL ALUK 16 LD.MDR MDR 16 LD.IR MIO.EN 16 B IR MDRMUX SR2MUX IR[5] N Z P LOGIC 16 SHF ALU LD.CC IR[5:0] A GateMDR GateALU 16 GateSHF 16 LƯU ĐỒ TRẠNG THÁI 0 DR SR1 00 SR2 ADD GatePC GateMARMUX MAR LD.MAR 16 16 LD.PC MARMUX PC +2 PCMUX 16 111 IR[11:9] 16 01 ZEXT &LSHF1 WE + ADDR1MUX 16 [10:0] DR SR2 OUT ADDR2MUX 16 16 16 16 16 MEMORY SR2 LSHF1 [7:0] DRMUX REG FILE LD.REG SR1 OUT 16 SR1 SR1MUX 16 IR[8:6] IR[11:9] 16 16 SEXT [8:0] LD.MAR SEXT LD.MDR LD.PC LD.REG GateALU [5:0] SEXT [4:0] SEXT CONTROL ALUK LD.IR 16 SR2MUX IR[5] MIO.EN 16 LD.MDR MDR 16 00 IR MDRMUX N Z P LOGIC 16 LD.CC LD.CC B IR[5:0] A ALU SHF GateMDR GateALU 16 GateSHF 16 0 DR SR1 imm5 ADD GatePC GateMARMUX MAR LD.MAR 16 16 LD.PC MARMUX PC +2 PCMUX 16 111 IR[11:9] 16 01 ZEXT &LSHF1 WE + ADDR1MUX 16 [10:0] DR SR2 OUT ADDR2MUX 16 16 16 16 16 MEMORY SR2 LSHF1 [7:0] DRMUX REG FILE LD.REG SR1 OUT 16 SR1 SR1MUX 16 IR[8:6] IR[11:9] 16 16 SEXT [8:0] LD.MAR SEXT LD.MDR LD.PC LD.REG GateALU [5:0] SEXT [4:0] SEXT CONTROL ALUK LD.IR 16 SR2MUX IR[5] MIO.EN 16 LD.MDR MDR 16 00 IR MDRMUX N Z P LOGIC 16 LD.CC LD.CC B IR[5:0] A ALU SHF GateMDR GateALU 16 GateSHF 16 1 DR SR1 00 SR2 AND GatePC GateMARMUX MAR LD.MAR 16 16 LD.PC MARMUX PC +2 PCMUX 16 111 IR[11:9] 16 01 ZEXT &LSHF1 WE + ADDR1MUX 16 [10:0] DR SR2 OUT ADDR2MUX 16 16 16 16 16 MEMORY SR2 LSHF1 [7:0] DRMUX REG FILE LD.REG SR1 OUT 16 SR1 SR1MUX 16 IR[8:6] IR[11:9] 16 16 SEXT [8:0] LD.MAR SEXT LD.MDR LD.PC LD.REG GateALU [5:0] SEXT [4:0] SEXT CONTROL ALUK LD.IR 16 SR2MUX IR[5] MIO.EN 16 LD.MDR MDR 16 11 IR MDRMUX N Z P LOGIC 16 LD.CC LD.CC B IR[5:0] A ALU SHF GateMDR GateALU 16 GateSHF 16 1 DR SR1 imm5 AND GatePC GateMARMUX MAR LD.MAR 16 16 LD.PC MARMUX PC +2 PCMUX 16 111 IR[11:9] 16 01 ZEXT &LSHF1 WE + ADDR1MUX 16 [10:0] DR SR2 OUT ADDR2MUX 16 16 16 16 16 MEMORY SR2 LSHF1 [7:0] DRMUX REG FILE LD.REG SR1 OUT 16 SR1 SR1MUX 16 IR[8:6] IR[11:9] 16 16 SEXT [8:0] LD.MAR SEXT LD.MDR LD.PC LD.REG GateALU [5:0] SEXT [4:0] SEXT CONTROL ALUK LD.IR 16 SR2MUX IR[5] MIO.EN 16 LD.MDR MDR 16 11 IR MDRMUX N Z P LOGIC 16 LD.CC LD.CC B IR[5:0] A ALU SHF GateMDR GateALU 16 GateSHF 16 0 DR SR1 11111 NOT GatePC GateMARMUX MAR LD.MAR 16 16 LD.PC MARMUX PC +2 PCMUX 16 111 IR[11:9] 16 01 ZEXT &LSHF1 WE + ADDR1MUX 16 [10:0] DR SR2 OUT ADDR2MUX 16 16 16 16 16 MEMORY SR2 LSHF1 [7:0] DRMUX REG FILE LD.REG SR1 OUT 16 SR1 SR1MUX 16 IR[8:6] IR[11:9] 16 16 SEXT [8:0] LD.MAR SEXT LD.MDR LD.PC LD.REG GateALU [5:0] SEXT [4:0] SEXT CONTROL ALUK LD.IR 16 SR2MUX IR[5] MIO.EN 16 LD.MDR MDR 16 10 IR MDRMUX N Z P LOGIC 16 LD.CC LD.CC B IR[5:0] A ALU SHF GateMDR GateALU 16 GateSHF 16 1 DR PCoffset9 LEA GateMARMUX GatePC MAR LD.MAR 16 16 LD.PC MARMUX PC +2 PCMUX 16 111 IR[11:9] 16 01 ZEXT &LSHF1 WE + ADDR1MUX 10 16 [10:0] DR SR2 OUT ADDR2MUX 16 16 16 16 16 MEMORY SR2 LSHF1 [7:0] DRMUX REG FILE LD.REG SR1 OUT 16 SR1 SR1MUX 16 IR[8:6] IR[11:9] 16 16 SEXT [8:0] LD.MAR SEXT LD.MDR LD.PC LD.REG GateALU [5:0] SEXT [4:0] SEXT CONTROL ALUK MDRMUX SR2MUX IR[5] MIO.EN 16 MDR 16 B LD.IR IR 16 LD.MDR N Z P LOGIC 16 LD.CC LD.CC IR[5:0] A ALU SHF GateMDR GateALU 16 GateSHF 16 1 DR BaseR offset6 LDR GateMARMUX GatePC MAR LD.MAR 16 16 LD.PC MARMUX PC +2 PCMUX 16 111 IR[11:9] 16 01 ZEXT &LSHF1 WE + ADDR1MUX ADDR2MUX 01 16 [10:0] DR SR2 OUT 16 16 16 16 16 SR1 OUT 16 SR1 SR1MUX 16 16 IR[8:6] LD.MAR SEXT LD.MDR LD.PC LD.REG GateALU [5:0] SEXT [4:0] 16 IR[8:6] IR[11:9] SEXT [8:0] MEMORY SR2 LSHF1 [7:0] DRMUX REG FILE LD.REG SEXT CONTROL ALUK MDRMUX SR2MUX IR[5] MIO.EN 16 MDR 16 B LD.IR IR 16 LD.MDR N Z P LOGIC 16 LD.CC LD.CC IR[5:0] A ALU SHF GateMDR GateALU 16 GateSHF 16 1 SR BaseR offset6 STR GateMARMUX GatePC MAR LD.MAR 16 16 LD.PC MARMUX PC +2 PCMUX 16 111 IR[11:9] 16 01 ZEXT &LSHF1 + ADDR2MUX [10:0] DR SR2 OUT 16 16 16 16 16 MEMORY SR2 ADDR1MUX 01 16 DRMUX REG FILE LD.REG LSHF1 [7:0] 11 WE SR1 OUT 16 SR1 SR1MUX 16 IR[8:6] IR[11:9] 16 16 SEXT [8:0] LD.MAR SEXT LD.MDR LD.PC LD.REG GateALU [5:0] SEXT [4:0] SEXT CONTROL ALUK LD.IR 16 SR2MUX IR[5] MIO.EN 16 LD.MDR MDR 16 01 IR MDRMUX N Z P LOGIC 16 LD.CC B IR[5:0] A ALU SHF GateMDR GateALU 16 GateSHF 16 1 0 000 BaseR 000000 JMP GatePC GateMARMUX MAR LD.MAR 16 16 LD.PC MARMUX PC +2 PCMUX 16 111 11 16 IR[11:9] WE 11 ZEXT &LSHF1 + ADDR1MUX 16 [10:0] DR SR2 OUT ADDR2MUX 16 16 16 16 16 SR1 OUT 16 SR1 SR1MUX SEXT [4:0] IR[8:6] LD.MDR LD.PC LD.REG GateALU [5:0] SEXT CONTROL ALUK LD.IR 16 SR2MUX IR[5] N Z P LOGIC 16 LD.CC MDRMUX MIO.EN 16 LD.MDR MDR 16 01 IR 16 16 LD.MAR SEXT 16 IR[8:6] IR[11:9] SEXT [8:0] MEMORY SR2 LSHF1 [7:0] DRMUX REG FILE LD.REG B IR[5:0] A ALU SHF GateMDR GateALU 16 GateSHF 16 0 JSR 00 BaseR 000000 GatePC GateMARMUX MAR LD.MAR 16 16 LD.PC MARMUX PC +2 PCMUX 16 111 11 16 IR[11:9] 01 ZEXT &LSHF1 WE + ADDR1MUX 16 [10:0] DR SR2 OUT ADDR2MUX 16 16 16 16 16 MEMORY SR2 LSHF1 [7:0] DRMUX REG FILE LD.REG SR1 OUT 16 SR1 SR1MUX 16 IR[8:6] IR[11:9] 16 16 SEXT [8:0] LD.MAR SEXT LD.MDR LD.PC LD.REG GateALU IR[11] = [5:0] SEXT [4:0] SEXT CONTROL ALUK LD.IR 16 SR2MUX IR[5] MIO.EN 16 LD.MDR MDR 16 01 IR MDRMUX N Z P LOGIC 16 LD.CC B IR[5:0] A SHF ALU GateMDR GateALU 16 GateSHF 16 0 PCoffset11 JSRR GatePC GateMARMUX MAR LD.MAR 16 16 LD.PC MARMUX PC +2 PCMUX 16 111 IR[11:9] 16 01 ZEXT &LSHF1 WE 10 + ADDR1MUX 11 16 [10:0] [10:0] DR SR2 OUT ADDR2MUX 16 16 16 16 16 MEMORY SR2 LSHF1 [7:0] DRMUX REG FILE LD.REG SR1 OUT 16 SR1 SR1MUX 16 IR[8:6] IR[11:9] 16 16 SEXT [8:0] LD.MAR SEXT LD.MDR LD.PC LD.REG GateALU IR[11] = [5:0] SEXT [4:0] SEXT CONTROL ALUK MDRMUX SR2MUX IR[5] MIO.EN 16 MDR 16 B LD.IR IR 16 LD.MDR N Z P LOGIC 16 LD.CC IR[5:0] A ALU SHF GateMDR GateALU 16 GateSHF 16 0 0 n z p PCoffset9 BR GatePC GateMARMUX GateMARMUX 16 16 LD.PC MARMUX 16 MAR 16 LD.MAR PC +2 PCMUX 11 111 IR[11:9] 01 ZEXT &LSHF1 WE + ADDR1MUX ADDR2MUX 11 16 [10:0] DR 16 16 SR2 OUT 16 16 16 MEMORY SR2 LSHF1 [7:0] DRMUX REG FILE LD.REG SR1 OUT 16 SR1 SR1MUX 16 IR[8:6] IR[11:9] 16 16 SEXT [8:0] LD.MAR SEXT BEN = [5:0] SEXT [4:0] SEXT CONTROL ALUK MDRMUX SR2MUX IR[5] MIO.EN 16 MDR 16 B LD.IR IR 16 LD.MDR N Z P LOGIC 16 LD.CC IR[5:0] A ALU SHF GateMDR GateALU 16 GateSHF 16 1 1 0000 trapvect8 TRAP GatePC GateMARMUX GateMARMUX 16 16 LD.PC MARMUX MAR PC +2 PCMUX 16 111 01 11 WE + DR SR2 OUT ADDR2MUX 16 16 16 16 16 MEMORY SR2 ADDR1MUX 16 DRMUX REG FILE LD.REG LSHF1 [7:0] IR[11:9] 16 ZEXT &LSHF1 [10:0] LD.MAR SR1 OUT 16 SR1 SR1MUX 16 IR[8:6] IR[11:9] 16 16 SEXT [8:0] LD.MAR SEXT LD.MDR LD.PC LD.REG GateALU [5:0] SEXT [4:0] SEXT CONTROL ALUK MDRMUX SR2MUX IR[5] MIO.EN 16 MDR 16 B LD.IR IR 16 LD.MDR N Z P LOGIC 16 LD.CC IR[5:0] A ALU SHF GateMDR GateALU 16 GateSHF 16