UVM Verification of an I2C Master Core

Rochester Institute of Technology RIT Scholar Works Theses 5-2019 UVM Verification of an I2C Master Core Shravani Balaraju sxb5692@rit.edu Follow this and additional works at: https://scholarworks.rit.edu/theses Recommended Citation Balaraju, Shravani, "UVM Verification of an I2C Master Core" (2019) Thesis Rochester Institute of Technology Accessed from This Master's Project is brought to you for free and open access by RIT Scholar Works It has been accepted for inclusion in Theses by an authorized administrator of RIT Scholar Works For more information, please contact ritscholarworks@rit.edu UVM VERIFICATION OF AN I2C M ASTER C ORE by Shravani Balaraju G RADUATE PAPER Submitted in partial fulfillment of the requirements for the degree of M ASTER OF S CIENCE in Electrical Engineering Approved by: Mr Mark A Indovina, Lecturer Graduate Research Advisor, Department of Electrical and Microelectronic Engineering Dr Sohail A Dianat, Professor Department Head, Department of Electrical and Microelectronic Engineering D EPARTMENT OF E LECTRICAL AND M ICROELECTRONIC E NGINEERING K ATE G LEASON C OLLEGE OF E NGINEERING ROCHESTER I NSTITUTE OF T ECHNOLOGY ROCHESTER , N EW YORK M AY, 2019 I dedicate this work to my mother Gouri Manthena, my father Dhananjaya Raju, my grandmother Siromani Manthena, my grandfather Narasa Raju, my partner Karthik Pythireddi, my best friend Veenadhari Polkam and my colleagues for their love and support during my thesis Declaration I hereby declare that except where specific reference is made to the work of others, that all content of this Graduate Paper are original and have not been submitted in whole or in part for consideration for any other degree or qualification in this, or any other University This Graduate Project is the result of my own work and includes nothing which is the outcome of work done in collaboration, except where specifically indicated in the text Shravani Balaraju May, 2019 Acknowledgements I would like to thank my advisor Professor Mark A Indovina for his support, guidance, feedback, and encouragement which helped in the successful completion of my graduate research Abstract With the increasing complexity of IP designs, verification has become quite popular yet is still a significant challenge for a verification engineer A proper verification environment can bring out bugs that one may never expect in the design On the contrary, a poorly designed verification environment could give false information about the functioning of the design and bugs may appear on the consumer’s end Hence, the verification industry is continually looking for more efficient verification methodologies This paper describes one such efficient methodology implemented on an Inter-Integrated Circuit (I2C) system I2C packs in itself the powerful features of the Serial Peripheral Interface (SPI) and the universal asynchronous receiver-transmitter (UART), but is comparatively more efficient and uses less hardware for implementation Also, it can establish secure communication between multiple masters and multiple slaves with minimal wiring In this project, from a design perspective, the master is a hardware block, and the slave is a verification IP The methodology used for verification is based on the Universal Verification Methodology (UVM), a class library written in the SystemVerilog language The paper describes how the verification of an I2C system uses the powerful tools of UVM The master core has been successfully verified and the coverage goals are met The effort has been documented in this paper in detail Contents Contents v List of Figures x List of Tables xii Introduction 1.1 Research Goals 1.2 Contributions 1.3 Organization Bibliographical Research 2.1 A brief history of Verification 2.2 Design and Verification Challenges 2.3 Verification Methodologies 2.4 Functional Coverage and Assertions 2.4.1 Different coverage metrics 2.4.1.1 Code Coverage 2.4.1.2 Functional Coverage Assertions 2.4.2 vi Contents 2.4.2.1 Immediate Assertions 10 2.4.2.2 Concurrent assertions 10 UVM Verification Hierarchy 11 3.1 UVM Environment 11 3.1.1 UVM Agent 12 3.1.1.1 UVM sequence item 12 3.1.1.2 UVM sequence 12 3.1.1.3 UVM sequencer 13 3.1.1.4 UVM driver 13 3.1.1.5 UVM Monitor 13 3.1.2 UVM Scoreboard 13 3.1.3 UVM Phasing 14 3.1.3.1 Build 14 3.1.3.2 Run 14 3.1.3.3 Cleanup 15 3.2 UVM Test 15 3.3 UVM Test bench 16 3.4 UVM Debugging 16 I2C Overview 18 4.1 A brief history of I2C 19 4.1.1 Advantages 20 I2C Protocol 20 4.2.1 Generation of START signal 21 4.2.2 Transfer of data 22 4.2 vii Contents 4.2.3 4.3 Generation of STOP signal 22 I2C Master Core 23 4.3.1 23 Design Features I2C Detail Design 25 5.1 Wishbone Interface Signals 25 5.2 Register Model 25 5.3 Register Description 27 5.3.1 Control Register 27 5.3.2 Transmit Register 27 5.3.3 Receive Register 28 5.3.4 Command Register 28 5.3.5 Status Register 28 I2C Verification components 30 6.1 I2C Interface 30 6.1.1 Master Interface 30 6.1.2 Wishbone signals 32 6.2 I2C Agent 32 6.3 I2C Sequences 32 6.3.1 I2C data transaction 32 6.3.2 Low and mid traffic sequences 33 6.3.3 Data sequence 33 I2C Wishbone BFM 33 6.4.1 Working of the BFM 33 6.4.2 Tasks in the BFM 34 6.4 viii Contents 6.4.2.1 Reset task 34 6.4.2.2 Write task 34 6.4.2.3 Read task 34 6.5 I2C Driver & Monitor 35 6.6 I2C Scoreboard 35 6.7 I2C Environment 35 6.8 I2C Test 36 6.9 I2C Top 36 Results and Discussion 37 7.1 RTL and Gate level Simulations 37 7.2 Simulation time dependence on transaction count 39 7.3 Measure of randomization effectiveness 39 7.4 UVM features for debugging 43 7.5 Observations 44 Conclusion 46 8.1 46 Future Work References 48 I Source Code I-1 I.1 Interface I-1 I.2 Sequence Item I-3 I.3 Sequencer I-7 I.4 Driver I-14 I.5 Monitor I-30 I-65 I.11 Slave 202 203 if ( read_write ) begin 204 #3 m e m o r y _ d a t a _ o u t