UVM Verification of a Floating Point Multiplier

Rochester Institute of Technology RIT Scholar Works Theses 12-2019 UVM Verification of a Floating Point Multiplier Nicholas J Marsaw njm3706@rit.edu Follow this and additional works at: https://scholarworks.rit.edu/theses Recommended Citation Marsaw, Nicholas J., "UVM Verification of a Floating Point Multiplier" (2019) Thesis Rochester Institute of Technology Accessed from This Master's Project is brought to you for free and open access by RIT Scholar Works It has been accepted for inclusion in Theses by an authorized administrator of RIT Scholar Works For more information, please contact ritscholarworks@rit.edu UVM VERIFICATION OF A F LOATING P OINT M ULTIPLIER by Nicholas J Marsaw G RADUATE PAPER Submitted in partial fulfillment of the requirements for the degree of M ASTER OF S CIENCE in Electrical Engineering Approved by: Mr Mark A Indovina, Senior Lecturer Graduate Research Advisor, Department of Electrical and Microelectronic Engineering Dr Sohail A Dianat, Professor Department Head, Department of Electrical and Microelectronic Engineering D EPARTMENT OF E LECTRICAL AND M ICROELECTRONIC E NGINEERING K ATE G LEASON C OLLEGE OF E NGINEERING ROCHESTER I NSTITUTE OF T ECHNOLOGY ROCHESTER , N EW YORK D ECEMBER , 2019 I dedicate this work to my elementary school teacher Darrel Dupra, who passed away in 2010 He took time to encourage me to think critically and to enjoy the journey as I progressed throughout my academics, and played a crucial role in my pursuit of Electrical Engineering Declaration I hereby declare that except where specific reference is made to the work of others, that all contents of this Graduate Paper are original and have not been submitted in whole or in part for consideration for any other degree or qualification in this, or any other University This Graduate Project is the result of my own work and includes nothing which is the outcome of work done in collaboration, except where specifically indicated in the text Nicholas J Marsaw December, 2019 Acknowledgements I want to thank Mark A Indovina for his support, advice, and guidance throughout my graduate research and education Your passion for the engineering field and dedication to your students is truly valuable I would also like thank my family for their encouragement as I’ve worked through my education You have been extremely patient and loving Lastly, I would like to thank Anna for her love and support over the past few years as I have been finishing up my academics You’re very special to me, and I couldn’t have accomplished this without you Abstract Increased design complexity has resulted in the need for efficient verification The verification process is crucial for discovering and fixing bugs prior to fabrication and system integration However, as designs increase in complexity, the use of traditional verification techniques with VHDL and Verilog may fall short to provide a proper toolset Especially when performing verification on designs involving audio signal processing, untested corner cases and bugs may result in significant and sometimes undiscovered processing errors This paper explores the use of SystemVerilog and the universal verification methodology (UVM) class library to verify a pipelined floating-point multiplier (FMULT) within the adaptive differential pulse code modulation (ADPCM) specification Contents Contents v List of Figures ix List of Tables x Introduction 1.1 Research Goals 1.2 Contributions 1.3 Organization Bibliographical Research Adaptive Differential Pulse Code Modulation UVM Overview 4.1 13 UVM Hierarchy 13 4.1.1 Sequencing 13 4.1.1.1 Sequence Item 15 4.1.1.2 Sequence 15 4.1.1.3 Sequencer 15 vi Contents 4.2 4.1.2 Interface 15 4.1.3 Driver 16 4.1.4 Monitor 16 4.1.5 Agent 16 4.1.6 Environment 16 4.1.7 Scoreboard 17 4.1.8 Test 17 4.1.9 Top 17 Testbench Operation 17 4.2.1 Build Phase 18 4.2.2 Run-time Phase 18 4.2.3 Clean Up Phase 18 Design and Test Methodology 19 5.1 FMULT Design 19 5.2 Testbench Design 20 5.2.1 Sequence Items 22 5.2.1.1 in_sqr_item 22 5.2.1.2 out_sqr_item 22 5.2.2 Sequence 22 5.2.3 Interface 22 5.2.4 Driver 22 5.2.5 Monitor 23 5.2.6 Agent 23 5.2.7 Environment 23 vii Contents 5.2.8 Test 24 5.2.9 Top 24 5.2.10 DPI Functions 24 5.2.11 Watermark 24 Results and Discussion 25 6.1 RTL and Gate Level Simulation Results 25 6.2 RTL and Gate Level Synthesis Results 27 6.3 Discussion 29 Conclusion 7.1 31 Future Work 31 References 33 I I-1 Source Code I.1 FMULT Design I-1 I.2 Interface I-11 I.3 Input Sequence Item I-12 I.4 Output Sequence Item I-13 I.5 Reference Model I-14 I.6 Sequencer I-16 I.7 Driver I-17 I.8 Monitor I-21 I.9 Agent I-30 I.10 Environment I-32 I.11 Test I-34 Contents viii I.12 Top I-35 I-22 I.8 Monitor 24 DUT_3 : c o v e r p o i n t v i f WAn[ ] ; 25 DUT_4 : c o v e r p o i n t v i f WAn[ ] ; 26 DUT_5 : c o v e r p o i n t v i f WAn[ ] ; 27 DUT_6 : c o v e r p o i n t v i f WAn[ ] ; 28 DUT_7 : c o v e r p o i n t v i f WAn[ ] ; 29 DUT_8 : c o v e r p o i n t v i f WAn[ ] ; 30 DUT_9 : c o v e r p o i n t v i f WAn[ ] ; 31 DUT_10 : c o v e r p o i n t v i f WAn[ ] ; 32 DUT_11 : c o v e r p o i n t v i f WAn[ 1 ] ; 33 DUT_12 : c o v e r p o i n t v i f WAn[ ] ; 34 DUT_13 : c o v e r p o i n t v i f WAn[ ] ; 35 DUT_14 : c o v e r p o i n t v i f WAn[ ] ; 36 DUT_15 : c o v e r p o i n t v i f WAn[ ] ; 37 38 REF_0 : c o v e r p o i n t exp WAn[ ] ; 39 REF_1 : c o v e r p o i n t exp WAn[ ] ; 40 REF_2 : c o v e r p o i n t exp WAn[ ] ; 41 REF_3 : c o v e r p o i n t exp WAn[ ] ; 42 REF_4 : c o v e r p o i n t exp WAn[ ] ; 43 REF_5 : c o v e r p o i n t exp WAn[ ] ; 44 REF_6 : c o v e r p o i n t exp WAn[ ] ; 45 REF_7 : c o v e r p o i n t exp WAn[ ] ; 46 REF_8 : c o v e r p o i n t exp WAn[ ] ; 47 REF_9 : c o v e r p o i n t exp WAn[ ] ; 48 REF_10 : c o v e r p o i n t exp WAn[ ] ; I-23 I.8 Monitor 49 REF_11 : c o v e r p o i n t exp WAn[ 1 ] ; 50 REF_12 : c o v e r p o i n t exp WAn[ ] ; 51 REF_13 : c o v e r p o i n t exp WAn[ ] ; 52 REF_14 : c o v e r p o i n t exp WAn[ ] ; 53 REF_15 : c o v e r p o i n t exp WAn[ ] ; 54 55 CC_0 : c r o s s DUT_0 , REF_0 56 { b i n s p a s s = b i n s o f ( DUT_0 ) 57 CC_1 58 { b i n s p a s s = b i n s o f ( DUT_1 ) 59 CC_2 60 { b i n s p a s s = b i n s o f ( DUT_2 ) 61 CC_3 62 { b i n s p a s s = b i n s o f ( DUT_3 ) 63 CC_4 64 { b i n s p a s s = b i n s o f ( DUT_4 ) 65 CC_5 66 { b i n s p a s s = b i n s o f ( DUT_5 ) 67 CC_6 68 { b i n s p a s s = b i n s o f ( DUT_6 ) 69 CC_7 70 { b i n s p a s s = b i n s o f ( DUT_7 ) 71 CC_8 72 { b i n s p a s s = b i n s o f ( DUT_8 ) 73 CC_9 && b i n s o f ( REF_0 ) ; } : c r o s s DUT_1 , REF_1 && b i n s o f ( REF_1 ) ; } : c r o s s DUT_2 , REF_2 && b i n s o f ( REF_2 ) ; } : c r o s s DUT_3 , REF_3 && b i n s o f ( REF_3 ) ; } : c r o s s DUT_4 , REF_4 && b i n s o f ( REF_4 ) ; } : c r o s s DUT_5 , REF_5 && b i n s o f ( REF_5 ) ; } : c r o s s DUT_6 , REF_6 && b i n s o f ( REF_6 ) ; } : c r o s s DUT_7 , REF_7 && b i n s o f ( REF_7 ) ; } : c r o s s DUT_8 , REF_8 : c r o s s DUT_9 , REF_9 && b i n s o f ( REF_8 ) ; } I-24 I.8 Monitor 74 { b i n s p a s s = b i n s o f ( DUT_9 ) 75 CC_10 76 { b i n s p a s s = b i n s o f ( DUT_10 ) 77 CC_11 78 { b i n s p a s s = b i n s o f ( DUT_11 ) 79 CC_12 80 { b i n s p a s s = b i n s o f ( DUT_12 ) 81 CC_13 82 { b i n s p a s s = b i n s o f ( DUT_13 ) 83 CC_14 84 { b i n s p a s s = b i n s o f ( DUT_14 ) 85 CC_15 86 { b i n s p a s s = b i n s o f ( DUT_15 ) 87 && b i n s o f ( REF_9 ) ; } : c r o s s DUT_10 , REF_10 && b i n s o f ( REF_10 ) ; } : c r o s s DUT_11 , REF_11 && b i n s o f ( REF_11 ) ; } : c r o s s DUT_12 , REF_12 && b i n s o f ( REF_12 ) ; } : c r o s s DUT_13 , REF_13 && b i n s o f ( REF_13 ) ; } : c r o s s DUT_14 , REF_14 && b i n s o f ( REF_14 ) ; } : c r o s s DUT_15 , REF_15 && b i n s o f ( REF_15 ) ; } endgroup 88 89 f u n c t i o n new ( s t r i n g name , uvm_component p a r e n t ) ; 90 s u p e r new ( name , p a r e n t ) ; 91 from_rm = new ( " from_rm " , t h i s ) ; 92 exp 93 c o v _ o u t = new ( ) ; 94 count 95 num_mismatches = ; 96 num_matches = 0; 97 free = 0; 98 = new ( " exp " ) ; endfunction = 0; I-25 I.8 Monitor 99 100 v i r t u a l f u n c t i o n v o i d b u i l d _ p h a s e ( uvm_phase p h a s e ) ; 101 super build_phase ( phase ) ; 102 void ’ ( uvm_resource_db #( i n t f _ v i f ) : : read_by_name ( scope ( " i f s " ), 103 104 105 name ( " i n t f _ v i f " ) , v a l ( v i f ) ) ) ; t r = in_sqr_item : : type_id : : create ( " t r " , this ) ; endfunction 106 107 108 109 v i r t u a l f u n c t i o n s t r i n g get_type_name ( ) ; r e t u r n type_name ; endfunction 110 111 v i r t u a l function i n t get_watermark ( ) ; 112 w m f i l e = $ f o p e n ( " s r c / w a t e r m a r k param " , " r " ) ; 113 w m s t r i n g = $ f s c a n f ( wmfile , "%d " , w a t e r m a r k ) ; 114 i f ( w a t e r m a r k == " " ) r e t u r n ; 115 e l s e $ d i s p l a y ( " Running t o Watermark o f : %d " , w a t e r m a r k ) ; 116 return 1; 117 endfunction 118 119 v i r t u a l t a s k r u n _ p h a s e ( uvm_phase p h a s e ) ; 120 phase r a i s e _ o b j e c t i o n ( t h i s ) ; 121 super run_phase ( phase ) ; 122 fork I.8 Monitor 123 c o m p a r e _ t r a n s a c t i o n s ( phase ) ; 124 end_sim ( phase ) ; 125 126 join endtask 127 128 v i r t u a l t a s k e n d _ s i m ( uvm_phase p h a s e ) ; 129 @( e n d s i m u l a t i o n ) 130 phase dro p_o bje cti on ( t h i s ) ; 131 endtask 132 133 134 135 v i r t u a l task put ( out_sqr_item t ) ; exp copy ( t ) ; endtask 136 137 v i r t u a l function bit try_put ( out_sqr_item t ) ; 138 exp copy ( t ) ; 139 return 1; 140 endfunction 141 142 143 144 v i r t u a l function b i t can_put ( ) ; return free ; endfunction 145 146 147 v i r t u a l t a s k c o m p a r e _ t r a n s a c t i o n s ( uvm_phase p h a s e ) ; a1 : a s s e r t ( g e t _ w a t e r m a r k ( ) == ) ; I-26 I-27 I.8 Monitor 148 start_time = get_time () ; 149 w a i t ( v i f r e s e t === 150 @( n e g e d g e v i f r e s e t ) ; 1) ; 151 152 −> b e g i n _ d e l a y ; 153 b e g i n 154 @( n e g e d g e v i f c l k ) ; 155 c o u n t ++; 156 end w h i l e ( c o u n t ! = ) ; 157 −> e n d _ d e l a y ; 158 159 160 161 forever begin @( n e g e d g e v i f c l k ) ; i f ( exp WAn !== v i f WAn) b e g i n 162 num_mismatches ++; 163 uvm_report_warning ( get_type_name ( ) , $sformatf ( " Output Mismatch RM: %h DUT: %h (% f m i s m a t c h e s ) " , exp WAn, v i f WAn, num_mismatches ) ,UVM_NONE) ; 164 end 165 e l s e begin 166 / / uvm_report_info ( get_type_name ( ) , $sformatf ( " Output match RM: %h DUT: %h (% f m i s m a t c h e s ) " , exp WAn, v i f WAn , num_mismatches ) ,UVM_NONE) ; 167 168 num_matches ++; end I-28 I.8 Monitor 169 cov_out sample ( ) ; 170 @( n e g e d g e v i f c l k ) ; 171 −> compared ; 172 173 / / Uncomment f o r Coverage −Based f u n c t i o n a l i t y i n s t e a d o f Watermark 174 / * 175 i f ( ( ( num_matches + num_mismatches ) % 0 0 ) == ) b e g i n 176 $ d i s p l a y ("% d Runs " , num_matches + num_mismatches ) ; 177 i f ( $ g e t _ c o v e r a g e ( ) >= 0 ) b e g i n 178 −> e n d s i m u l a t i o n ; 179 end 180 end 181 * / 182 / / Uncomment f o r Watermark−Based F u n c t i o n a l i t y i n s t e a d o f Coverage 183 / / /* 184 i f ( ( num_matches + num_mismatches ) == w a t e r m a r k ) b e g i n −> e n d s i m u l a t i o n ; 185 186 187 end / / */ 188 189 end 190 endtask 191 I.8 Monitor 192 193 I-29 f u n c t i o n v o i d r e p o r t _ p h a s e ( uvm_phase p h a s e ) ; $ d i s p l a y ( " S i m u l a t i o n Ended Number o f T e s t s : %d " , num_matches + num_mismatches ) ; 194 $ d i s p l a y ( " T o t a l C o v e r a g e : %.2 f " , $ g e t _ c o v e r a g e ( ) ) ; 195 $ d i s p l a y ( "Num P a s s e s : %d \ nNum F a i l s : %d " , num_matches , num_mismatches ) ; 196 run_time = get_time ( ) − s t a r t _ t i m e ; 197 hrs = run_time / 3600; 198 = ( r u n _ t i m e − ( h r s * 0 ) ) / ; 199 s e c = ( r u n _ t i m e − ( h r s * 0 ) − ( * ) ) ; 200 $ d i s p l a y ( " Run Time : %d Hrs %d Min %d Sec " , h r s , , s e c ) ; 201 g e n e r a t e _ r e p o r t ( num_matches , num_mismatches , w a t e r m a r k , , , , run_time , $get_coverage ( ) ) ; 202 203 email_report () ; endfunction 204 205 e n d c l a s s I-30 I.9 Agent I.9 Agent c l a s s a g e n t e x t e n d s uvm_agent ; sequencer sqr ; driver dvr ; monitor #( o u t _ s q r _ i t e m ) mtr ; uvm_put_port #( in_sqr_item ) icp ; ‘uvm_component_utils ( agent ) 10 f u n c t i o n new ( s t r i n g name = " a g e n t " , uvm_component p a r e n t = null ) ; 11 s u p e r new ( name , p a r e n t ) ; 12 i c p = new ( " i c p " , t h i s ) ; 13 endfunction 14 15 v i r t u a l f u n c t i o n v o i d b u i l d _ p h a s e ( uvm_phase p h a s e ) ; 16 super build_phase ( phase ) ; 17 sqr = sequencer : : type_id : : create ( " sqr " , t h i s ) ; 18 dvr = d r i v e r : : type_id : : c r e a t e ( " dvr " , t h i s ) ; 19 mtr = monitor #( o u t _ s q r _ i t e m ) : : t y p e _ i d : : c r e a t e ( " mtr " , t h i s ) ; 20 endfunction 21 22 v i r t u a l f u n c t i o n v o i d c o n n e c t _ p h a s e ( uvm_phase p h a s e ) ; I.9 Agent 23 super connect_phase ( phase ) ; 24 dvr icp connect ( icp ) ; 25 dvr seq_item_port connect ( sqr seq_item_export ) ; 26 endfunction 27 28 e n d c l a s s I-31 I-32 I.10 Environment I.10 Environment c l a s s env e x t e n d s uvm_env ; agent mstr ; refmod rm ; u v m _ t l m _ a n a l y s i s _ f i f o #( i n _ s q r _ i t e m ) to_rm ; ‘ u v m _ c o m p o n e n t _ u t i l s ( env ) f u n c t i o n new ( s t r i n g name , uvm_component p a r e n t = n u l l ) ; 10 s u p e r new ( name , p a r e n t ) ; 11 t o _ r m = new ( " t o _ r m " , t h i s ) ; 12 endfunction 13 14 v i r t u a l f u n c t i o n v o i d b u i l d _ p h a s e ( uvm_phase p h a s e ) ; 15 super build_phase ( phase ) ; 16 mstr = 17 rm 18 = agent : : type_id : : c r e a t e ( " mstr " , t h i s ) ; r e f m o d : : t y p e _ i d : : c r e a t e ( " rm " , this ) ; endfunction 19 20 v i r t u a l f u n c t i o n v o i d c o n n e c t _ p h a s e ( uvm_phase p h a s e ) ; 21 super connect_phase ( phase ) ; 22 / / S e q u e n c e r t o Ref Mod FIFO 23 mstr i c p c o n n e c t ( to_rm p u t _ e x p o r t ) ; I.10 Environment I-33 24 25 / / Ref Mod FIFO t o Ref Mod 26 rm i n c o n n e c t ( t o _ r m g e t _ e x p o r t ) ; 27 28 / / Ref Mod t o M o n i t o r 29 rm o u t c o n n e c t ( m s t r m t r from_rm ) ; 30 endfunction 31 32 v i r t u a l f u n c t i o n v o i d e n d _ o f _ e l a b o r a t i o n _ p h a s e ( uvm_phase phase ) ; 33 34 super end_of_elaboration_phase ( phase ) ; endfunction 35 36 v i r t u a l f u n c t i o n v o i d r e p o r t _ p h a s e ( uvm_phase p h a s e ) ; 37 super r e p o r t _ p h a s e ( phase ) ; 38 ‘ u v m _ i n f o ( g e t _ t y p e _ n a m e ( ) , $ s f o r m a t f ( " R e p o r t i n g Matched %0d " , m s t r m t r num_matches ) ,UVM_NONE) 39 40 i f ( m s t r m t r num_mismatches ) b e g i n ‘ u v m _ e r r o r ( g e t _ t y p e _ n a m e ( ) , $ s f o r m a t f ( " Saw %0d m i s m a t c h e d s a m p l e s " , m s t r m t r num_mismatches ) ) 41 42 end endfunction 43 44 e n d c l a s s I-34 I.11 Test I.11 Test c l a s s FMULT_test e x t e n d s u v m _ t e s t ; env env_h ; seq_in sqr_h ; ‘ u v m _ c o m p o n e n t _ u t i l s ( FMULT_test ) f u n c t i o n new ( s t r i n g name , uvm_component p a r e n t = n u l l ) ; s u p e r new ( name , p a r e n t ) ; endfunction 10 v i r t u a l f u n c t i o n v o i d b u i l d _ p h a s e ( uvm_phase p h a s e ) ; 11 super build_phase ( phase ) ; 12 env_h = env : : t y p e _ i d : : c r e a t e ( " env_h " , t h i s ) ; 13 sqr_h = seq_in : : type_id : : c r e a t e ( " sqr_h " , t h i s ) ; 14 endfunction 15 16 t a s k r u n _ p h a s e ( uvm_phase p h a s e ) ; 17 s q r _ h s t a r t ( env_h m s t r s q r ) ; 18 endtask 19 20 e n d c l a s s I-35 I.12 Top I.12 Top ‘ i n c l u d e " uvm_macros s v h " ‘ i n c l u d e " i n t f sv " ‘ i n c l u d e "FMULT_pkg s v " module t e s t ; 10 import uvm_pkg : : * ; 11 i m p o r t FMULT_pkg : : * ; 12 13 logic clk ; 14 15 i n t f vif ( clk ) ; 16 17 i n i t i a l begin 18 clk 19 vif r e s e t = 0; 20 = 0; end 21 22 23 a l w a y s #5 c l k = ~ c l k ; I-36 I.12 Top 24 i n i t i a l begin 25 $ t i m e f o r m a t ( −9 ,2 , " n s " , ) ; 26 ‘ i f d e f SDFSCAN 27 $ s d f _ a n n o t a t e ( " s d f / FMULT_tsmc18_scan s d f " , t e s t t o p ) ; 28 ‘endif 29 u v m _ r e s o u r c e _ d b # ( i n t f _ v i f ) : : s e t ( s c o p e ( " i f s " ) , name ( " i n t f _ v i f " ) , val ( vif ) ) ; 30 $ s e t _ c o v e r a g e _ d b _ n a m e ( "FMULT" ) ; 31 r u n _ t e s t ( " FMULT_test " ) ; 32 end 33 34 FMULT t o p ( v i f r e s e t , 35 clk , 36 v i f scan_in0 , 37 v i f scan_en , 38 v i f test_mode , 39 v i f scan_out0 , 40 v i f An , 41 v i f SRn , 42 v i f WAn) ; 43 44 endmodule ... a 6-stage 20 5.2 Testbench Design Stage An SRn AnMAG SRnMAG WAnS Stage Stage Stage Stage An1 An2 An3 An4 SRn2 SRn3 SRn4 AnMAG1 AnMAG2 AnMAG3 AnMAG4 SRnMAG1 SRnMAG2 SRnMAG3 SRnMAG4 AnEXP1 AnEXP2... robustness in verification As a language capable of both design and verification, or a hardware description and verification language (HDVL), SV was adopted by IEEE as a standard in 2005 [7] SV also included... SRnEXP1 AnMANT SRnMANT Stage SRn1 AnEXP SRnEXP Stage SRnEXP2 AnMANT1 AnEXP3 SRnMANT2 WAnS1 WAnS2 WAnEXP AnEXP4 SRnEXP3 AnMANT2 SRnMANT1 SRnEXP4 AnMANT3 SRnMANT3 AnMANT4 SRnMANT4 WAnS3 WAnEXP1 WAnMANT