Low-Power and Programmable Analog Circuitry for Wireless Sensors

Graduate Theses, Dissertations, and Problem Reports 2014 Low-Power and Programmable Analog Circuitry for Wireless Sensors Brandon David Rumberg Follow this and additional works at: https://researchrepository.wvu.edu/etd Recommended Citation Rumberg, Brandon David, "Low-Power and Programmable Analog Circuitry for Wireless Sensors" (2014) Graduate Theses, Dissertations, and Problem Reports 6541 https://researchrepository.wvu.edu/etd/6541 This Dissertation is protected by copyright and/or related rights It has been brought to you by the The Research Repository @ WVU with permission from the rights-holder(s) You are free to use this Dissertation in any way that is permitted by the copyright and related rights legislation that applies to your use For other uses you must obtain permission from the rights-holder(s) directly, unless additional rights are indicated by a Creative Commons license in the record and/ or on the work itself This Dissertation has been accepted for inclusion in WVU Graduate Theses, Dissertations, and Problem Reports collection by an authorized administrator of The Research Repository @ WVU For more information, please contact researchrepository@mail.wvu.edu Low-Power and Programmable Analog Circuitry for Wireless Sensors by Brandon David Rumberg Dissertation submitted to the College of Engineering and Mineral Resources at West Virginia University in partial fulfillment of the requirements for the degree of Doctor of Philosophy in Electrical Engineering David W Graham, Ph.D., Chair Lawrence A Hornak, Ph.D Vinod K Kulathumani, Ph.D James W Lewis, Ph.D Matthew C Valenti, Ph.D Lane Department of Computer Science and Electrical Engineering Morgantown, West Virginia 2014 Copyright 2014 Brandon David Rumberg Abstract Low-Power and Programmable Analog Circuitry for Wireless Sensors by Brandon David Rumberg Doctor of Philosophy in Electrical Engineering West Virginia University David W Graham, Ph.D., Chair Embedding networks of secure, wirelessly-connected sensors and actuators will help us to conscientiously manage our local and extended environments One major challenge for this vision is to create networks of wireless sensor devices that provide maximal knowledge of their environment while using only the energy that is available within that environment In this work, it is argued that the energy constraints in wireless sensor design are best addressed by incorporating analog signal processors The low power-consumption of an analog signal processor allows persistent monitoring of multiple sensors while the device’s analog-to-digital converter, microcontroller, and transceiver are all in sleep mode This dissertation describes the development of analog signal processing integrated circuits for wireless sensor networks Specific technology problems that are addressed include reconfigurable processing architectures for low-power sensing applications, as well as the development of reprogrammable biasing for analog circuits iii Dedication To faculty and peers who have been so helpful, To family who won’t try to read beyond this page— and more so to those who will, And to anyone who may benefit from this work iv Contents Dedication iii List of Figures ix List of Tables xii Symbols and Acronyms xiii Introduction Analog Signal Processing and Energy Efficiency in Sensor Networks 2.1 Resource Limitations in Wireless Sensors 2.2 Low-Power Analog Signal Processing 3 A “Hibernets” Event Detector for Slumbering Sensors 3.1 Introduction 3.2 Analog Signal Processing in Sensor Networks 3.3 Background 3.4 Design of Analog Computational Elements 3.4.1 Filter Bank 3.4.2 Resistive Biasing 3.4.3 Magnitude Detector 3.4.4 Event Detection 3.4.5 Power Consumption 3.5 Interfacing With the Telos Mote 3.6 Performance Evaluation 3.6.1 Selective Wake-Up Mode 3.6.2 Selective Sample Mode 3.6.3 Evaluation in the context of an automobile classification application 3.6.3.1 Data Collection 3.6.3.2 Training 3.6.3.3 Testing 3.6.3.4 Comparison with all-digital implementation 3.6.3.5 Discussion 3.6.4 Other Applications and Potential Extensions 3.7 Conclusions 9 11 13 14 15 16 16 17 18 20 21 21 22 23 24 25 26 26 28 29 29 CONTENTS v A Low-Power and High-Precision Programmable Analog Filter Bank 4.1 Analog Filter Banks 4.2 Bandpass Filter 4.2.1 OTA-C4 4.2.2 Design 4.2.3 Performance 4.3 Filter Bank 4.3.1 Filter Characterization and Programming 4.3.2 Demonstrations 4.4 Conclusion A Low-Power Magnitude Detector for Analysis of 5.1 Magnitude Detector Circuits 5.2 Magnitude Detector Architecture 5.3 Peak Detector 5.3.1 Overview of the Peak Detector Circuit 5.3.2 Peak Detector Analysis 5.3.3 Peak Detector Biasing 5.4 Adaptive-Time-Constant Filter 5.4.1 Nonlinear Transconductor 5.4.2 Demonstration of Performance 5.4.3 Design 5.5 Complete Magnitude Circuit 5.6 Conclusion Transient-Rich Signals Floating-Gate Transistors for Programmable Analog Circuitry 6.1 Floating-Gate Transistors 6.2 Applications of Floating-Gate Transistors 6.2.1 Programmable Parameters 6.2.2 Precision Mismatch Correction 6.2.3 Parameter Adaptation 6.2.4 Input Scaling 6.2.5 Multiple-Input Transistors 6.2.6 Summary of FG Transistor Applications 6.3 Overview of Floating-Gate Programming 6.4 Pulse-Based Programming 6.4.1 Coarse Programming Mode 6.4.2 Fine Programming Mode 6.5 Continuous-Time Floating Gate Programming 6.6 Current-Conveyor-Based Memory Cell 6.7 Programmer Circuit 6.8 Array Architecture 6.9 Conclusion 31 31 33 34 35 36 38 38 40 40 41 41 43 45 45 46 48 49 49 50 51 52 56 58 58 60 60 62 62 62 63 63 64 65 66 68 69 70 72 74 74 CONTENTS vi Modeling of Charge Manipulation in Floating-Gate Transistors 7.1 Efficiency and Reliability of Fowler-Nordheim Tunneling in CMOS FloatingGate Transistors 7.1.1 Fowler-Nordheim Tunneling Current 7.1.2 Temporal Dynamics of Tunneling Junctions 7.1.3 Sizing of Tunneling Junctions for Speed and Reliability 7.1.4 Conclusion of Tunneling-Junction Study 7.2 Characterization of Hot-Electron Injection Across Varying Transistor Dimensions 7.2.1 Injection Measurement 7.2.2 Injection Parameterization 7.3 Conclusion and Future Work 76 76 77 78 80 81 81 81 82 85 A Regulated Charge Pump for Programming Floating-Gate Transistors 86 8.1 Floating-Gate Programming Voltages in Standard CMOS 86 8.2 Overview of Charge Pump Circuitry 89 8.2.1 Charge Pump Topologies 89 8.2.2 Charge Pump Regulation 90 8.3 The Charge Pump Stages 93 8.4 The Current-Controlled Oscillator and the Edgifier 96 8.5 The Complete Charge Pump 100 8.6 How to Adapt the Charge Pump to Generate the Injection Voltage 106 8.7 Conclusion 106 Improving the Hibernets Signal Processor 9.1 Hibernets 2.0 Architecture 9.2 Spectral Analysis Block 9.2.1 Transconductor 9.2.2 Floating-Gate Biasing 9.3 System Operation 9.4 Vehicle-Classification Application 9.5 Discussion of In-Network Training 9.5.1 Towards In-the-Field Training 9.5.2 Steps to Achieve In-the-Field Training 9.6 Conclusion 107 108 109 109 110 110 112 115 115 116 117 10 Netamorph: Simplifying the Design of Low-Power Sensor Networks with Reconfigurable Analog Circuitry 119 10.1 A Sensor Node Architecture Incorporating Reconfigurable Analog Circuitry 119 10.2 Parallelized FPAA Architecture for Embedded Signal Processing 123 10.2.1 Netamorph 1.0 124 10.2.2 Netamorph 2.0 125 10.3 Memory Programming 126 10.3.1 Memory Programming Infrastructure 127 10.3.1.1 Clear Switches & NVM 128 CONTENTS 10.3.1.2 Write NVM 10.3.1.3 Write Switches 10.3.2 High-Side Switch 10.3.3 Summary of FPAA Programming 10.4 Using the FPAA 10.4.1 Interface PCBs 10.4.1.1 Netamorph 1.0 Interface PCB 10.4.1.2 Netamorph 2.0 Interface PCB 10.4.2 Development Environment 10.4.3 Compression of FPAA Configuration Files 10.5 Applications 10.5.1 Demonstrations of Netamorph 1.0 10.5.1.1 Rising Frequency Detector 10.5.1.2 Voice-Activity Detector 10.5.2 Demonstrations of Netamorph 2.0 10.5.2.1 Temperature Sensor 10.5.2.2 Heart-Rate Monitor 10.5.2.3 Audio Spectrum Normalization 10.6 Conclusion and Future Work vii 11 Tradeoffs in Designing Reconfigurable Analog Sensor Interfaces for less Sensing Applications 11.1 FPAA Trends 11.2 FPAA Architecture Tradeoffs 11.2.1 Applying Rent’s Rule to FPAA Design 11.2.2 Designing CAB Size 11.3 The Cost of Analog Reconfiguration 11.3.1 Equivalent Switch Resistance 11.3.2 Erasing a Floating-Gate Switch Matrix 11.3.3 Writing a Floating-Gate Switch 11.3.4 Energy Costs of Volatile and Nonvolatile Switches 11.3.5 Other Considerations Regarding Switches 11.4 System-Level Implications of Reconfiguration 11.5 Discussion of Reconfiguration Costs 128 128 129 130 130 130 130 131 132 133 137 137 137 137 137 139 140 140 140 Wire144 144 147 148 149 152 152 153 154 155 155 156 158 12 Conclusions and Future Work 160 References 162 A Background on Sub-Threshold Analog Circuits 181 A.1 Sub-Threshold MOSFET Operation 181 A.2 Electronically-Tunable Transconductors 182 B Event Detection Time-Lag and Memory Buffers 184 B.1 Time Lag to Assert Events 184 B.2 Memory Buffering 185 CONTENTS viii C Analysis of the OTA-Based Capacitively-Coupled Current Conveyor C.1 Derivations for an OTA-based C4 C.1.1 Transfer Function C.1.2 C4 at High Frequencies C.1.3 C4 at Low Frequencies C.1.4 Capacitive Feedthrough C.1.5 Solving for Qmax C.2 OTA-C4 Noise Analysis C.2.1 Noise Transfer Function for Gm1 Noise Source C.2.2 Noise Transfer Function for Gm2 Noise Source C.2.3 Integrated Noise 190 190 190 192 193 193 194 195 195 196 197 D Analysis of the Peak Detector D.1 Problem Setup D.1.1 Input/Output Definitions D.2 Solving the Loop D.2.1 Node e D.2.2 Node u D.2.2.1 Solving for DC at Node u D.2.2.2 Solving for the Fundamental D.2.3 Node Vout D.3 Balancing the Terms D.3.1 Tracking Level D.4 Ripple D.5 Conclusions 201 201 202 203 203 204 204 204 205 205 206 207 207 at Node u ix List of Figures 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 Analog pre-processing for sensor networks “Hibernets” architecture First Hibernets design Hibernets filter bank Hibernets magnitude detector Multi-band detection using an exclusive-or template Power consumption of ASP versus frequency Hibernets system Event detection demonstrations Vehicle classification demonstration System lifetime as a function of event frequency 10 11 14 15 17 18 19 20 22 24 28 4.1 4.2 4.3 4.4 4.5 Block diagram of the programmable analog filter bank chip Capacitively-coupled current conveyor (C4 ) bandpass filter Bandpass filter noise and linearity measurements AC responses of the programmable filter bank Time-frequency decomposition with the filter bank 32 33 37 39 40 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 5.10 5.11 Magnitude detector overview Tradeoff between amplitude accuracy and temporal accuracy Peak detector circuit Nonlinear modeling of the peak detector circuit Adaptive-time-constant filter Operation of the adaptive-time-constant filter Amplitude dependence of the time constant Micrograph of the magnitude circuit Dynamic range of the magnitude detector Transient response of the magnitude detector Speech response of the magnitude detector 42 44 46 47 49 50 51 53 55 56 57 6.1 6.2 6.3 6.4 6.5 Overview of floating-gate transistors Applications of charge manipulation in floating-gate transistors Applications of capacitive coupling in floating-gate transistors Floating-gate programming: pulsed vs continuous Block diagram of our benchtop floating-gate programmer 59 61 63 65 66 Appendix C C4 Analysis Brandon D Rumberg 193 C2 Vin C1 V a Vout -A CL CW Gm2 Figure C.3: Schematic for transfer-function derivation at low frequencies C.1.3 C4 at Low Frequencies Now let’s consider the C4 at low frequencies At node Va sC1 Vin + sC2 Vout = −Gm2 Vout C1 sC2 +1 = −s Vin Vout Gm2 Gm2 s GCm2 Vout = − Vin + s GCm2 C2 C1 s Gm2 = − C2 + s GCm2 = − where τl = C.1.4 C1 sτl C2 + sτl C2 Gm2 (C.26) (C.27) (C.28) (C.29) (C.30) (C.31) Capacitive Feedthrough During normal operation we want to keep the corner caused by the capacitive feedthrough time-constant τf at a much higher frequency than the low-pass corner caused by τh τf C2 Gm1 2C2 2C2 τh CO CT − C2 C2 Gm1 C O CT (C2 + CL ) (C1 + C2 + CW ) (C.32) (C.33) (C.34) (C.35) If all capacitors are equal 2C 6C (C.36) Appendix C C4 Analysis Brandon D Rumberg C.1.5 194 Solving for Qmax Now let’s find the maximum Q value Q = CL = CT CO − C2 Gm2 Gm1 Gm2 Gm1 Gm2 Gm1 + C2 Gm1 Gm2 CT CO − C2 C2 Gm2 Gm1 (C.37) CL Gm2 C2 Gm1 +1 (C.38) Let Gm2 Gm1 CL a = C2 b = (C.39) (C.40) CT CO − C2 C2 d = (C.41) √ bd √ ab + bd = + ab = db1/2 (1 + ab)−1 Q = (C.42) (C.43) (C.44) Take the derivative −1/2 dQ = db (1 + ab)−1 + db1/2 −a (1 + ab)−2 db d − ab = √ b (1 + ab) This equals zero when − ab = 0, which is when b = a d a + a a1 d = √ a Qmax = (C.46) meaning Qmax occurs when C2 Gm2 = CL Gm1 = (C.45) CT CO − C2 CL C2 (C.47) (C.48) (C.49) (C.50) Brandon D Rumberg Appendix C C4 Analysis 195 The gain at Qmax is C1 C2 + a a1 C1 = − 2C2 Av = − Qmax = (2Qmax )2 = CT CO − C2 CL C2 CT CO − C2 CL C2 (C.51) (C.52) (C.53) (C.54) Let X = (2Qmax )2 XC2 CL = CT CO − C2 CT CO = C2 (XCL + C2 ) = XC2 CO + C2 (1 − X) C2 (1 − X) CT = XC2 + CO CL (X − 1) = C2 + C2 + CL CL (X − 1) − C1 + CW = C2 C2 + CL CL (X − 1) = C2 C2 + CL C2 CL = (X − 1) C2 + CL = (X − 1) C2 ||CL = 4Qmax − C2 ||CL C.2 (C.55) (C.56) (C.57) (C.58) (C.59) (C.60) (C.61) (C.62) (C.63) (C.64) OTA-C4 Noise Analysis The OTA’s are the noise sources in an OTA-C4 We can determine the noise contribution of each OTA by placing a noise source at the non-inverting terminal of that OTA, grounding the input to the C4 and calculating the response at the output Let’s start with a noise source at the non-inverting terminal of the feed-forward OTA C.2.1 Noise Transfer Function for Gm1 Noise Source At node Vout we have sCO Vout = Gm1 v1n + Va (sC2 − Gm1 ) (C.65) Appendix C C4 Analysis Brandon D Rumberg 196 C2 C1 Va Vout Gm1 σ2 CW Gm2 CL σ2 Figure C.4: Schematic of the OTA-C4 for noise analysis and at node Va we have Va (sCT + Gm2 ) = Vout (Gm2 + sC2 ) (C.66) Combining equations C.65 and C.66 we have Vout = v1n C.2.2 T s GCm2 +1 CT −C2 s2 CGOm1 +s Gm2 CL Gm1 + C2 Gm2 +1 (C.67) +1 Noise Transfer Function for Gm2 Noise Source Next we will look at the noise contribution for the feed-back OTA Starting with node Vout sCO Vout = Va (sC2 − Gm1 ) (C.68) Vout (sC2 + Gm2 ) + Gm2 i2n = (sCT + Gm2 ) Va (C.69) and at node Va Combining these equations we get Vout = v2n Since C2 Gm1 s GCm1 −1 CO −C2 s2 CGT m1 +s Gm2 CL Gm1 + C2 Gm2 (C.70) +1 = τf , and τf is far outside the passband, we can approximate Vout ≈ v2n CO −C2 s2 CGT m1 Gm2 +s CL Gm1 + C2 Gm2 (C.71) +1 Appendix C C4 Analysis Brandon D Rumberg C.2.3 197 Integrated Noise Now to combine and integrate the noise The standard form for the equivalent noise bandwidth of a bandpass filter is also f f0 Q ∞ f f0 1− 2 ∞ f f0 1− 2 + f f0 Q π f0 2Q (C.72) df = π f0 Q (C.73) f f0 Q + df = where 2πτ f0 = 2π = Gm1 Gm2 CO CT − C2 (C.74) CO CT − C2 Q = Gm2 Gm1 CL (C.75) Gm1 Gm2 + C2 The full noise of the circuit is ∞ v1n 2 Vˆout = 1− ∞ f f0 + 1− f f0 ∞ 1− ∞ f f0 + df 2 f f0 Q + f f0 Q v2n Av2 + 2 v2n + f f0 Q f f0 Q v1n Av1 + 1− f f0 f f0 Q df 2 + df f f0 Q df (C.76) Appendix C C4 Analysis Brandon D Rumberg 198 where CT τ = Q Gm2 CT Q Av1 = Gm2 τ CT Gm1 Gm2 = Gm2 Gm2 CL + Gm1 C2 Gm1 CT = Gm2 CL + Gm1 C2 C2 τ = Av2 Q Gm1 C2 Q Av2 = Gm1 τ C2 Gm1 Gm2 = Gm1 Gm2 CL + Gm1 C2 Gm2 C2 = Gm2 CL + Gm1 C2 (C.77) Av1 f0 Q = = 2π Gm1 Gm2 CO CT − C2 CL (C.78) (C.79) (C.80) (C.81) (C.82) (C.83) (C.84) CO CT − C2 Gm2 Gm1 + C2 Gm1 Gm2 2π CL Gm2 + C2 Gm1 Gm1 Gm2 CL CO CT − C2 CL Gm2 + C2 Gm1 = 2π CO CT − C2 f0 = Q 2π (C.85) Gm1 Gm2 (C.86) Gm2 Gm1 + C2 Gm1 Gm2 CO CT − C2 (C.87) (C.88) Using the integral results listed above π f0 π f0 2 π 2 π Vˆout = v1n f0 Q + v1n A2v1 + v2n f0 Q + v2n A2v2 2Q 2Q Gm1 Gm2 π = v1n 2π CL Gm2 + C2 Gm1 Gm1 CT CL Gm2 + C2 Gm1 π +v1n Gm2 CL + Gm1 C2 2π CO CT − C22 Gm1 Gm2 π +v2n 2π CL Gm2 + C2 Gm1 Gm2 C2 CL Gm2 + C2 Gm1 π +v2n Gm2 CL + Gm1 C2 2π CO CT − C22 (C.89) (C.90) Appendix C C4 Analysis Brandon D Rumberg G2m1 Gm1 Gm2 v2 CT2 v2 + 1n Vˆout = 1n CL Gm2 + C2 Gm1 CO CT − C22 Gm2 CL + Gm1 C2 v2 G2m2 Gm1 Gm2 v2 C22 + 2n + 2n CL Gm2 + C2 Gm1 CO CT − C22 Gm2 CL + Gm1 C2 to 199 (C.91) When Q = Qmax , Gm1 = Gm2 CCL2 and Gm2 = Gm1 CCL2 This simplifies the above expression 2 v Gm1 v1n CT2 Gm1 v2n Gm2 v2n C22 Gm2 = 1n + + + Vˆout 2 2CL CO CT − C2 2C2 2C2 CO CT − C2 2CL Assuming that CT2 (C.92) C22 , this can be approximated as 2 v Gm1 v1n CT Gm1 v2n Gm2 v2n Gm2 C22 Vˆout = 1n + + + 2CL 2C2 CO 2C2 2CT CL2 (C.93) The last term makes contributes very little in relation to the rest of the terms so it can be neglected For an OTA the noise is vn2 = N qVL2 N qIb N qVL = = Ib Gm Gm (C.94) where N is the number of noise sources We will assume that both OTA’s have the same number of noise sources and linear range VL N qVL N qVL CT N qVL Vˆout = + + 8CL 8C2 CO 8C2 (C.95) Under normal operation, CL is very large so the first term can be neglected N qVL Vˆout = 8C2 CT +1 CO (C.96) CT CO − C22 CT CO CT ≈ ≈ = CL C2 CL C2 C2 There are three cases to consider Q2max Case 1: CT CO (C.97) N qVL CT N qVL Q2max Vˆout ≈ ≈ 8C2 CO 2CO   VL √   SN R = 10log10   = 10log10 Vˆout (C.98) VL CO N qQ2max (C.99) Brandon D Rumberg Case 2: CT CO Appendix C C4 Analysis =1 N qVL ≈ Vˆout 4C2 SN R = 10log10 Case 3: CT CO 200 (C.100) 2VL C2 Nq (C.101) N qVL N qVL Q2max Vˆout ≈ ≈ 8C2 2CT VL CT SN R = 10log10 N qQ2max (C.102) (C.103) 201 Appendix D Analysis of the Peak Detector In Chapter 5, which described our magnitude detector circuit, we described the analysis of the circuit in broad terms In this Appendix, we provide the full analysis of the peak detector The steady-state operating parameters of the peak detector are the tracking level (At ) and the ripple (RO ) To bias the circuit, the tunable parameters (i.e the transconductances Gm,A and Gm,D ) are set such that the desired operating characteristics are achieved Thus, biasing requires knowledge of how the operating parameters (At and RO ) depend upon the tunable parameters (Gm,A and Gm,D ) As such, we have analyzed the peak detector to obtain these relations D.1 Problem Setup Nonlinearity M1 M2 Gm,A Linear Integration Vout Vin CPD Vin + Nonlinearity e u f(e) Linear Integration 1/sC Vout - Gm,D M4 M3 (a) (b) Figure D.1: (a) Peak detector circuit (b) First-order nonlinear model of the peak detector circuit The peak detector has a lowpass form and can be modeled by the system in Fig D.1, Brandon D Rumberg Appendix D Magnitude Detector Analysis 202 where the nonlinearity is the piecewise-linear asymmetry formed by the OTAs and current mirrors The nonlinearity can be written in terms of the transconductances f (e) = Gm,a e, e > Gm,d e, else (D.1) As an aside, note that (D.1) can be written as Gm,a − Gm,d Gm,a + Gm,d e+ |e| (D.2) 2 The rectifying nature of the system can be observed from the second term The harmonic balance method will be used to analyze the system’s steady-state response to a sinusoidal input Using this method, we will obtain approximate analytical expressions for the dc (i.e tracking level) and fundamental (i.e ripple) frequency components These expressions are approximate because the harmonics created by the nonlinearity are ignored However, this approximation is justifiable because the circuit has lowpass characteristics and is biased such that the harmonics (as well as the fundamental) are heavily suppressed Furthermore, our experimental results in Fig 5.4 show excellent agreement with the derived expressions f (e) = D.1.1 Input/Output Definitions The input to the system is a sine wave Vin = Vin,pk sin(ωt) (D.3) Within the intended application of spectral analysis, the peak detector will receive its input from narrow-band filters Thus, the peak detector input will be sine-like, and so performing the analysis only for sine waves is sufficient For the harmonic balance method, we specify the form of the output based on the number of frequency components that are expected Since the peak detector has a lowpass form, the harmonics that are created by the nonlinearity can be ignored Thus, we write the output as Vout = Vout,pk sin(ωt + φ) + Vout,dc (D.4) Vout,dc is the magnitude estimate, which should change in proportion to Vin,pk The sine term is the ripple, which is suppressed by the second stage of the magnitude detector By defining the circuit’s operating parameters as the tracking level At = Vout,dc Vin,pk (D.5) and the ripple proportion Vout,pk Vin,pk we can rewrite the output in terms of those operating parameters RO = Vout = Vin,pk [RO sin(ωt + φ) + At ] A graphical illustration of these parameters is shown in Fig D.2 (D.6) (D.7) Brandon D Rumberg Appendix D Magnitude Detector Analysis 203 Vin,pk ROVin,pk AtVin,pk Figure D.2: Illustration of the input/output definitions D.2 D.2.1 Solving the Loop Node e We begin prior to the nonlinearity, at node e Combining (D.3) and (D.7), the signal at node e can be written e = Vin − Vout = Vin,pk [sin(ωt) − RO sin(ωt + φ) − At ] The sinusoids can be combined using the trig identity √ a sin x + b sin(x + α) = a2 + b2 + 2ab cos α sin (x + γ) where γ = tan−1 b sin α a + b cos α + 0, a > π, else (D.8) (D.9) (D.10) Using (D.9), (D.8) simplifies to e = Vin,pk [Re sin(ωt + γ) − At ] (D.11) where Re = + RO − RO cos φ (D.12) To further simplify, we will define θ = ωt + γ and write (D.11) as e = Vin,pk [Re sin θ − At ] (D.13) Brandon D Rumberg D.2.2 Appendix D Magnitude Detector Analysis 204 Node u The signal at node u can be obtained by inserting (D.13) into (D.1) u = f (e) = Gm,a Vin,pk [Re sin θ − At ] , θ > sin−1 Gm,d Vin,pk [Re sin θ − At ] , else At Re (D.14) Given the form for the output in (D.7), node u can be approximated by its first two Fourier components u = U0 + U1 sin(θ) (D.15) where π U0 = π and U1 = π u(θ)dθ (D.16) u(θ) sin θdθ (D.17) − π2 π − π2 The nonlinearity does not present a delay, so a single in-phase component is sufficient D.2.2.1 Solving for DC at Node u To solve for the dc component at node u, insert (D.14) into (D.16) to obtain Gm,d Vin,pk U0 = π A e sin−1 ( R t ) − π2 Gm,a Vin,pk [Re sin θ − At ] dθ + π π A e [Re sin θ − At ] dθ sin−1 ( R t ) (D.18) A π sin−1 ( t ) Gm,d Vin,pk Gm,a Vin,pk [−Re cos θ − At θ]− π Re + [−Re cos θ − At θ] −1 At = sin ( R ) π π e Using the identity √ cos sin−1 (x) = − x2 (D.19) (D.20) and grouping terms, we obtain (Gm,A − Gm,D )Vin,pk U0 = π D.2.2.2 Re A2t − + At sin−1 Re At Re − (Gm,a + Gm,d )Vin,pk At π (D.21) Solving for the Fundamental at Node u To solve for the fundamental component at node u, insert (D.14) into (D.17) to obtain Gm,d Vin,pk U1 = π A e sin−1 ( R t ) − π2 Gm,a Vin,pk [Re sin θ − At ] sin θdθ+ π π A e [Re sin θ − At ] sin θdθ sin−1 ( R t ) (D.22) Brandon D Rumberg Appendix D Magnitude Detector Analysis 205 Looking at just the integral, we obtain θ2 θ2 [Re sin θ − At ] sin θdθ = θ1 θ1 = Re Re − cos(2θ) − At sin θ dθ 2 Re Re θ− sin (2θ) + At cos θ (D.23) θ2 (D.24) θ1 Inserting (D.24) into (D.22) and grouping terms yields U1 = (Gm,A + Gm,D )Re Vin,pk (Gm,A − Gm,D )Vin,pk − At cos sin−1 π Re At At Re − sin sin−1 + sin−1 Re Re At Re Using the identity in (D.20) as well as the following identity √ sin sin−1 (x) = 2x − x2 (D.25) (D.26) we can simplify (D.25) to U1 = (Gm,A + Gm,D )Re Vin,pk (Gm,A − Gm,D )Vin,pk − π D.2.3 At 1− A2t Re + sin−1 Re At Re (D.27) Node Vout The output is related to node u as Vout = u sC (D.28) Equating the frequency components in (D.7) and (D.15) yields Vout,dc = Vin,pk At = U0 |sC| (D.29) Vout,pk = Vin,pk RO = U1 |sC| (D.30) at dc and at the fundamental frequency D.3 Balancing the Terms We can now obtain the analytical expressions that relate the operating parameters At and RO to the tuning parameters Gm,A and Gm,D Brandon D Rumberg D.3.1 Appendix D Magnitude Detector Analysis 206 Tracking Level To solve the loop at dc, we write (D.29) as U0 = |sC|Vout,dc (D.31) Since this is dc, s=0 and therefore U0 =0 Setting (D.27) to zero = (Gm,A − Gm,D ) Vin,pk π and dividing through by A2t + At sin−1 Re2 At Re 1− A2t + sin−1 Re2 At Re Re At 1− 1− Re − (Gm,A + Gm,D ) Vin,pk At (D.32) Vin,pk At = (Gm,A − Gm,D ) π Re At − (Gm,A + Gm,D ) (D.33) For the moment, let us define L= π A2t + sin−1 Re2 At Re (D.34) Now a few manipulations 0 Gm,A (L − 1) Gm,A Gm,D = (Gm,A − Gm,D )L − (Gm,A + Gm,D ) = Gm,A (L − 1) − Gm,D (L + 1) = Gm,D (L + 1) L+1 1+L = = − 1−L L−1 Take the log of both sides and multiply by ln (D.35) (D.36) (D.37) (D.38) Gm,A Gm,D = ln L+1 L−1 (D.39) and use the hyperbolic function identity coth−1 (x) = to obtain ln Gm,A Gm,D ln x+1 x−1 (D.40) = coth−1 (L) (D.41) Now reinsert (D.34) to obtain the final equation log Gm,A Gm,D = coth−1 π Re At 1− A2t + sin−1 Re2 At Re (D.42) Brandon D Rumberg D.4 Appendix D Magnitude Detector Analysis 207 Ripple From (D.30), we can relate U1 to the ripple as Vout,pk U1 = Vin,pk |sC| Vin,pk U1 = Vin,pk RO = ωCRO (D.43) (D.44) Inserting U1 yields ωCRO = (Gm,A + Gm,D )Re Gm,A − Gm,D − π Gm,A Gm,D Defining Rg = At 1− A2t Re sin−1 + Re At Re (D.45) and dividing through by Gm,D RO ωC (Rg + 1)Re Rg − At − = Gm,D π 1− A2t Re + sin−1 Re 1− A2t + sin−1 Re At Re + At Re (D.46) Dividing by Re Rg + 1 − Rg RO ωC = + Re Gm,D π At Re Rg + 1 − Rg ωCP D RO + sin−1 = Gm,D Re π D.5 − Rg At π Re At Re 1− (D.47) A2t Re2 (D.48) Conclusions We have derived two equations—(D.42) and (D.48)—which enable us to purposefully bias the peak detector circuit The biasing procedure is described in Section 5.3.3 These equations describe the steady-state characteristics of an asymmetric integrator in response to a sinusoidal input Asymmetric integration is relevant in other areas, such as in neuronal dynamics, and so this analysis may be of broader interest than for peak detectors ... Science and Electrical Engineering Morgantown, West Virginia 2014 Copyright 2014 Brandon David Rumberg Abstract Low-Power and Programmable Analog Circuitry for Wireless Sensors by Brandon David.. .Low-Power and Programmable Analog Circuitry for Wireless Sensors by Brandon David Rumberg Dissertation submitted to the College of Engineering and Mineral Resources at... automation and analytics for non-specialists, and in the process, will help us to make our living and working spaces more comfortable and sustainable, and also help us to make our public and health