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Lecture – MSP430 ISA Instruction Set Architecture Reading Textbook: Chapter 5: Architecture of the MSP430 Processor (60 pages) Topics to Cover… MSP430 ISA Instruction Formats Double Operand Instructions Single Operand Instructions Jump Instructions Addressing Modes Instruction Disassembly Emulated Instructions Lecture 03 - MSP430 ISA Lecture Objectives (cont’d) Upon completion this lecture, students will be able to: Covert a MSP430’s assembly instruction into machine code Instruction Format: I, II, III 27 Core Instructions and 24 Emulated Instructions source addressing modes destination addressing modes MSP430 Architecture Lecture Objectives Upon completion this lecture, students will be able to: Disassemble a sequence of MSP430’s machine code into assembly language: Using the opcode to find the corresponding instruction mnemonic Append “.b” or “.w” using the b/w bit when appropriate If double operand instruction, decode and list source operand If single or double operand instruction, decode and list destination operand If jump instruction, sign extend the 10-bit PC offset, multiply by 2, and add to the current PC List that address MSP430 Architecture Levels of Transformation Problem Machine Problem Coder Problem solved by Algorithm lampDoesntWork() { if(unPlugged) { plugin(); } else if(burnedOut) { replace(); } else { buyNewLamp(); } } One algorithm = Many statements Assembly language instructions Compiler High-level language statements Algorithm Engineer Problem More concrete, machine-dependent; error prone, harder to write, read, debug, maintain MOV.B 0x0001(SP),R14 MOV.W SP,R15 INCD.W R15 ADD.W R15,R14 MOV.B @R14,0x0000(SP) MOV.B 0x0001(SP),R14 INC.W R14 MOV.W SP,R15 INCD.W R15 ADD.W R15,R14 MOV.B 0x0001(SP),R13 MOV.W SP,R15 INCD.W R15 ADD.W R15,R13 MOV.B @R14,0x0000(R13) MOV.B 0x0001(SP),R15 INC.W R15 MOV.W SP,R14 INCD.W R14 ADD.W R15,R14 MOV.B @SP,0x0000(R14) One statement = Many instructions Lecture 03 - MSP430 ISA Machine language instructions Assembler Abstract, machine-independent; easier to write, read, debug, maintain 415E 0001 410F 532F 5F0E 4EE1 0000 415E 0001 531E 410F 532F 5F0E 415D 0001 410F 532F 5F0D 4EED 0000 415F 0001 531F 410E 532E 5F0E 41EE 0000 Instruction = Many cycles MSP430 ISA Instruction Set Architecture The computer ISA defines all of the programmer-visible components and operations of the computer Memory organization address space how may locations can be addressed? addressibility how many bits per location? Register set (Register File) how many? what size? how are they used? Instruction set opcodes data types (operands) addressing modes ISA provides all information needed for someone that wants to write a program in assembly language (or translate from a high-level language to machine language) Lecture 03 - MSP430 ISA MSP430 ISA MSP430 ISA RISC/CISC machine 27 orthogonal instructions jump instructions single operand instructions 12 double operand instructions addressing modes 8/16-bit instruction addressing formats Memory architecture 16 16-bit registers 16-bit Arithmetic Logic Unit (ALU) 16-bit address bus (64K address space) 16-bit data bus (8-bit addressability) 8/16-bit peripherals Lecture 03 - MSP430 ISA MSP430 ISA MSP430 Registers R0 (PC) – Program Counter This register always points to the next instruction to be fetched Each instruction occupies an even number of bytes Therefore, the least significant bit (LSB) of the PC register is always zero After fetch of an instruction, the PC register is incremented by 2, 4, or to point to the next instruction R1 (SP) – Stack Pointer The MSP430 CPU stores the return address of routines or interrupts on the stack User programs store local data on the stack The SP can be incremented or decremented automatically with each stack access The stack “grows down” thru RAM and thus SP must be initialized with a valid RAM address SP always points to an even address, so its LSB is always zero Lecture 03 - MSP430 ISA MSP430 ISA MSP430 Registers R2 (SR/CG1) – Status Register The status of the MSP430 CPU is contained in register R2 Only accessable through register addressing mode - all other addressing modes are reserved to support the constants generator R3 (CG2) – Constant Generator Register R2 R2 R2 R2 R3 R3 R3 R3 As 00 01 10 11 00 01 10 11 Constant (0) 00004h 00008h 00000h 00001h 00002h 0FFFFh Remarks Register mode Absolute mode +4, bit processing +8, bit processing 0, word processing V Overflow bit SCG1 Turns off the SMCLK SCG0 Turns off the DCO dc generator OSCOFF Oscillator off CPUOFF Turns off the CPU GIE General interrupt enable N Negative bit Z Zero bit C Carry bit +1 +2, bit processing -1, word processing R4-R15 – General Purpose registers Lecture 03 - MSP430 ISA MSP430 ISA MSP430 ALU 16 bit Arithmetic Logic Unit (ALU) Performs instruction arithmetic and logical operations Instruction execution affects the state of the following flags: Zero (Z) Carry (C) Overflow (V) Negative (N) The MCLK (Master) clock signal drives the CPU Lecture 03 - MSP430 ISA 10 Instruction Disassembly How to Disassembly MSP430 Code Begin with a “PC” pointing to the first word in program memory Retrieve instruction word and increment PC by Find and list the corresponding instruction mnemonic using the opcode Append “.b” or “.w” using the b/w bit when appropriate If double operand instruction, decode and list source operand If single or double operand instruction, decode and list destination operand If jump instruction, sign extend the 10-bit PC offset, multiply by 2, and add to the current PC List that address Lecture 03 - MSP430 ISA 42 Instruction Disassembly How to Disassemble MSP430 Code Begin with a “PC” pointing to the first word in program memory Retrieve instruction word and increment PC by PC 0xf800: 0xf804: 0xf80a: 0xf810: 0xf812: 0xf816: 0xf81a: 0xf81c: 0xf820: 0xf822: 0xf826: 0xf828: 0xf82c: 0xf82e: 0xf832: 0xf836: 4031 40b2 d0f2 430e 43a0 4ec2 531e f03e 120e 403e 122e 8391 23fd 411e 5011 3fef 0300 5a80 0120 000f 0022 09ec 0021 000f 0200 0000 0002 0004 mov.w mov.w bis.b mov.w mov.w mov.b add.w and.w push.w mov.w push.w sub.w jne mov.w add.w jmp Lecture 03 - MSP430 ISA 43 Instruction Disassembly How to Disassemble MSP430 Code Find and list the corresponding instruction mnemonic using the opcode (most significant 4-9 bits) Append “.b” or “.w” using the b/w bit when appropriate 0xf800: 0xf804: 0xf80a: 0xf810: 0xf812: 0xf816: 0xf81a: 0xf81c: 0xf820: 0xf822: 0xf826: 0xf828: 0xf82c: 0xf82e: 0xf832: 0xf836: 4031 40b2 d0f2 430e 43a0 4ec2 531e f03e 120e 403e 122e 8391 23fd 411e 5011 3fef 0300 5a80 0120 000f 0022 09ec 0021 000f 0200 0000 0002 0004 mov.w mov.w bis.b mov.w mov.w mov.b add.w and.w push.w mov.w push.w sub.w jne mov.w add.w jmp Lecture 03 - MSP430 ISA 44 Instruction Disassembly How to Disassemble MSP430 Code If double operand instruction, decode and list source operand 0xf800: 0xf804: 0xf80a: 0xf810: 0xf812: 0xf816: 0xf81a: 0xf81c: 0xf820: 0xf822: 0xf826: 0xf828: 0xf82c: 0xf82e: 0xf832: 0xf836: 4031 40b2 d0f2 430e 43a0 4ec2 531e f03e 120e 403e 122e 8391 23fd 411e 5011 3fef 0300 5a80 0120 000f 0022 09ec 0021 000f 0200 0000 0002 0004 mov.w mov.w bis.b mov.w mov.w mov.b add.w and.w push.w mov.w push.w sub.w jne mov.w add.w jmp Lecture 03 - MSP430 ISA #0x0300 #0x5a80 #0x000f #0 #2 r14 #1 #0x000f #0x0200 #1 0x0002(r1) 0x0004(r0) 45 Instruction Disassembly How to Disassemble MSP430 Code If single or double operand instruction, decode and list destination operand 0xf800: 0xf804: 0xf80a: 0xf810: 0xf812: 0xf816: 0xf81a: 0xf81c: 0xf820: 0xf822: 0xf826: 0xf828: 0xf82c: 0xf82e: 0xf832: 0xf836: 4031 40b2 d0f2 430e 43a0 4ec2 531e f03e 120e 403e 122e 8391 23fd 411e 5011 3fef 0300 5a80 0120 000f 0022 09ec 0021 000f 0200 0000 0002 0004 mov.w mov.w bis.b mov.w mov.w mov.b add.w and.w push mov.w push sub.w jne mov.w add.w jmp Lecture 03 - MSP430 ISA #0x0300,sp #0x5a80,&0x0120 #0x000f,&0x0022 #0,r14 #2,0x09ec(r0) r14,&0x0021 #1,r14 #0x000f,r14 r14 #0x0200,r14 @r14 #1,0x0000(r1) 0x0002(r1),r14 0x0004(r0),r1 46 Instruction Disassembly How to Disassemble MSP430 Code If jump instruction, sign extend the 10-bit PC offset, multiply by 2, and add to the current PC List that address 0xf800: 0xf804: 0xf80a: 0xf810: 0xf812: 0xf816: 0xf81a: 0xf81c: 0xf820: 0xf822: 0xf826: 0xf828: 0xf82c: 0xf82e: 0xf832: 0xf836: 4031 40b2 d0f2 430e 43a0 4ec2 531e f03e 120e 403e 122e 8391 23fd 411e 5011 3fef 0300 5a80 0120 000f 0022 09ec 0021 000f 0200 0000 0002 0004 mov.w mov.w bis.b mov.w mov.w mov.b add.w and.w push mov.w push sub.w jne mov.w add.w jmp Lecture 03 - MSP430 ISA #0x0300,sp #0x5a80,&0x0120 #0x000f,&0x0022 #0,r14 #2,0x09ec(r0) r14,&0x0021 #1,r14 #0x000f,r14 r14 #0x0200,r14 @r14 #1,0x0000(r1) $-0x0004 0x0002(r1),r14 0x0004(r0),r1 $-0x0020 47 Instruction Disassembly How to Decode an Operand To decode a source operand: a b c d e f g h i Decode the addressing mode from the “As” bits (00=register, 01=indexed, 10=indirect, or 11=indirect auto-increment) and source register from the “S-Reg” bits If “@R2”, “@R2+”, “R3”, “x(R3)”, “@R3”, or “@R3+”, list appropriate constant preceded by pound sign (ie #1) Else if “x(R0)”, change to symbolic mode, retrieve index (next code word), add index word to PC, increment PC, and list that address as operand (0x8023) Else if “x(R2)”, change to absolute mode, retrieve address (next code word), increment PC, and list address preceded by an ampersand symbol (ie &addr) Else if “@PC+”, change to immediate mode, retrieve immediate value (next code word), increment PC, and list immediate value preceded by the pound symbol (ie #100) Else if register mode, list register (ie Rn) Else if indexed mode, retrieve index (next code word), increment PC, and list index followed by the register in parentheses (ie 0x0200(R4)) Else if indirect mode, list the register preceded by an @ symbol (ie @R4) Else indirect auto-increment mode, list the register preceded by an @ symbol and followed by a plus symbol (ie @R4+) To decode a destination operand, use the “Ad” bit and the destination register bits Follow the same steps as for the source operand (except there will only be register and indexed modes – no constants, immediate, or indirect modes) Lecture 03 - MSP430 ISA 48 Instruction Disassembly Addressing Modes and Constant Generator Address Mode Register Symbolic Indexed Absolute +1 Indirect +4 +2 Immediate Indirect auto-inc +8 -1 As 00 00 01 01 01 01 10 10 10 11 11 11 11 Ad – 1 – – – – – – – – Registers Syntax Operation R0-R2, R4-R15 Rn Register Contents R3 #0 Constant source / bit bucket destination R0 ADDR (PC+next word) points to operand (X(PC)) R1, R4-R15 X(Rn) (Rn+X) points to operand X is next code word R2 &ADDR Next code word is the absolute address (X(SR)) R3 #1 +1 Constant R0-R1,R4-R15 @Rn Rn points to operand R2 #4 +4 Constant R3 #2 +2 Constant R0 #N Next word is the constant N (@PC+) R1,R4-R15 @Rn+ Rn points to operand, Rn is incremented (1 or 2) R2 #8 +8 Constant R3 #-1 -1 Constant Lecture 03 - MSP430 ISA 49 Quiz Quiz Disassemble the following MSP430 instructions: Address 0x8010: 0x8012: 0x8014: 0x8016: 0x8018: 0x801a: 0x801c: 0x801e: 0x8020: 0x8022: 0x8024: 0x8026: 0x8028: 0x802a: 0x802c: 0x802e: Data 4031 0600 40B2 5A1E 0120 430E 535E F07E 000F 1230 000E 8391 0000 23FD 413F 3FF6 Lecture 03 - MSP430 ISA 50 Emulated Instructions as known as Pseudo-Instructions Emulated Instructions Emulated Instructions In addition to the 27 instructions defined by the MSP 430 ISA, there are 24 additional emulated instructions The emulated instructions make reading and writing code more easy, but not have their own op-codes Emulated instructions are replaced automatically with native MSP 430 instructions by assembler There are no penalties for using emulated instructions Lecture 03 - MSP430 ISA 52 Emulated Instructions Emulated Instructions Mnemonic Operation Emulation Description Arithmetic instructions ADC(.B or W) dst dst+Cdst ADDC(.B or W) #0,dst Add carry to destination DADC(.B or W) dst dst+Cdst (decimally) DADD(.B or W) #0,dst Decimal add carry to destination DEC(.B or W) dst dst-1dst SUB(.B or W) #1,dst Decrement destination DECD(.B or W) dst dst-2dst SUB(.B or W) #2,dst Decrement destination twice INC(.B or W) dst dst+1dst ADD(.B or W) #1,dst Increment destination INCD(.B or W) dst dst+2dst ADD(.B or W) #2,dst Increment destination twice SBC(.B or W) dst dst+0FFFFh+Cdst dst+0FFhdst SUBC(.B or W) #0,dst Subtract source and borrow /.NOT carry from dest Lecture 03 - MSP430 ISA 53 Emulated Instructions Emulated Instructions Mnemonic Operation Emulation Description Logical and register control instructions INV(.B or W) dst NOT.dstdst XOR(.B or W) #0(FF)FFh,dst Invert bits in destination RLA(.B or W) dst CMSBMSB-1 LSB+1LSB0 ADD(.B or W) dst,dst Rotate left arithmetically RLC(.B or W) dst CMSBMSB-1 LSB+1LSBC ADDC(.B or W) dst,dst Rotate left through carry BR dst dstPC MOV dst,PC Branch to destination DINT 0GIE BIC #8,SR Disable (general) interrupts EINT 1GIE BIS #8,SR Enable (general) interrupts NOP None MOV #0,R3 No operation RET @SPPC SP+2SP MOV @SP+,PC Return from subroutine Program flow control Lecture 03 - MSP430 ISA 54 Emulated Instructions Emulated Instructions Mnemonic Operation Emulation Description CLR(.B or W) dst 0dst MOV(.B or W) #0,dst Clear destination CLRC 0C BIC #1,SR Clear carry flag CLRN 0N BIC #4,SR Clear negative flag CLRZ 0Z BIC #2,SR Clear zero flag POP(.B or W) dst @SPtemp SP+2SP tempdst MOV(.B or W) @SP+,dst Pop byte/word from stack to destination SETC 1C BIS #1,SR Set carry flag SETN 1N BIS #4,SR Set negative flag SETZ 1Z BIS #2,SR Set zero flag TST(.B or W) dst dst + 0FFFFh + dst + 0FFh + CMP(.B or W) #0,dst Test destination Data instructions Lecture 03 - MSP430 ISA 55 Summary Lecture 03 - MSP430 ISA 56 ... start address end Lecture 03 - MSP430 ISA 40 Disassembling Instructions Convert machine codes into Assembly language instructions Instruction Disassembly How to Disassembly MSP430 Code Begin with... The MCLK (Master) clock signal drives the CPU Lecture 03 - MSP430 ISA 10 MSP430 ISA MSP430 Memory Organization Lecture 03 - MSP430 ISA 11 Instruction Formats MSP430 Instructions There are three... MSP430 ISA Instruction Formats Double Operand Instructions Single Operand Instructions Jump Instructions Addressing Modes Instruction Disassembly Emulated Instructions Lecture 03 - MSP430 ISA Lecture