Kĩ thuật vi xử lý Green_card_v1
Op-code 5h 6h Fh Ch Dh Bh 0001 0010 1b 9h Ah 0010 11b 0010 01b 0011 01b 0011 10b 0011 11b 0011 00b 0010 10b 0010 00b 4h 0001 0010 0b Instruction ADC(.B)* ADD(.B) ADDC(.B) AND(.B) BIC(.B) BIS(.B) BIT(.B) BR* CALL2 CLR(.B)* CLRC* CLRN* CLRZ* CMP(.B) DADC(.B)* DADD(.B) DEC(.B)* DECD(.B)* DINT* EINT* INC(.B)* INCD(.B)* INV(.B)* JC/JHS3 JEQ/JZ3 JGE3 JL3 JMP3 JN3 JNC/JLO3 JNE/JNZ3 MOV(.B) NOP* POP(.B)* PUSH(.B) S-Reg, D-Reg dst src,dst src,dst src,dst src,dst src,dst src,dst dst dst dst src,dst dst src,dst dst dst dst dst dst Label Label Label Label Label Label Label Label src,dst dst src RETI S RET* RLA(.B)* RLC(.B)* dst dst 0001 0001 0b RRA(.B) dst 0001 0000 0b RRC(.B) dst dst 8h 7h 0001 0000 1b SBC(.B)* SETC* SETN* SETZ* SUB(.B) SUBC(.B) SWPB2 0001 0001 1b SXT2 dst Eh TST(.B)* XOR(.B) dst src,dst src,dst src,dst dst Legend: Status bit always cleared Format I Operation dst + C → dst src + dst → dst src + dst + C → dst src and dst → dst not.src and dst → dst src or dst → dst src and dst Branch to … PC + → SP, dst → PC Clear dest Clear carry bit Clear negative bit Clear zero bit dst - src dst + C → dst (decimal) src + dst + C → dst (decimal) dst - → dst dst - → dst disable interrupt enable interrupt Increment destination, dst + → dst Double-Increment destination, dst + → dst Invert destination Jump to Label if Carry-bit is set Jump to Label if Zero-bit is set Jump to Label if (N XOR V) = Jump to Label if (N XOR V) = Jump to Label unconditionally Jump to Label if Negative-bit is set Jump to Label if Carry-bit is reset Jump to Label if Zero-bit is reset src → dst No operation Item from SP, SP + → SP SP - → SP, src → @SP Return from interrupt, TOS → SR, SP + → SP, TOS → PC, SP + → SP Return from subroutine, TOS → PC, SP + → SP Roll (shift) bits to left/Rotate left arithmetically Roll bits to left through Carry Roll (shift) to right arithmetically, i.e., B(n) → B(n-1) → … → B(1) → B(0) → C Roll (shift) to right through Carry, i.e., C → B(n) → B(n-1) → … → B(1) → B(0) → C Subtract carry from destination Set Carry-bit Set Negative-bit Set Zero-bit dst + not.src + → dst dst + not.src + C → dst swap bytes, MSB ↔ LSB Sign extend LSB to 16-bit word, Bit → Bit → … → Bit 15 Test destination src xor dst → dst Status bit always set Format II Status bits Core Inst V N Z C X x x 0 x x x x x x x x - X x x x x x x x x x x x x - X x x x x x x x x x x x x - X x x x x x x x x x x x x - x x x x - - - - mov @SP+, PC x x x x x x x x add dst, dst addc dst, dst x x x x x x x x x x - x x x - x x x - x x x - x x x x x x x x x x x x Status bit cleared or set on results Format III MSP430 Reference Data addc #0, dst BASIC INSTRUCTION FORMATS Format I: Instruction with two operands 15 12 11 Op-code Ad S-reg b/w b/w As D-reg Format II: Instruction with single operand mov dst, PC mov #0, dest bic #1, SR bic #4, SR bic #2, SR addc #0, dst 15 Op-code Ad D/S-reg Format III: Jump Instructions 15 13 12 10 Condition Op-code 10-bit, 2’s complement PC offset REGISTER R0 (PC) R1 (SP) –0– –1– Program Counter Stack Pointer 15 sub #1, dst sub #2, dst bic #8, SR bis #8, SR add #1, dst add #2, dst xor #0FFFFh, dst 0 Program Counter/Stack Pointer R2 (SR/CG1) – – Status Register/Constant Generator 15 Reserved R3 (CG2) Register R2 R2 R2 R2 –3– As 00 01 10 11 V SCG1 SCG0 OSC OFF CPU OFF GIE N Z C Constant Generator Constant (0) 00004h 00008h Remarks Register mode Absolute mode +4, bit processing +8, bit processing Register R3 R3 R3 R3 As 00 01 10 11 Constant 00000h 00001h 00002h 0FFFFh Remarks 0, word processing +1 +2, bit processing -1, word processing R4→R15 – 4→15 – General Purpose registers WTDCTL – 0x0120 – Watchdog timer control register 15 WDTHOLD WDTNMIES Normally 69h; WDTPW = 5Ah for writting WDTNMI WDTTMSEL WDTCNTCL WDTSSEL b1-b0 value: 00/01/10/11: Watchdog clock source/(32768/8192/512/64) mov R3, R3 mov @SP+, dst ADDRESSING MODES As(src) 00 01 01 01 10 11 11 Ad(dst) 1 - Addressing mode Register Mode Indexed Mode Symbolic Mode Absolute Mode Indirect Register Mode Indirect Autoincrement Immediate Mode subc #0, dst bis #1, SR bis #4, SR bis #2, SR cmp #0, dst - Status bit not affected * Emulated Inst Syntax Rn X(Rn) ADDR &ADDR @Rn @Rn+ #N Description Rn Mem(Rn+X) Mem(PC+ADDR) Mem(ADDR) Mem(Rn) Mem(Rn+) #N WDTIS1 WDTIS2