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Lecture 2: The MSP430 Architecture Reading Textbook: Chapter 2: The Texas Instruments MSP430 (20 pages) Chapter 5: Architecture of the MSP430 Processor (60 pages) Lecture Outline MSP430: An Overview in Architecture The MSP430 family Technology Roadmap Typical Applications The MSP430 Documentation MSP430 Architecture Registers Addressing Modes Instruction Set Instruction Formats and Encodings Memory Address Space MSP430 Devices (chips) MSP430’s Clock, WDT, Timer, Comparator, ADC, Digital I/O, USART MSP430 Architecture Lecture Objectives (cont’d) Upon completion this lecture, students will be able to: Describe the MSP430’s register file: R0/PC register R1/SP register R2/SR/CG1 register R3/CG2 register R4-R15 general purpose registers Draw the MSP430’s memory map: Memory Address Space Special function registers Peripherals registers RAM, ROM, flash memory Interrupt and reset vector table MSP430 Architecture Lecture Objectives (cont’d) Upon completion this lecture, students will be able to: Use the MSP430’s addressing modes: Register mode Indexed mode Symbolic mode (PC Relative mode) Absolute mode SP-Relative mode Indirect Register mode Indirect Autoincrement Register Mode Immediate mode Basic Clock System Master clock MCLK Sub-system master clock SMCLK Auxiliary clock ACLK MSP430 Architecture Lecture Objectives (cont’d) Upon completion this lecture, students will be able to: Have a big picture about the MSP430’s instruction set Data Movement Instructions Arithmetic and Logic Instructions with Two Operands Binary Arithmetic Instructions with Two Operands Arithmetic Instructions with One Operand Decimal Arithmetic Logic Instructions with Two Operands Logic Instructions with One Operand Byte Manipulation Operations on Bits in Status Register Shift and Rotate Instructions Flow of Control MSP430 Architecture Lecture Objectives Upon completion this lecture, students will be able to: Have a big picture about the function of MSP430’s WDT, Timer, Comparator, ADC, Digital I/O, USART WatchDog Timer TimerA Comparator Analog Digital Converter Digital I/O Universal Synchronous Asynchronous Receiver Transmitter (USART) MSP430 Architecture The MSP430 Family Broad family of TI’s 16-bit microcontrollers (over 150 different configurations) From KB to 256 KB of flash memory From KB to 120 KB of ROM memory From 128 B to 16 KB of RAM memory With clock rate of KHz, 16 KHz, or 18 KHz MSP430 Architecture The MSP430 Family Non-LCD based subfamilies MSP430x1xx – Flash/ROM based MCUs offering 1.8V to 3.6V operation, up to 60kB, 8MIPS and a wide range of peripherals MSP430F2xx – Flash-based family featuring even lower power and up to16MIPS with 1.8 to 3.6V operation Additional enhancements include ±1% onchip very low power oscillator, internal pull-up/pull-down resistors and low-pin count options MSP430x5xx – New Flash-based family featuring the lowest power consumption up to 25 MIPS with 1.8 to 3.6V operation starting at 12 MIPS Features include an innovative Power Management Module for optimizing power consumption, an internally controlled voltage regulator, and 2x more memory than previous devices LCD based subfamilies MSP430x3xx – Older family of ROM/OTP devices offering 2.5V-5.5V operation, up to 32kB and 4MIPS MSP430x4xx – Flash/ROM based devices offering 1.8V-3.6V operation, up to 120kB/ Flash/ ROM 8MIPS with FLL + SVS along with an integrated LCD controller Ideal for low power metering and medical applications MSP430 Architecture Part numbering convention MSP430MtFaFbMc Mt : Memory type C – ROM, F – Flash, P – OTP, E – EPROM Fa,Fb 10, 11 – basic 12, 13 – HW UART 14 – HW UART, HW multiplier 31, 32 – LCD Controller 33 – LCD controller, HW UART, HW multiplier 41 – LCD controller 43 - LCD controller, HW UART 44 - LCD controller, HW UART, HW multiplier MSP430 Architecture Part numbering convention MSP430MtFaFbMc Mc : Memory capacity 0: Kb ROM, 128 b RAM 1: KB ROM, 128 b RAM 2: KB ROM, 256 b RAM 9: 60 KB ROM, Kb RAM MSP430 Architecture 10 Timing: Basic Clock System Basic Clock Module provides the clocks for the MSP430 processor and peripherals MSP430 Architecture 71 Watchdog Timer WDT module performs a controlled system restart after a software problem occurs • Can serve as an interval timer (generates interrupts) • WDT Control register is password protected • Note: Powers-up active MSP430 Architecture 72 Timer_A Timer_A is a 16-bit timer/counter with three capture/compare registers • Capture external signals • Compare PWM mode • SCCI latch for asynchronous communication MSP430 Architecture 73 Comparator_A Comparator_A is an analog voltage comparator • Supports precision slope analog-to-digital conversions • Supply voltage supervision, and • Monitoring of external analog signals MSP430 Architecture 74 Digital I/O Independently programmable individual I/Os Port1 Port2 Port3 … Port6 yes yes Interrupt Edge Select Register PxIES yes no Interrupt Enable Register PxIE yes no Interrupt Flag Register PxIFG yes no Direction Register PxDIR yes yes Output Register PxOUT yes yes yes yes Function Select Register PxSEL • Up to ports (P1 – P6) • Each has I/O pins • Each pin can be configured as input or output • P1 and P2 pins can be configured to assert an interrupt request Input Register PxIN P1 P2 P3 P4 P5 P6 MSP430 Architecture 75 ADC12 High-performance 12-bit analog-to-digital converter • More than 200 Ksamples/sec • Programmable sample& hold • external input channels • Internal storage MSP430 Architecture 76 USART Serial Port The universal synchronous/ asynchronous receive/transmit (USART) peripheral interface supports two serial modes with one hardware module • UART or SPI (Synchronous Peripheral Interface) modes • Double-buffered • Baud-rate generator MSP430 Architecture 77 Quiz (1/7) The number and types of instructions supported by the MSP430 CPU are: (a) 27 core instructions; (b) 20 core instructions and 14 emulated ones; (c) 27 core instructions and 24 emulated ones; (d) 24 core instructions The MSP430 RISC type CPU is: (a) Based on a reduced instruction set; (b) Based on pure pattern matching and absence of instructions; (c) Based on a complex instruction set; (d) A CPU without peripherals connections 78 Quiz (2/7) The von Neumann architecture considered for the MSP430: (a) Has the data storage entirely contained within the data processing unit; (b) Has physically separate storage and signal pathways for instructions and data; (c) Has a separate bus just for peripherals; (d) Has program, data memory and peripherals all sharing a common bus structure 79 Quiz (3/7) The ALU in the MSP430 CPU handles: (a) Addition, subtraction, multiplication and division operations; (b) Addition, subtraction, comparison and logical (AND, OR, XOR) operations; (c) Addition, subtraction, multiplication and comparison operations; (d) Addition, subtraction, multiplication and logical (AND, OR, XOR) operations 80 Quiz (4/7) The MSP430 CPU incorporates: (a) 14 registers (2 for dedicated functions and 12 for work); (b) 16 registers (6 for dedicated functions and 10 for work); (c) 18 registers (4 for dedicated functions and 14 for work); (d) 16 registers (4 for dedicated functions and 12 for work) The Program Counter (PC): (a) Stores the return addresses of subroutine calls and interrupts; (b) Points to the next instruction to be read from memory and executed by CPU; (c) Stores state and control bits; (d) Points to the next instruction to be written in memory 81 Quiz (5/7) The result of the Status Register SR = 0x0104h indicates: (a) Arithmetic operation result overflows the signed-variable range and produced a carry; (b) Arithmetic operation result overflows the signed-variable range which result is negative; (c) Arithmetic operation result is negative and produced a carry; (d) CPU is disabled and the maskable interrupts are enabled The MSP430 Status Register (SR) bit: (a) V is set when the result of a byte or word operation overflows; (b) Z is set when the result of a byte or word operation is zero; (c) all of the above; (d) none of the above 82 Quiz (6/7) The MSP430 supports: (a) Seven addressing modes for the source operand and four addressing modes for the destination operand; (b) Six addressing modes for the source operand and four addressing modes for the destination operand; (c) Seven addressing modes for the source operand and (plus emulated) addressing modes for the destination operand; (d) Six addressing modes for the source operand and three addressing modes for the destination operand 83 Quiz (7/7) Answers (c) 27 core instructions and 24 emulated instructions (a) Based on a reduced instruction set (d) has program, data memory and peripherals all sharing a common bus structure (b) Addition, subtraction, comparison and logical (OR, AND, XOR) operations (d) 16 registers (4: dedicated functions and 12 working) (b) Points to the next instruction to be read from memory and executed by the CPU (b) Arithmetic operation result overflows the signed-variable range when result is negative (c) all of the above (c) for the source operand and (plus emulated) addressing modes for the destination operand 84 Summary MSP430 Architecture 85