Advanced gate stacks for nano scale CMOS technology

... ADVANCED GATE STACKS FOR NANO- SCALE CMOS TECHNOLOGY WANG XIN PENG (M Eng., Tsinghua University; B Eng., Tsinghua University) A THESIS SUBMITTED FOR THE DEGREE OF DOCTOR ... Developments in Advanced Gate Stacks Involving High-k Dielectrics and Metal Gates Chapter Developments in Advanced Gate Stacks Involving High-k Dielectrics and Metal Gates 2.1 High-k Gate Di...

Ngày tải lên: 15/09/2015, 21:16

... that of the direct tunneling leakage current of 13 - 20 Å at its initial unstressed state higher than that of post-QB leakage in thicker oxides Due to this high gate leakage for ultra- thin oxides, ... Device Scaling and Dielectric Performance 23 2.5 Ultra- thin oxide Reliability 24 2.6 High- K Dielectrics Reliability 27 2.6.1 High- K charge trapping 28 2.6.2...

Ngày tải lên: 16/09/2015, 17:12

... FABRICATION OF ULTRA- SHALLOW JUNCTIONS AND ADVANCED GATE STACKS FOR ULSI TECHNOLOGIES USING LASER THERMAL PROCESSING CHONG YUNG FU (B A Sc (First Class Hons.), NTU) A THESIS SUBMITTED FOR ... fabricate ultra- shallow p+/n junctions and advanced poly-Si gate stacks for ultra- large scale integration technologies LTP of ultra- shallow ju...

Ngày tải lên: 12/09/2015, 11:29

... 1. 2 -1. 6 0. 9 -1. 3 0. 8 -1. 2 0. 7 -1. 1 Gate leakage at 10 0 oC for high performance (A/cm2) 2 70 4 ,00 0 17 ,00 0 54 ,00 0 1 10 , 000 Gate leakage at 10 0 oC for lowoperating-power (A/cm2) 0. 57 2 .19 4.55 18 .75 90. 9 Gate ... 22 16 11 EOT for high-performance (nm) 0. 9 -1. 4 0. 6 -1. 1 0. 5 -0. 8 0. 4 -0. 6 0. 4 -0. 5 EOT for low-operating-power (nm) 1....

Ngày tải lên: 15/09/2015, 21:16

... Metal gate/ SiO2 stack (b) Metal gate/ high-k stack Metal gate High-k dielectric SiO2 Si substrate SiO2 Si substrate Fig 1.3 An illustration of (a) metal gate/ SiO2 and (b) metal gate/ high-k stacks formed ... Typical gate leakage and (b) breakdown voltage showed better characteristics for NiSi gate stack incorporating a YIL and a TbIL A RTA at 950ºC was conducted before FUS...

Ngày tải lên: 11/09/2015, 16:01

... step of gate stack etching to silicidation of gate stacks with Hf based high-K gate dielectrics are summarized Fig 1.8 Integration issues from gate stack etching to silicidation of gate stacks ... Metal gate Gate dielectric Selectivity of PR to metal gate Selectivity of metal gate to dielectric and optical emission trace endpoint Si Fig 1.11 Illustratio...

Ngày tải lên: 16/09/2015, 08:30

... SCHOTTKY BARRIER ENGINEERING FOR CONTACTS IN ADVANCED CMOS TECHNOLOGY PHYLLIS LIM SHI YA (B ENG (HONS.)), NATIONAL UNIVERSITY OF SINGAPORE A THESIS SUBMITTED FOR THE DEGREE OF ... in CMOS technology 14 1.6 Modulation of Schottky barrier height 16 1.6.1 S/D material engineering 16 1.6.2 Dopant segregation engineering 17 1.6.3 Interface engineering ... of Ge...

Ngày tải lên: 09/09/2015, 10:21

... dielectric, such as high- k gate dielectric, the physical thickness of the high- k (thigh -k) employed to the EOT can be obtained form the expression: Ch Introduction EOT thigh k = k SiO2 khigh k (1-4) or ... high- k gate dielectrics for advanced CMOS application Several approaches presented in this thesis can be used to effectively solve the major challenges for...

Ngày tải lên: 14/09/2015, 17:46

... replacement for SiO2, the present work is aimed at exploring the feasibility of using atomic layer deposited (ALD) Hf -based materials as gate dielectrics in deep sub- 0.1 µm CMOS technology As ... Alternating Current ADF Annular Dark Field AFM Atomic Force Microscopy ALCVD Atomic Layer Chemical Vapor Deposition ALD Atomic Layer Deposition ALE Atomic Layer Ep...

Ngày tải lên: 30/09/2015, 14:23

... NOVEL III- V MOSFET INTEGRATED WITH HIGH- K DIELECTRIC AND METAL GATE FOR FUTURE CMOS TECHNOLOGY Jianqiang Lin 2009 NOVEL III- V MOSFET INTEGRATED WITH HIGH- K DIELECTRIC AND METAL GATE FOR FUTURE ... 2006 [1.38] I Ok, H Kim, M Zhang, T Lee, F Zhu, L Yu, S Koveshnikov, W Tsai1 ,V Tokranov, M Yakimov, S Oktyabrsky, and J.C Lee “Self-Al...

Ngày tải lên: 16/10/2015, 15:37

... DEVELOPMENT OF HIGH MOBILITY CHANNEL LAYER FORMATION TECHNOLOGY FOR HIGH SPEED CMOS DEVICES OH Hoon Jung (B Sc., Ewha Womans University, Korea) ... the use of new gate stack materials Thus this work of development of high mobility channel layer formation technology has been carried out for the innovative change The subsequent sections in ... pro...

Ngày tải lên: 11/09/2015, 10:00

... STUDY ON HIGH MOBILITY CHANNEL TRANSISTORS FOR FUTURE SUB- 10 nm CMOS TECHNOLOGY Fei GAO (B Eng, Xi’an Jiaotong University, PR CHINA) A THESIS SUBMITTED FOR THE DEGREE OF DOCTOR ... strained high- Ge concentration SGOI is successfully demonstrated by two-step oxidation of sputtered low Ge content α-SiGe (amorphous SiGe) on a SOI substrate Compared with convention...

Ngày tải lên: 12/09/2015, 08:16

... metal-oxide-semiconductor (CMOS) scaling requires the development of new materials and device architectures This dissertation focuses on introducing lanthanoid based materials into CMOS technology to address ... optimization of lanthanoid based materials for applications in advanced CMOS technology 1.4 Thesis Organization The main issues discussed in this thesis ar...

Ngày tải lên: 14/09/2015, 08:36

... SCHOTTKY SOURCE/ DRAIN TRANSISTOR INTEGRATED WITH HIGH- K AND METAL GATE FOR SUB- TENTH NM TECHNOLOGY LI RUI (B Sc., Univ of Science and Technology of China, CHINA) A THESIS SUBMITTED FOR THE ... integration of germanide Schottky source/ drain Ge channel MOSFET with high- k gate dielectric and metal gate for sub- tenth nm technology...

Ngày tải lên: 14/09/2015, 14:04