Advanced gate stack for CMOS nanotechnology

METAL GATE TECHNOLOGY FOR ADVANCED CMOS GATE STACKS LIM EU-JIN ANDY NATIONAL UNIVERSITY OF SINGAPORE 2008 METAL GATE TECHNOLOGY FOR ADVANCED CMOS GATE STACKS LIM EU-JIN ANDY (B. ENG.) NATIONAL UNIVERSITY OF SINGAPORE A THESIS SUBMITTED FOR THE DEGREE OF DOCTOR OF PHILOSOPHY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING NATIONAL UNIVERSITY OF SINGAPORE AUG 2008 Acknowledgements First and foremost, I would like to express my utmost gratitude and appreciation to my research advisor, Dr. Yeo Yee-Chia who has guided me throughout my Ph.D. candidature. I am thankful to Dr. Yeo for sharing his knowledge, and giving me his support and patience during these four years. He has always been there to give insights into my research work and I have greatly benefited from his guidance. I would also like to express my sincere appreciation to my co-advisor, Prof. Kwong Dim-Lee. Prof. Kwong has always been encouraging in my research work, and has provided valuable advice throughout my course. I am also grateful to Prof. Ganesh Samudra for sitting on my thesis advisory committee and providing valuable feedback and suggestions, especially during our group meetings. I would like to express appreciation to Agency for Science, Technology and Research (A*STAR) for funding my graduate studies through a graduate scholarship award. I would also like to acknowledge the efforts of the technical staff in Silicon Nano Device Laboratory (SNDL) specifically Mr Yong Yu Fu, Mr O Yan Wai Linn, Patrick Tang, and Lau Boon Teck in providing efficient technical and administrative support for my research work. Appreciation also goes out to Institute of Microelectronics (IME) and Institure of Materials Research, and Engineering (IMRE) for the use of their equipment for materials characterization work. I am grateful for the friends I have met in SNDL in particular, my buddy Rinus. It has been great fun working with you and I really appreciate your help, especially during the initial phase of my course when I was working on silicide gates. I would also like to thank Ren Chi, Xin Peng, Wan Sik, King Jien, Kah Wee, Kian Ming, Jason, Shen i Chen, Whang Sung Jin, Wei-Feng, Hoong Shing, Lina, Alvin, Fangyue, Shao Ming, Hock Chun, and many others for their useful discussions, assistance and friendships throughout my candidature. My deepest gratitude goes out to my parents who have given me their support and encouragement during my studies. Most importantly, a special “Thank you!” goes out to my dearest Fei who has been always there unconditionally with her love and support throughout these years. ii Table of Contents Acknowledgements i Table of Contents . iii Abstract vi List of Tables . viii List of Figures ix List of Symbols xix Chapter Introduction 1.1 Overview for CMOS Scaling . 1.2 Why Metal Gate Electrodes? 1.2.1 Current Status of Metal Gate Technology 1.2.2 Work Function Extraction Method . 1.3 Objective of Research . 10 1.4 Thesis Organization 11 1.5 References 13 Chapter Nickel Alloying for Fully-Silicided or Fully-Germanided Metal Gate Work Function Modulation 2.1 Introduction 19 2.2 Experiment . 21 2.3 Results and Discussion . 22 2.3.1 Nickel-Terbium Alloy for Fully-Silicided Gate . 2.3.2 Nickel-Aluminum Alloy for Fully-Silicided and Fully-Germanided 22 Gate . 31 2.4 Summary 40 2.5 References . 42 iii Chapter Novel Rare-earth Based Interlayers for Wide NMOS Work Function Tunability in Nickel Fully-Silicided Gate 3.1 Introduction 46 3.2 Experiment . 47 3.3 Results and Discussion . 49 3.3.1 Electrical and Material Characterization of Rare-earth based Interlayer 49 3.3.2 Proposed Interfacial Dipole Model . 60 3.3.3 Integration in HfO2/SiO2 Dielectric Stack 64 3.4 Summary . 68 3.5 References 69 Chapter Manipulating Interface Dipoles of Opposing Polarity for Work Function Engineering 4.1 Introduction 74 4.2 Experiment . 75 4.3 Results and Discussion . 78 4.3.1 Opposing Interface Dipoles in TaN/SiO2 Gate Stack 78 4.3.2 Opposing Interface Dipoles in TaN/High-k Gate Stack . 87 4.3.3 Utilization of Aluminum-Incorporated Metal Gates for Reversal of n-type Dipole 91 4.4 Summary . 100 4.5 References 101 Chapter Interdiffusion of Thin Metallic Layers for Metal Gate Work Function Control 5.1 Introduction 105 5.2 Experiment . 106 5.3 Results and Discussion . 109 5.3.1 Gate Work Function Dependence on Metal Thickness 109 iv 5.3.2 Gate Work Function Dependence on Annealing Temperature . 113 5.3.3 Work Function Modulation on HfO2 and HfLaOx Dielectric . 116 5.4 Summary . 119 5.5 References 120 Chapter Conclusions and Future Work 6.1 Conclusion 6.1.1 123 Nickel Alloying for Fully-Silicided or Fully-Germanided Metal Gate Work Function Modulation . 124 6.1.2 Novel Rare-earth Based Interlayers for Wide NMOS Work Function Tunability in Nickel Fully-Silicided Gate . 6.1.3 124 Manipulating Interface Dipoles of Opposing Polarity for Work Function Engineering 125 6.1.4 Interdiffusion of Thin Metallic Layers for Metal Gate Work Function Control 126 6.2 Suggestions for Future Work . 127 6.3 References . 129 Appendix A. Publication List 130 v Abstract Aggressive complementary metal-oxide-semiconductor (CMOS) scaling requires metal gate/high-k dielectric gate stacks for enhanced device performance in sub-45 nm technology nodes. The elimination of polysilicon gate depletion effect and reduction in gate leakage are major advantages of metal gate/high-k gate stacks over conventional polysilicon/SiO(N) gate stacks. However, achieving the desired effective metal gate work function (Φm) to meet threshold voltage requirements in future CMOS devices is one of the main hurdles for implementation. Full silicidation of a polysilicon gate electrode with nickel (Ni) is an attractive metal gate option due to its simplicity and compatibility with current CMOS process. In this work, novel methods were explored to modulate the mid-gap Φm (~4.65 eV) of Ni fully-silicided (Ni-FUSI) gate. Ni-alloying with either terbium (Tb), or aluminum (Al) achieved a FUSI gate Φm lowering of about ~0.2 – 0.3 eV. Ni-Al alloy further reduced the Φm of a Ni fully-germanided gate by ~0.6 eV. The change in gate crystallinity and the segregation of elemental Al were the mechanisms responsible for the gate Φm shifts using Ni-Tb and Ni-Al alloy, respectively. To widen the Ni-FUSI gate Φm tunability range, an alternative technique using ultra-thin rare-earth (RE) silicate interlayers was employed. Conduction band-edge gate Φm of ~3.8 – 4.1 eV were obtained through the formation of the interlayers on SiO2. A proposed interface rare-earth–oxygen (RE-O) dipole model exhibited excellent correlation between the modulated Φm values and the calculated RE-O dipole magnitudes. Additional factors like interlayer thickness, nickel vi silicide phase and RE position (for interlayer formation) in a high-k stack were found to influence the effective gate Φm significantly. Two distinct metal gate Φm tuning methods were also investigated for dual metalgate integration. Firstly, the manipulation of n- and p-type interface dipoles for Φm engineering within the same metal gate stack was explored. Continuous Φm tunability was attained through the modulation of dipole magnitude and polarity by combining Tb (n-type) and Al (p-type) –induced interface dipoles in a single metal gate stack. Dipole formation hinges critically on the reaction of Tb or Al with SiO2 (or underlying SiO2 for high-k dielectric stacks). We also show, for the first time, that the net interface dipole polarity in a metal gate stack can be reversed through the incorporation of dipoles with opposite polarity and control of the subsequent annealing conditions. Secondly, the interdiffusion of elemental metals or metal alloys not more than 10 nm thick was examined for gate Φm control. Φm modulation was successfully achieved using these thin layers, which allowed better spatial uniformity and ease of process integration for dual metal gate technology. Metal thickness ratios before interdiffusion and annealing temperatures were also crucial in determining the final Φm value. The exploration of novel metal gate materials and Φm tuning techniques provides new avenues for future metal gate/high-k gate stack engineering in scaled CMOS technology nodes. vii List of Tables Table 1.1 Table 3.1 Table 3.2 Table 4.1 Table 5.1 A summary of different metal gate integration approaches for CMOS devices. The RE metals used in this work are listed below with their respective sputtering power and sputtering times. A working pressure of mTorr was used during sputtering. . 49 Net electronegativity difference (Δχ) of RE and O atoms, the sum their ionic radii (dRE-O), and Δχ × dRE-O are tabulated [3.22]. The ionic radius of trivalent RE ion (3+) with coordination number of is used. The relative magnitude of RE-O dipole moment μ can be estimated by Δχ × dRE-O. χ and ionic radius of O is 3.44 and 1.4, respectively. 63 Thicknesses of Tb, Al, and AlTb films (TTb, TAl, and TAlTb) which were deposited by sputtering or co-sputtering at a working pressure of mTorr. A sputtering power of 60 and 80 W was used for Tb and Al, respectively. A surface profiler was used to estimate the IL metal deposition rates for thickness calculations. . 77 Metal layers, thicknesses and thickness ratios used in this work. The Metal layer is formed on the Metal layer. The bottommost Metal layer was either a high work function metal layer (shaded rows), or a low work function metal alloy layer (unshaded rows). 107 viii 700°C RTA give a lower VFB on HfLaOx than on HfO2. This was similarly observed with different underlying SiO2 thicknesses and annealing temperatures (500 and 600°C). The extracted Φm are summarized in Fig. 5.10 which shows that the gate Φm on HfLaOx consistently gave a lower value than on HfO2 for the same metal gate stack. Therefore, La incorporation into HfO2 affects the gate Φm significantly. A plausible reasoning for our observation is the formation of a dipole at the HfLaO/SiO2 interface based on our results in Chapters and 4. Fixed charge in HfLaOx cannot account for the significant Φm shift, as we found that the addition of La into HfO2 did not generate a large amount of fixed charges. In Fig. 5.10, the Φm values of Pt on HfO2 and HfLaOx are both lower than the vacuum Φm value of Pt (5.65 eV), suggesting the existence of Fermi-level pinning [5.14], [5.15]. From Fig. 5.10, we observe Φm tunability between Hf/Pt and Pt stack, of ~0.3 – 0.4 eV for HfO2, and ~0.5 eV for HfLaOx. This gate Φm range is suitable for transistors with advanced structures such as ultra-thin body (UTB) fully-depleted (FD) SOI or multiple-gate structures [5.16]. With Metal and Metal thickness optimization, appropriate gate Φm values for advanced NMOS and PMOS transistors could be achieved using the proposed dual gate integration scheme. 117 (a) 1.0 C/Cox 0.8 0.6 Hf/Pt on HfO2 0.4 0.2 0.2 After 700°C RTA -1.5 -1.0 -0.5 0.0 Gate Voltage VG (V) After 700°C RTA 0.5 Pt on HfLaOx 0.6 0.4 0.0 -2.0 (b) 0.8 Pt on HfO2 C/Cox 1.0 Hf/Pt on HfLaOx 0.0 -2.0 -1.5 -1.0 -0.5 0.0 Gate Voltage VG (V) 0.5 Fig. 5.9 C-V curves of interdiffused Hf/Pt stacks on (a) HfO2/SiO2 and (b) HfLaOx/SiO2 after 700°C RTA shows Φm tunability from single layer Pt stack. Work Function (eV) 5.2 Pt stack 5.0 4.8 4.6 4.4 4.2 HfO2 4.0 HfLaOx Hf/Pt stack 500 600 700 RTA Temperature (°C) Fig. 5.10 Φm values for Pt and Hf/Pt stacks after 500 – 700°C RTA on both HfO2 and HfLaOx dielectrics. Φm modulation over Pt stack was attained through metal interdiffusion of Hf/Pt stack for both dielectrics. 118 5.4 Summary Gate work function (Φm) modulation through the interdiffusion of thin metallic layers with thicknesses less than or equal to 10 nm was demonstrated on SiO2 and high-k dielectrics (HfO2 and HfLaOx). The thin metallic layers were either elemental metals (Ni, Pt and Hf), or metal alloys (Ni-Hf and Pt-Hf). For a bilayer stack comprising of Hf on Ni (Hf/Ni stack), varying the Hf/Ni metal thickness ratio from (single-layer Ni stack) to 1.4 achieved Φm tunability from 4.74 to 4.2 eV after forming gas anneal (FGA) at 420°C. In contrast, a Ni on Ni-Hf bilayer stack (Ni/Ni-Hf stack) did not achieve sufficient interdiffusion to modulate the gate Φm. By replacing Ni with Pt, more thermally stable Hf/Pt and Pt/Pt-Hf stacks were annealed at higher temperatures for metal interdiffusion. A higher thermal budget was evidently shown to have facilitated interdiffusion which resulted in a larger Φm shift, in comparison to the Φm values of their respective singe layer stacks. For example, the largest Φm shift of ~0.5 eV was obtained for both Hf/Pt and Pt/Pt-Hf stacks after annealing at 700ºC for 30 s. The correlation between Φm tunability and metal interdiffusion was clearly supported either by SIMS, or XPS depth profiling of the gate stacks. The Hf/Pt stack was further employed to demonstrate Φm tunability of thin interdiffused metal layers on high-k gate dielectrics. Φm range of ~0.3 – 0.4 eV and ~0.5 eV was obtained for HfO2 and HfLaOx dielectrics, respectively, between interdiffused Hf/Pt stack and single layer Pt stack after annealing. Through process optimization, the interdiffusion of thin metallic layers for precise Φm control could be implemented on advanced transistors using a dual gate stack integration scheme. 119 5.5 References [5.1] I. Polishchuk, P. Ranade, T.-J. King, and C. Hu, “Dual work function metal gate CMOS technology using metal interdiffusion,” IEEE Electron Device Letters, vol. 22, no. 9, pp. 444–446, 2001. [5.2] J. Lee, H. Zhong, Y.-S. Suh, G. Heuss, J. Gurganus, B. Chen, and V. Misra, “Tunable work function dual metal gate technology for bulk and non-bulk CMOS,” International Electron Device Meeting Tech. Dig., pp. 359–362, 2002 [5.3] T. Matsukawa, Y. X. Liu, M. Masahara, K. Ishii, K. Endo, H. Yamauchi, E. Sugimata, H. Takashima, T. Higashino, E. Suzuki, and S. Kanemaru, “Work function controllability of metal gates made by interdiffusing metal stacks with low and high work functions,” Microelectronic Engineering, vol. 80, pp. 284–287, 2005. [5.4] C.-H. Lu, G. M. T. Wong, M. D. Deal, W. Tsai, P. Majhi, C. O. Chui, M. R. Visokay, J. J. Chambers, L. Colombo, B. M. Clemens, and Y. Nishi, “Characteristics and mechanism of tunable work function gate electrodes using a bilayer metal structure on SiO2 and HfO2,” IEEE Electron Device Letters, vol. 26, no. 7, pp. 445–447, 2005. [5.5] M. DiBattista, and J. W. Schwank, “Determination of diffusion in polycrystalline platinum thin films,” Journal of Applied Physics, vol. 86, no. 9, pp. 4902–4907, 1999. [5.6] K. J. Yang, Y. C. King, and C. Hu, “Quantum effect in oxide thickness determination from capacitance measurement,” Symposium on VLSI Technology, pp. 77–78, 1999. [5.7] D.-G. Park, Z. J. Luo, N. Edleman, W. Zhu, P. Nguyen, K. Wong, C. Cabral, P. Jamison, B.H. Lee, A. Chou, M. Chudzik, J. Bruley, O. Gluschenkov, P. Ronsheim, A. Chakravarti, R. Mitchell, V. Ku, H. Kim, E. Duch, P. Kozlowski, C. D. Emic, V. Narayanan, A. Steegen, R. Wise, R. Jammy, R. Rengarajan, H. Ng, A. Sekiguchi, and C.H. Wann, “Thermally robust dual-work function ALD-MNx MOSFETs using conventional CMOS process flow,” Symposium on VLSI Technology, pp. 186–187, 2004. 120 [5.8] C. Cabral, Jr., C. Lavoie, A. S. Ozcan, R. S. Amos, V. Narayanan, E. P. Gusev, J. L. Jordan-Sweet, and J. M. E. Harper, “Evaluation of thermal stability for CMOS gate metal materials,” Journal of The Electrochemical Society, vol. 151, no. 12, F283– F287, 2004. [5.9] I. S. Jeon, J. Lee, P. Zhao, P. Sivasubramani, T. Oh, H. J. Kim, D. Cha, J. Huang, M. J. Kim, B. E. Gnade, J. Kim, and R. M. Wallace, “A novel methodology on tuning work function of metal gate using stacking bi-metal layers,” International Electron Device Meeting Tech. Dig., pp. 303–306, 2004. [5.10] E. Cartier, F. R. McFeely, V. Narayanan, p. Jamison, B. P. Linder, M. Copel, V. K. Paruchuri, V. S. Basker, R. Haight, D. Lim, R. Carruthers, T. Shaw, M. Steen, J. Sleight, J. Rubino, H. Deligianni, S. Guha, R. Jammy, and G. Shahidi, “Role of oxygen vacancies in VFB/Vt stability of pFET metals on HfO2,” Symposium on VLSI Technology, pp. 230– 231, 2005. [5.11] G. D. Wilk, R. M. Wallace, and J. M. Anthony, “High-k gate dielectrics: Current status and materials properties considerations,” Journal of Applied Physics, vol. 89, no. 10, pp. 5243–5274, 2001. [5.12] X. P. Wang, M. –F. Li, C. Ren, X. F. Yu, C. Shen, H. H. Ma, A. Chin, C. X. Zhu, J. Ning, M. B. Yu, and D.-L. Kwong, “Tuning effective metal gate work function by a novel gate dielectric HfLaO for nMOSFETs,” IEEE Electron Device Letters, vol. 27, no. 1, pp. 31– 34, 2006. [5.13] R. Jha, J. Gurganos, Y. H. Kim, R. Choi, J. Lee, and V. Misra, “A capacitance-based methodology for work function extraction of metals on high-k,” IEEE Electron Device Letters, vol. 25, no. 6, pp. 420–423, 2004. [5.14] Y.-C. Yeo, T.-J. King, and C. Hu, “Metal-dielectric band alignment and its implications for metal gate complementary metal-oxide-semiconductor technology,” Journal of Applied Physics, vol. 92, no. 12, pp. 7266–7271, 2002. 121 [5.15] H. Y. Yu, C. Ren, J. F. Kang, X. P. Wang, H. H. H. Ma, M.-F. Li, D. S. H. Chan, Y.-C. Yeo, and D.-L. Kwong, “Fermi-pinning induced thermal instability of metal-gate work functions,” IEEE Electron Device Letters, vol. 25, no. 5, pp. 337–339, 2004. [5.16] I. De, D. Johri, A. Srivastava, and C.M. Osburn, “Impact of gate work function on device performance at the 50 nm technology node,” Solid-State Electronics, vol. 44, no. 6, pp. 1077–1080, 2000. 122 Chapter Conclusions and Future Work 6.1 Conclusions The integration of metal gate/high-k dielectric gate stack is imperative for superior device performance and was initially projected for production in the 65 nm CMOS technology node. This has now been delayed to the 45 nm node and beyond due to various issues such as the choice of materials and process flow, tunability and optimization of dual gate Φm, and reliability of the gate stack [6.1]. Thus far, only Intel has started high volume manufacturing of products based on a 45 nm process node with a metal gate/high-k gate stack [6.2]. However, whether Intel’s metal gate/high-k scheme, which uses a replacement-gate (gate-last) approach, will be adopted in its sub-45 nm nodes remains to be seen. Other leading-edge semiconductor manufacturers are also expected to start production of their 45 nm technology nodes this year, but have yet to announce the new materials they will adopt [6.3]. It is believed that some companies are delaying the incorporation of a metal gate/high-k stack to later technology nodes. The revolutionary change of the MOSFET gate stack is by no means a trivial process. Immense efforts and continuous developments have to be made to ensure a smooth transition. This thesis has studied specific areas in metal gate technology that may provide insights for future integration in subsequent CMOS nodes. The main contributions of this thesis are summarized below. 123 6.1.1 Nickel Alloying for Fully-Silicided or Fully-Germanided Metal Gate Work Function Modulation This chapter investigated the possibility of using Ni-alloys during silicidation for NMOS Φm modulation of Ni fully-silicided (Ni-FUSI) gates. Low Φm metals, namely terbium (Tb), or aluminum (Al) were alloyed with Ni at varying atomic concentrations. The difference in silicidation kinetics of the low Φm metals and Ni affected the FUSI gate formation significantly. Using a Ni-Tb alloy, a dual layered NixTbySiz/NiSi FUSI gate was formed, as Tb remained relatively immobile during the gate silicidation process. A lowering in the FUSI gate Φm to ~4.4 eV was attributed to a decrease in crystallinity of the bottom layer NiSi gate. The use of a Ni-Al alloy resulted in a FUSI gate Φm of ~4.4 eV due to Al segregation at the gate/dielectric interface. Further employment of the NiAl alloy in a fully-germanided (FUGE) gate obtained a Φm decrease of ~0.6 eV, as compared to a NiGe gate (~5.0eV). Despite the presence of low Φm Al (~4.25 eV) at the gate/dielectric interface, the inability to further lower the Φm to that of pure Al was due to Fermi-pinning from the formation of interfacial Al2O3 at the gate/SiO2 interface. The Φm values attained by Ni-alloying are suitable for transistors with advanced structures, but other Φm techniques would be required to extent the gate Φm tunability range towards the Si band-edges for high performance logic technology. 6.1.2 Novel Rare-earth Based Interlayers for Wide NMOS Work Function Tunability in Nickel Fully-Silicided Gate In this chapter, we exploit rare-earth (RE) –based silicate interlayers to engineer the Φm of Ni-FUSI gates on SiO2 dielectrics to silicon conduction band-edge. RE metals 124 comprising yttrium (Y), erbium (Er), dysprosium (Dy), terbium (Tb), gadolinium (Gd), ytterbium (Yb) or lanthanum (La) modulated the Ni-FUSI gate Φm to a varying degree from ~3.8 to 4.1 eV. Variation in interlayer thickness (up to a critical thickness of ~1 nm) and Ni-silicide phase are both able to further tune the gate Φm. This is an attractive Φm tuning method due to improvements in electrical characteristics after interlayer incorporation which was concurrently obtained with an equivalent oxide thickness scaling. The modulation of Ni-FUSI gate Φm was attributed to the presence of interfacial rare-earth–oxygen (RE–O) dipoles. A proposed RE-O interface dipole model showed excellent correlation of the modulated NiSi gate Φm values with the calculated RE–O dipole magnitudes. Further incorporation of a La-based interlayer into a high-k stack indicated that the formation of an interface dipole at the HfO2/SiO2 interface dominated the effective gate Φm. This result is noteworthy for attaining band-edge Ni-FUSI gate Φm on high-k dielectric stacks. 6.1.3 Manipulating Interface Dipoles of Opposing Polarity for Work Function Engineering within a Single Metal Gate Stack In the previous chapter, it was demonstrated that an n-type interface dipole layer was able to modulate the NiSi metal gate Φm. There has been increasing reports on using interface dipole layers to pin the metal gate Φm either for NMOS, or PMOS tunability. Therefore, a more comprehensive evaluation and understanding of this interfacial phenomenon is crucial for CMOS integration. In this work, Tb-induced (n-type) and Alinduced (p-type) dipoles were incorporated within the same gate stack for TaN metal gate Φm engineering. The TaN gate Φm, can be continuously tuned by controlling Tb- and Al- 125 induced dipole densities. Tb-O-Si and Al-O-(Si) bond formation in the dielectric stack was essential in determining the dominant interface dipole when both elements are present. Most importantly, we show the modulation of a TaN Φm, initially pinned by an n-type dipole, by the formation of p-type dipoles after a 950ºC anneal. The incorporation of Al from Al-containing metal gates into the gate dielectric stack to form p-type dipoles was further demonstrated. The manipulation of dipoles with opposing polarity would allow novel ways in integrating dipole layers for achieving low threshold voltage CMOS transistors. 6.1.4 Interdiffusion of Thin Metallic Layers for Metal Gate Work Function Control Finally, the interdiffusion of thin metallic layers (thicknesses less than or equal to 10 nm) was explored for Φm modification. Elemental metals (nickel, platinum and hafnium), or metal alloys (nickel-hafnium and platinum-hafnium) were used for the interdiffusion, and Φm tunability of up to ~0.5 eV, between single layer and interdiffused stacks, was achieved on both SiO2 and high-k gate dielectrics. This Φm range is suitable for transistors with advanced structures. The metal thicknesses before interdiffusion, as well as the interdiffusion annealing conditions can be calibrated accurately to tailor to the desired metal gate Φm. The application of thin metal layers is sufficient for gate Φm control, and provides better uniformity and ease of process. The interdiffusion of thin metallic layers also avoids exposing the gate dielectric during metal etching and is a feasible and attractive dual metal gate scheme. 126 6.2 Suggestions for Future Work The work in this thesis has been very exploratory and more detailed investigation and rigorous characterization will be necessary to determine the potential in applying these methods or concepts in coming technology nodes. Suggestions for future work will be directly or indirectly related to the work described earlier in this thesis. In Chapter 2, NMOS Φm tunability for Ni-FUSI gates was limited due to the difficulty in getting the low Φm metals at the interface. Further investigation can be conducted to circumvent this problem such as reducing the silicon gate height to facilitate the diffusion of the low Φm metals towards the gate/dielectric interface. In addition, possible dual gate integration schemes using two different Ni-alloys for NMOS and PMOS gate Φm control should be conducted. In Chapter 3, conduction band-edge FUSI gate Φm was attained by forming an n-type dipole layer before the Si gate deposition. Such a process flow would include the n-type dipole layer at the PMOS regions, and techniques to individually tune the Ni-FUSI gate Φm to the band-edges for CMOS NiFUSI gate integration should be developed. The segregation of implanted rare-earth metal and Al in FUSI gates is a possible way to tune NMOS and PMOS Φm, respectively. The modulation of the Schottky barrier height by introducing RE metals [6.4] and Al [6.5] in nickel silicided source/drain (S/D) has also been reported. A promising and novel integration scheme would include the segregation these implanted species in the gate, source and drain simultaneously in either an NMOS, or a PMOS to modulate the gate Φm and S/D barrier height concurrently. For Chapter 4, only X-ray photoelectron spectroscopy (XPS) was used to observe bonding chemistry of Al and Tb after PDA. It would be good if other characterization 127 methods such as electron energy loss spectroscopy (EELS) can be used to directly probe the completed gate stack for more atomic-level chemical bonding information to complement the XPS data. The incorporation of Al from the metal gates to reverse ntype dipole pinning is an attractive way for CMOS integration. However, further work must be done in terms of reliability in such a gate stack to ascertain its feasibility. For Chapter 5, metals were selected solely on their Φm values and novelty in a metal interdiffusion scheme. However, they may not be the most suitable metals in terms of thermal stability, adhesion and processing (e.g. deposition or etching). Therefore, based on current evaluation of metal gate materials, these factors should be considered during material selection for further implementation of this scheme in dual gate integration. Investigation should also be conducted on the possible adverse effects after the interdiffusion on the metals into the gate dielectric. 128 6.3 References [6.1] International Technology Roadmap for Semiconductor, Semiconductor Industry Association, 2007. [6.2] K. Mistry, C. Allen, C. Auth, B. Beattie, D. Bergstrom, M. Bost, M. Brazier, M. Buehler, A. Cappellani, R. Chau, C. H. Choi, G. Ding, K. Fischer, T. Ghani, R. Grover, W. Han, D. Hanken, M. Hattendorf, J. He, J. Hicks, R. Huessner, D. Ingerly, P. Jain, R. James, L. Jong, S. Joshi, C. Kenyon, K. Kuhn, K. Lee, H. Liu, J. Maiz, B. Mclntyre, P. Moon, J. Neirynck, S. Pae, C. Parker, D. Parsons, C. Prasad, L. Pipes, M. Prince, R. Ranade, T. Reynolds, J. Sandford, L. Shifren, J. Sebastian, J. Seiple, D. Simon, S. Sivakumar, P. Smith, C. Thomas, T. Troeger, P. Vandervoorn, S. Williams, and K. Zawadzki, “A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging,” International Electron Device Meeting Tech. Dig., pp. 247–250, 2007. [6.3] D. James, “From strain to high-k/metal gate – the 65–45nm transistion,” IEEE/SEMI Advanced Semiconductor Manufacturing Conference, pp. 76 – 81, 2008. [6.4] R.T.-P. Lee, A.T.-Y. Koh, F. Y. Liu, W.-W. Fang, T.-Y. Liow, K.-M. Tan, P.-C. Lim, A.E.-J. Lim, M. Zhu, K.-M. Hoe, C.-H. Tung, G.-Q. Lo, X. Wang, D.K.-Y. Low, G.S. Samudra, D.-Z. Chi, and Y.-C. Yeo, “Route to Low Parasitic Resistance in MuGFETs with Silicon-Carbon Source/Drain: Integration of Novel Low Barrier Ni(M)Si:C Metal Silicides and Pulsed Laser Annealing,” International Electron Device Meeting Tech. Dig., pp. 685–688, 2007. [6.5] M. Sinha, E. F. Chor, and Y. C. Yeo, “Tuning the Schottky barrier height of nickel silicide on p-silicon by aluminum segregation,” Applied Physics Letters, vol. 92, 222114, 2008. 129 Appendix A. List of Publications Journal Publications [1] A. E.-J. Lim, R. T. P. Lee, C. H. Tung, S. Tripathy, D.-L. Kwong, and Y.-C. Yeo, “Full silicidation of silicon gate electrode using nickel-terbium alloy for MOSFET applications,” Journal of The Electrochemical Society, vol. 153, no. 4, G337-G340, 2006. [2] A. E.-J. Lim, W. S. Hwang, X. P. Wang, D. M. Y. Lai, G. S. Samudra, D.-L. Kwong, and Y.-C. Yeo, “Metal gate work function modulation using Hf alloys obtained by interdiffusion of thin metallic layers,” Journal of The Electrochemical Society, vol. 154, no. 4, H309-H313, 2007. [3] A. E.-J. Lim, R. T. P. Lee, X. P. Wang, W. S. Hwang, C. H. Tung, G. S. Samudra, D.-L. Kwong, and Y.-C. Yeo, “Yttrium- and terbium-based interlayer on SiO2 and HfO2 gate dielectrics for work function modulation of nickel fully-silicided gate in NMOSFETs,” IEEE Electron Device Letters, vol. 28, no. 6, pp. 482-485, 2007. [4] A. E.-J. Lim, W.-W. Fang, F. Liu, R. T. P. Lee, G. Samudra, D.-L. Kwong, and Y.-C. Yeo, “Impact of interfacial dipole on effective work function of nickel fully-silicided gate electrodes formed on rare-earth based dielectric interlayers,” Applied Physics Letters, vol. 91, 172115, 2007. [5] X. P. Wang, H. Y. Yu, M.-F. Li, C. X. Zhu, S. Biesemans, A. Chin, Y. Y. Sun, Y. P. Feng, A. E-J. Lim, Y.-C. Yeo, W. Y. Loh, P. Lo, and D.-L. Kwong, “Wide Vfb and Vth tunability for metal gated MOS devices with HfLaO gate dielectrics,” IEEE Electron Device Letters, vol. 28, no. 4, pp. 258–260, 2007. [6] X. P. Wang, A. E.-J. Lim, M.-F. Li, C. Ren, W. Y. Loh, C. X. Zhu, A. Chin, A. D. Trigg, Y.-C. Yeo, S. Biesemanns, G. Q. Lo, and D.-L. Kwong, “Work function tunability of 130 refractory metal nitrides by lanthanum or aluminum doping for advanced CMOS devices,” IEEE Transactions on Electron Devices, vol. 54, no. 11, pp. 2871-2877, 2007. [7] A. E.-J. Lim, R. T. P. Lee, A. T. Y. Koh, G. S. Samudra, D.-L. Kwong, and Y.-C. Yeo, “Effectiveness of aluminum incorporation in nickel silicide and nickel germanide metal gates for work function reduction,” Japanese Journal of Applied Physics, vol. 47, no.4, pp. 2383-2387, 2008. [8] A. E.-J. Lim, R. T. P. Lee, G. S. Samudra, D.-L. Kwong, and Y.-C. Yeo, “Novel rareearth dielectric interlayers for wide NMOS work function tunability in Ni-FUSI gates,” IEEE Transactions on Electron Devices, vol. 55, no.9, pp. 2370-2377, 2008. [9] A. E.-J. Lim, R. T. P. Lee, G. S. Samudra, D.-L. Kwong, and Y.-C. Yeo, “Modification of molybdenum gate electrode work function via (La-, Al-induced) dipole effect at highk/SiO2 interface,” IEEE Electron Device Letters, vol. 29, no. 8, pp. 848–851, 2008. [10] A. E.-J. Lim, D.-L. Kwong, and Y.-C. Yeo, “Work Function Engineering within a Single Metal Gate Stack: Manipulating Terbium- and Aluminum-Induced Interface Dipoles of Opposing Polarity,” IEEE Transactions on Electron Devices, vol. 30, no. 3, 2009. Conference Publications [11] X. P. Wang, C. Shen, M.-F. Li, H. Y. Yu, Y. Sun, Y. P. Feng, A. E.-J. Lim, W. S. Hwang, A. Chin, Y.-C. Yeo, P. Lo, and D.-L. Kwong, “Dual metal gates with band-edge work functions on novel HfLaO high-k gate dielectric,” Symposium on VLSI Technology, Honolulu, HI, Jun. 13-15, pp. 9-10, 2006. [12] A. E.-J. Lim, W.S. Hwang, X.P. Wang, D.–L. Kwong, and Y.-C. Yeo, “Work function modulation using thin interdiffused metal layers for dual metal-gate technology,” 2006 International Conference on Solid State Devices and Materials (SSDM), Yokohama, Japan, Sep. 13-15, pp. 484-485, 2006. 131 [13] A. E.-J. Lim, R. T. P. Lee, X. P. Wang, W. S. Hwang, C.-H. Tung, D. M. Y. Lai, G. Samudra, D.-L. Kwong, and Y.-C. Yeo, “Band edge NMOS work function for nickel fully-silicided (FUSI) gate obtained by the insertion of novel Y-, Tb-, and Yb-based interlayers,” 37th European Solid-State Device Research Conference (ESSDERC), Munich, Germany, Sep. 11-13, pp. 210-213, 2007. [14] A. E.-J. Lim, R. T. P. Lee, Alvin T. Y. Koh, G. Samudra, D.–L. Kwong, and Y.-C. Yeo, “Effectiveness of Aluminum Incorporation of Nickel Silicide and Nickel Germanide Metal Gate for Work Function Reduction,” 2007 International Conference on Solid State Devices and Materials (SSDM), Ibaraki, Japan, Sep. 19-21, pp. 856-857, 2007. [15] X. P. Wang, J. J. Yang, H. Y. Yu, M. F. Li, J. D. Chen, R. L. Xie, C. X. Zhu, A. Y. Du, P. C. Lim, A. E.-J. Lim, Y. Y. Mi, D. M. Y. Lai, W. Y. Loh, S. Biesemans, G. Q. Lo, and D. L. Kwong, “Practical solutions to enhance EWF tunability of Ni FUSI gates on HfO2,” 2007 International Conference on Solid State Devices and Materials (SSDM), Ibaraki, Japan, Sep. 19-21, pp. 854-855, 2007. [16] A. E.-J. Lim, W.-W. Fang, F. Liu, R. T. P. Lee, G. S. Samudra, D.-L. Kwong, and Y.-C. Yeo, "Interface dipole mechanism and NMOS Ni-FUSI gate work function engineering using rare-earth metal (RE)-based dielectric interlayers,” International Semiconductor Device Research Symposium (ISDRS), College Park MD, USA, Dec. 12-14, WP3-09, 2007. [17] A. E.-J. Lim, J. Hou, D.-L. Kwong, and Y.-C. Yeo, “Manipulating interface dipoles of opposing polarity for work function engineering within a single metal gate stack,” International Electron Device Meeting Tech. Dig., San Francisco, USA, Dec 15-17, 2008. 132 [...]... the same method Therefore, continuous research is essential to allow a smooth transition from the current conventional poly-Si/SiON gate stack to a metal gate/ high-k gate stack for future CMOS technology nodes 7 Table 1.1 A summary of different metal gate integration approaches for CMOS devices Metal gate integration approach One metal Φ1 Φ2 M1 M1 • • 1 masking step Other methods for Φm tuning to achieve... dipole formation were also found to influence the effective gate Φm after extensive research was conducted for various metal gate systems [1.18]-[1.20] As such, the implementation of metal gate/ high-k dielectric gate stack is not a straightforward process, and substantial efforts are required for material selection and integration into the mainstream CMOS process 1.2.1 Current Status in Metal Gate Technology... shifts of ~0.6 – 0.8 V from NiSi control were obtained for REIL incorporated gate stacks A wide selection of RE materials was investigated, including Y, Er, Dy, Tb, Gd, Yb, and La NiSi (60 nm)/REIL(~1 – 1.5 nm)/SiO2 gate stacks were formed using an initial SiO2 layer of 3 nm (b) Tight VFB distributions for REIL gate stacks confirmed the uniformity of REIL formation by sputtering 50 (a) VFB versus Tox... uniform formation throughout the dielectric 58 Backside SIMS profile of NiSi/YIL/SiO2 gate stack confirmed that there was no Y diffusion into the Si substrate which might degrade device characteristics 59 (a) Typical gate leakage and (b) breakdown voltage showed better characteristics for NiSi gate stack incorporating a YIL and a TbIL A RTA at 950ºC was conducted before FUSI for the gate. .. curves of TaAlN-gated HfO2/Tb/SiO2 gate dielectric stack after 500ºC and 950ºC RTA showing large VFB shift of ~0.75 V 92 N-type Φm tunability obtained on HfLaO dielectric for a wide variety of metal gates including Mo, TaC, TiN, HfN, and TaN 93 VFB versus Tox plot shows that the Mo/Al2O3/SiO2 and the MoAl/SiO2 gate stacks have larger effective Φm than the Mo/SiO2 gate stack All gate stacks underwent... Therefore, a dielectric stack with a single high-k thickness on varying SiO2 thicknesses will limit the influence of high-k bulk charges and enable a reasonably accurate Φm extraction [Fig 1.3(b)] (a) Metal gate/ SiO2 stack (b) Metal gate/ high-k stack Metal gate High-k dielectric SiO2 Si substrate SiO2 Si substrate Fig 1.3 An illustration of (a) metal gate/ SiO2 and (b) metal gate/ high-k stacks formed... thickness Hence, for a given technology node (fixed Nd and Tox), the metal gate Φm would determine the Vth To obtain low and symmetrical Vth for optimal CMOS device performance, the metal gate Φm must be close to the silicon conduction and valence bands for n and p-channel bulk CMOS transistors, respectively, or about 0.2 eV above and below the intrinsic Si Fermi level is required for advanced transistor... showing the poly-Si gate depletion layer during inversion bias (b) The capacitance-voltage plot depicts how the poly-Si gate depletion effect decreases the gate capacitance in the inversion regime 4 Metal gate Φm requirements for both planar bulk transistors and transistors with advanced structures are shown 5 An illustration of (a) metal gate/ SiO2 and (b) metal gate/ high-k stacks formed with different... recent breakthrough in the implementation of metal gate/ high-k gate stack for CMOS devices in high volume production [1.7] However, research on issues such as optimization of n- and p-type gate Φm, physics in metal- 2 dielectric interface, and gate stack reliability are still on-going for improvements in future technology nodes To further boost transistor performance, carrier mobility in transistor channel... poly-Si/high-k gate stacks [1.13] This was caused by the reaction of poly-Si gate with the high-k dielectric after post-deposition annealing steps Thereafter, the advent of metal gates became unavoidable and the feasibility of a metal gate/ high-k gate stack was further affirmed by the demonstration of CMOS transistors with high drive currents [1.14] One of the most important parameters for metal gate candidates . METAL GATE TECHNOLOGY FOR ADVANCED CMOS GATE STACKS LIM EU-JIN ANDY NATIONAL UNIVERSITY OF SINGAPORE 2008 METAL GATE TECHNOLOGY FOR ADVANCED CMOS GATE STACKS . avenues for future metal gate/ high-k gate stack engineering in scaled CMOS technology nodes. vii List of Tables Table 1.1 A summary of different metal gate integration approaches for CMOS. Typical gate leakage and (b) breakdown voltage showed better characteristics for NiSi gate stack incorporating a Y IL and a Tb IL . A RTA at 950ºC was conducted before FUSI for the gate stacks.