Study on high mobility channel transistors for future sub 10 nm CMOS technology

STUDY ON HIGH MOBILITY CHANNEL TRANSISTORS FOR FUTURE SUB-10 nm CMOS TECHNOLOGY FEI GAO NATIONAL UNIVERSITY OF SINGAPORE 2007 STUDY ON HIGH MOBILITY CHANNEL TRANSISTORS FOR FUTURE SUB-10 nm CMOS TECHNOLOGY Fei GAO (B. Eng, Xi’an Jiaotong University, PR CHINA) A THESIS SUBMITTED FOR THE DEGREE OF DOCTOR OF PHILOSOPHY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING NATIONAL UNIVERSITY OF SINGAPORE 2007 Acknowledgements Upon completion of this thesis, as I retrospect my four years research life in SNDL, I realize there are indeed many people to thank. I would like to thank: My supervisors, Dr. Lee Sungjoo (NUS) and Dr. Subramanian Balakumar (IME) for their effective guidance during the past four years; their knowledge, insights and ideas are critical to the successful completion of my PHD research. Their fresh thought and creative thinking always inspire me when I was lost in direction. My deepest thanks and heartfelt appreciation are always with them. Prof. D.L. Kwong (IME), A/P. B.J Cho (NUS), Dr. D.Z. Chi (IMRE), Dr. N. Balasubramanian (IME), Dr. G-Q Lo (IME) and Prof. C.W. Liu (National Taiwan University) for their insightful comments and fruitful discussions during the course of my research; their professionalism also impresses me greatly; Mr. C.H. Tung (IME), Dr. A. Jay (IME), Dr. C.K. Chia (IMRE), Dr. T. Sudhiranjan (IMRE), Dr. J.S. Pan (IMRE), Dr. Y.-L. Foo (IMRE), Dr. A. Du (IME), and Mr. L.J. Tang (IME), for their help in setting up the experiment and analyzing experimental results; their easily comprehensible illustrations have greatly broadened my horizon and their dedication to science is hard to forget. My collaborators Li Rui, S.J. Whang, and H.B. Yao for their assistance in experiment; I can still recall vividly those sleepless nights we spent together in SNDL. I want to extend my gratitude to many other staff & students in SNDL, IME and IMRE, who had helped me in processing my samples, carrying out analysis, or in other formats, my sincere thanks go to them and I wish them all the best in future. Finally, I would like to express my deepest love to my parents for everything they provided. I TABLE of CONTENTS Acknowledgements I Table of Contents II Abstract VI List of Tables VIII List of Figures IX List of Symbols XIV Chapter 1: Introduction 1.1 Introduction-----------------------------------------------------------------------------------1 1.2 MOSFET Scaling----------------------------------------------------------------------------2 1.2.1 Scaling Trend--------------------------------------------------------------------------2 1.2.2 Requirements for Further Scaling--------------------------------------------------4 1.2.3 Challenges for Scaling---------------------------------------------------------------5 1.3 Approaches for Further Scaling------------------------------------------------------------7 1.3.1 High-k and Metal Gate---------------------------------------------------------------7 1.3.2 Innovative Device Structure---------------------------------------------------------9 1.3.3 Advanced Channel Material-------------------------------------------------------10 1.4 Summary------------------------------------------------------------------------------------13 1.5 Thesis Organization------------------------------------------------------------------------14 Reference----------------------------------------------------------------------------------------15 Chapter 2: Surface Passivation for Ge and GaAs substrates for MOS Device Application 25 II 2.1 Surface Passivation for Ge----------------------------------------------------------------26 2.1.1 Introduction--------------------------------------------------------------------------26 2.1.2 Experiment---------------------------------------------------------------------------27 2.1.3 Results and Analysis----------------------------------------------------------------28 2.1.3.1 Passivation---------------------------------------------------------------------28 2.1.3.2 Gate Stack TEM--------------------------------------------------------------30 2.1.3.3 C-V and I-V Characteristics-------------------------------------------------31 2.1.3.4 Gate Stack Thermal Stability------------------------------------------------32 2.1.3.5 Effect of AlN Thickness-----------------------------------------------------33 2.1.3.6 Scalability----------------------------------------------------------------------35 2.1.3.7 Ge MOSFET with AlN Passivation----------------------------------------36 2.1.4 Conclusion----------------------------------------------------------------------------39 2.2 Surface Passivation for GaAs-------------------------------------------------------------40 2.2.1 Introduction--------------------------------------------------------------------------40 2.2.2 Experiment---------------------------------------------------------------------------41 2.2.3 Results and Discussion-------------------------------------------------------------41 2.2.3.1 Surface Cleaning Effect------------------------------------------------------41 2.2.3.2 Surface Morphology----------------------------------------------------------43 2.2.3.3 PN Surface Treatment--------------------------------------------------------45 2.2.3.4 AlN Surface Treatment------------------------------------------------------47 2.2.3.5 Electrical Characteristics----------------------------------------------------50 2.2.3.6 TEM of Gate Stack-----------------------------------------------------------54 2.2.3.7 Thermal Stability-------------------------------------------------------------55 2.2.3.8 GaAs n-MOSFET with AlN-HfO2-----------------------------------------60 2.2.4 Conclusion----------------------------------------------------------------------------63 2.3 Summary------------------------------------------------------------------------------------63 Reference----------------------------------------------------------------------------------------64 Chapter 3: Fabrication of High-Mobility Channel on Insulator Substrate-------------------------------------------------------------------------70 3.1 Introduction---------------------------------------------------------------------------------70 3.2 SPE to Form Localized GOI--------------------------------------------------------------71 3.2.1 Concept of Localized GOI Formation--------------------------------------------71 3.2.2 Experiment---------------------------------------------------------------------------72 III 3.2.3 Results and Discussion-------------------------------------------------------------74 3.2.3.1 Seed Region Analysis--------------------------------------------------------74 3.2.3.2 GOI Structure-----------------------------------------------------------------76 3.2.4 Conclusion----------------------------------------------------------------------------79 3.3 Condensation of amorphous SiGe Film on SOI Substrate to form SGOI----------79 3.3.1 Condensation Mechanism ---------------------------------------------------------79 3.3.2 Experiment---------------------------------------------------------------------------81 3.3.3 Results and Discussion-------------------------------------------------------------82 3.3.3.1 Amorphous SiGe layer on SOI---------------------------------------------82 3.3.3.2 Crystal Quality and Composition of SGOI--------------------------------82 3.3.3.3 XRD strain analysis of SGOI-----------------------------------------------86 3.3.3.4 Cyclic Anneal Effect---------------------------------------------------------88 3.3.4 Conclusion----------------------------------------------------------------------------91 3.4 Summary------------------------------------------------------------------------------------92 Reference----------------------------------------------------------------------------------------93 Chapter 4: High Mobility Channel MOSFET Integrated with Highk/Metal Gate and Schottky S/D----------------------------------------------97 4.1 Introduction---------------------------------------------------------------------------------97 4.1.1 High Mobility Channel MOSFET Integration-----------------------------------97 4.1.2 Schottky S/D Transistor------------------------------------------------------------98 4.2 Schottky S/D MOSFET on Si0.05Ge0.95/Si Substrate---------------------------------100 4.2.1 Experiment--------------------------------------------------------------------------100 4.2.2 Results and Discussion------------------------------------------------------------105 4.2.2.1 Gate Stack----------------------------------------------------------------------105 4.2.2.2 Performance of Long Channel MOSFET----------------------------------107 4.2.2.3 Performance of Short Channel MOSFET----------------------------------110 4.2.3 Conclusion--------------------------------------------------------------------------113 4.3 Schottky S/D MOSFET on thin SGOI substrate-------------------------------------113 4.3.1 SGOI substrate and Transistor Structure---------------------------------------114 4.3.2 Gate Stack and S/D TEM---------------------------------------------------------115 4.3.3 Transistor Characteristics---------------------------------------------------------117 4.3.4 Conclusion--------------------------------------------------------------------------118 4.4 Summary-----------------------------------------------------------------------------------120 IV Reference---------------------------------------------------------------------------------------121 Chapter 5: Conclusion--------------------------------------------126 5.1 Conclusion---------------------------------------------------------------------------------126 5.1.1 Surface Passivation for Ge and GaAs-------------------------------------------126 5.1.2 GOI and SGOI fabrication--------------------------------------------------------128 5.1.3 Schottky S/D transistor------------------------------------------------------------129 5.2 Recommendations------------------------------------------------------------------------130 Reference---------------------------------------------------------------------------------------132 List of Publications V Abstract Driven by consumers’ demand for IC (Integrated Circuits) chips with higher performance but lower cost, the dimension of MOSFET (Metal Oxide Semiconductor Field Effect Transistor) has been scaled continuously, following the Moor’s law. However, further scaling of conventional MOSFET with poly-Si/SiON/Si-substrate structure is approaching its physical limits: intolerable high gate leakage current, undesirable poly-Si gate depletion and difficulties in controlling the short channel effects. MOSFET made on high mobility channel materials, such as Ge and GaAs, with high-k/metal gate stack, is a possible alternative to extend the Moor’s law. Hence, in this thesis, several technical aspects regarding the high-mobility channel MOSFET are explored. High quality gate stack is critical for high performance Ge and GaAs MOSFET. It was found that the surface oxidation of Ge and GaAs substrates during the high-k deposition should be avoided since the formed oxides would cause the dysfunction of the MOS devices. Hence, surface passivation using thin sputtered AlN film on both Ge and GaAs substrates, prior to the deposition of high-k, is proposed and investigated. XPS (X-Ray Photoelectron Spectroscopy) analysis confirms the role of AlN in preventing the substrates from oxidation, resulting in excellent Ge and GaAs MOS devices. Besides, PN (Plasma Nitridation) surface treatment on GaAs substrate is applied. With optimized nitridation process, excellent GaAs MOS capacitors are realized. Excellent thermal stability of the aforementioned passivation methods is also confirmed by thermal stress tests. Subsequently, Ge and GaAs MOSFETs with AlN passivation and HfO2/TaN gate stack are also demonstrated. VI For highly scaled MOSFET fabrication, high mobility on insulator structure is more desirable than bulk substrate, due to its better immunity to short channel effects, reduced parasitic junction capacitance and free of latch-up. Methods of realizing localized high mobility channel on insulator structure and cost effective approaches are always attractive for integration and commercial purpose. By using Ge SPE (Solid Phase Epitaxy) lateral growth at 800oC on pre-patterned Si substrate, localized GOI (Germanium on Insulator) structure on Si substrate is fabricated. Besides, strained high-Ge concentration SGOI is successfully demonstrated by two-step oxidation of sputtered low Ge content α-SiGe (amorphous SiGe) on a SOI substrate. Compared with conventional condensation approach, this novel condensation method is not only cost effective but also process simple. Finally, an integration scheme for Ge and SiGe (with high Ge percentage) MOSFET with HfO2/TaN gate stack is proposed by using Schottky S/D (Source/Drain) rather than the conventional doped S/D. The metallic Schottky S/D with low formation temperature can overcome several sever technical issues facing the doped S/D in these channels: low dopant solubility, insufficient dopant activation, dopant loss and Ge out-diffusion into the high-k at high temperature dopant activation process. Ni-germanide Schottky S/D p-MOSFET with 85% hole mobility enhancement over the universal hole mobility was realized on Si0.05Ge0.95/Si substrate with HfO2/TaN gate stack. Besides, thin-S0.35G0.65OI Schottky S/D transistor, one of the promising non-classical architectures for future CMOS application, was demonstrated using a self-aligned top gate process. VII List of Tables Table 1.1 HP, LSP and LOP Logic Technology Requirements (MPU: Microprocessor Unit; EOT: Equivalent Oxide Thickness; Jg,limit: Gate Leakage Current Density Limit.)-------------------------------------------------------------------------5 Table 1.2 Properties of semiconductor materials: Si, Ge, GaAs, InAs, InP, and InSb (μelectron: Electron Mobility; μhole: Hole Mobility)-------------------------------11 Table 2.1 Top surface roughness RMS values measured by AFM within an area of μm by μm after different process steps.----------------------------------------44 Table 2.2 Interface state density (D i t ) estimated by conduction method for TaN/HfO2/GaAs stack with different passivations.-----------------------------53 Table 4.1 Comparison between this work and previous works regarding the characteristics of Schottky S/D and conventional MOSFETs; Lg is gate length, Id is drain current and Ion/off is on/off ratio.----------------------------113 VIII Chapter 4: High Mobility Channel MOSFET Integrated with High-k/Metal Gate and Schottky S/D [9] C. Jasper, L. Rubin, C. Lindfors, K.S. Jones, and J. Oh, “Electrical Activation of Implanted Single Crystal Germanium Substrates,” Proceeding of 14th International Conference on Ion Implantation Technology, p.548 (2002); [10]R. Hattori, and J. Shirafuji, “Numerical Simulation of Tunnel Effect Transistors Employing Internal Field Emission of Schottky Barrier Junction,” Japanese Journal of Applied physics, vol. 33, p.612 (1994); [11] W. Saitoh, A. Itoh, S. Yamagami and M. Asada, “Analysis of Short-Channel Schottky Source/Drain Metal-Oxide-Semiconductor Field-Effect Transistor on Silicon-On-Insulator Substrate and Demonstration of Sub-50-nm n-type Devices with Metal Gate,” Japanese Journal of Applied Physics, vol. 38, p.6226 (1999); [12] W. Saitoh, S. Yamagami, A. Itoh, and M. Asada, “35 nm Metal Gate p-type Metal Oxide Semiconductor Filed-Effect Transistor with PtSi Schottky Source/Drain on Separation by Implanted Oxygen Substrate,” Japanese Journal of Applied Physics, vol. 38, p. L629 (1999); [13] Q.T. Zhao, F. Klinkhammer, M. Dolle, L. Kappius, and S. Mantl, “Nanometer patterning of epitaxial CoSi2/Si (100) for ultrashort channel Schottky barrier metaloxide-semiconductor field effect transistor,” Applied Physics Letters, vol. 74, p.454 (1999); [14] S. Zhu, H.Y. Yu, J.D. Chen, S.J. Whang, J.H. Chen, C. Shen, C. Zhu, S.J. Lee, M.F. Li, D.S.H. Chan, W.J. Yoo, A. Du, C.T. Tung, J. Singh, A. Chin, and D.L. Kwong, “Low Temperature MOSFET Technology with Schottky Barrier Source/Drain, High-k Gate Dielectric and Metal Gate Electrode,” Solid-State Electronics, vol. 48, p.1987 (2004); 122 Chapter 4: High Mobility Channel MOSFET Integrated with High-k/Metal Gate and Schottky S/D [15] J. Kedzierski, P. Xuan, V. Subramanian, J. Bokor, T.-S. King, C. Hu, “A 20nm Gate -Length Ultra-thin Body p-MOSFET with Silicide Source/Drain,” Superlattices and Microstructures, vol. 28, p.445 (2000); [16] A. Nayfeh, C.O Chui, T. Yonehara, and K.C. Saraswat, “Fabrication of HighQuality p-MOSFET in Ge grown Heteroepitaxially on Si,” IEEE, Electron Device Lett., Vol. 26, March, p.331 (2004); [17] X. Chen, S. Joshi, J. Chen, T. Ngai, and S.K. Banerjee, “MOS Capacitors on Epitaxial Ge-Si1-xGex with high-k gate Dielectrics using RPCVD,” IEEE, Trans. Electron Devices, Vol. 51, September, p.1532 (2004); [18] C.C Yeo, B.J. Cho, F. Gao, S.J. Lee, M.H. Lee, C.-Y. Yu, C.W. Liu. L.J. Tang and T.W. Lee, “Electron Mobility Enhancement Using Ultrathin Pure Ge on Si Substrate,” IEEE, Electron Device Lett., Vol. 26, October, p.761 (2005); [19] N. Wu. Q. Zhang, C. Zhu, D.S.H. Chan, M.F. Li, N. Balasubramanian, A. Chin, D.-L. Kwong, “Alternative Surface Passivation on Germanium for Metal-OxideSemiconductor Applications with High-k Gate dielectric,” Applied Physics Letter, vol, 85, p.4127 (2004); [20] L.Kang, B.H. Lee, W.-J Qi, Y. Jeon, R. Nieh, S. Gopalan, K. Onishi, J.C. Lee, “Electrical Characteristics of Highly Reliable Ultrathin Hafnium Oxide Gate Dielectric,” IEEE Electron Device Letter, vol. 21, p.181 (2000); [21] Rui Li, Lee, S.J, Yao H.B, Chi D.Z., Yu M.B, D.-L Kwong, “Pt-Germanide Schottky source/drain Germanium p-MOSFET with HfO2 gate dielectric and TaN gate electrode, ” IEEE Electron Device Letter, vol. 27, no. 6, June, p.476 (2006); [22] D.Z. Chi, R.T.P. Lee, S.J. Chua, S.J. Lee, S. Ashok, D.-L. Kwong, “CurrentVoltage Characteristics of Schottky Barriers with Barrier Heights Larger than the 123 Chapter 4: High Mobility Channel MOSFET Integrated with High-k/Metal Gate and Schottky S/D Semiconductor Band Gap: the Case of NiGe/n-(001)Ge Contact,” Journal of Applied Physics, vol. 97, p.113706 (2005); [23]D.K. Schroder, “Semiconductor Material and Device Characterization,” WileyInterscience, (1998); [24] A.G. Sabnis, and J.T. Clemens, “Characterization of the Electron Mobility in the Inverted (100) Si surface,” IEEE Int. Electron Dev. Meet., Washington, DC, p.18 (1979); [25] S.C. Sun and J.D. Plummer, “Electron Mobility In Inversion and Accumulation Layers on Thermally Oxidized Silicon Surfaces,” IEEE Trans. Electron Dev. Ed-47, p.1497 (1980); [26] S.M. Sze, “Physics of Semiconductor Devices,” Wiley-Interscience Publication, (1981); [27] K. Goto, J. Matsuo, Y. Tada, T. Tanaka, Y. Momiyama, T. Sugii, and I. Yamada, “A High Performance 50 nm PMOSFET using Decaborane (B10H14) Ion implantation and 2-step Activation Annealing Process,”IEEE Electron Device Meeting, Technical Digest, p.471 (1997); [28] C. Wang, J.P. Synder, and J.R. Tucker, “Sub-50nm PtSi Schottky Source/Drain p-MOSFETs,” 56th Device Research Conference, Virginia, p.72 (1998); [29] T. Maeda, K. Ikeda, S. Nakaharai, T. Tezuka, N. Sugiyama, Y. Moriyama, and S. Takagi, “High Mobility Ge-on-Insulator p-Channel MOSFETs Using Pt Germanide Schottky Source/Drain,” IEEE Electron Device Letters, vol.26, p.102 (2005); [30] S.L. Zhang, M. Ostling, “Metal silicides in CMOS technology: Past, present and future trends,” Critical Reviews in Solid State and Mater. Sci., 28, p.1 (2003); [31] S.J. Whang, S.J. Lee, F. Gao, N. Wu, C.X. Zhu, J.S. Pan, L.J. Tan, D.L. Kwong, “Germanium p- & n-MOSFETs fabricated with Novel surface passivation (Plasma- 124 Chapter 4: High Mobility Channel MOSFET Integrated with High-k/Metal Gate and Schottky S/D PH3 and thin AlN) and TaN/HfO2 Gate Stack,” Tech. Dig. –Int. Electron Devices Meet. 2004, p.307 (2004). 125 Chapter 5: Conclusion Chapter Conclusion In this chapter, summary of the previous chapters will be made, and then recommendation on future research on high mobility transistor will be discussed. 5.1 Conclusion 5.1.1 Surface Passivation for Ge and GaAs High mobility channel materials such as Ge and GaAs will be possible alternatives to conventional Si substrate for high performance CMOS (Complementary Metal Oxide Semiconductor) application. However the lack of high quality native oxides proves to be a serious challenge for fabrication of high performance Ge and GaAs MOSFET. Although deposited high-k gate dielectric rather than thermally grown oxides could be a promising solution for Ge and GaAs, the degradation of the interface quality due to the surface oxidation during the high-k deposition process is inevitable. The surface oxidation generated GeO2 and As(Ga)O2 are the root causes for severely distorted C-V (Capacitance-Voltage) and interface Fermi level pinning, resulting in dysfunction of the MOS devices. An effective surface treatment on these new substrates is indispensable to the successful fabrication of Ge and GaAs MOSFET (Metal Oxide Semiconductor Field Effect Transistor) with high drivability. Besides effectively suppressing the oxide formation during the process of gate stack formation, a desirable surface passivation method should provide excellent thermal stability. Methods for passivation of Ge and GaAs substrates are studied extensively such as NH3 treatment of Ge surface and thin layer Si/Ge passivation for GaAs. Because of concerns over these passivation methods such 126 Chapter 5: Conclusion as thermal stability and effectiveness of NH3 treatment for Ge and Si/Ge passivation related doping effects for GaAs (details are discussed in Chapter 1), new and innovative passivation approaches are expected. In this thesis, a thin sputtered AlN passivation method for Ge substrate was proposed and implemented, XPS (X-ray Photoelectron Spectroscopy) analysis revealed that by applying thin AlN passivation, the amount of GeO2, formed mainly during the high-k deposition, was greatly reduced compared with the sample with conventional NH3 treatment and without surface treatment. As expected, improved CV characteristics were observed. Besides, AlN surface passivated Ge MOS capacitor showed superior thermal stability compared with NH3 surface treated Ge MOS capacitor, mainly due to AlN’s effectiveness in preventing Ge diffusion. The thickness of AlN required for effective passivation depends strongly on the high-k thickness, a 0.5 nm was found to be enough for a nm HfO2; but for a 3.5 nm HfO2 deposition, thicker AlN is needed. Hence, thickness of AlN passivation layer should be engineered for optimal device performance. AlN passivation also showed excellent scalability on Ge substrate. MOS device with EOT as thin as 10.5 nm was demonstrated with reduced gate leakage current compared with NH3 treated samples. Finally, Ge p-MOSFET with S.S as low as 82mv/dec and 40% peak hole mobility enhancement over NH3 treated sample is realized. Great reduction of the oxides formed during the high-k deposition was similarly confirmed on GaAs substrate by using AlN passivation; improved thermal stability due to the effectiveness of AlN in retarding the Ga and As diffusion into high-k was also observed. Besided, enhancement mode GaAs p-MOSFET using AlN surface passivation and HfO2/TaN gate stack was successfully demonstrated. In addition, the effect of PN (Plasma Nitridation) surface treatment of GaAs was studied. The 127 Chapter 5: Conclusion phenomenon of selective nitridation of Ga atoms on GaAs surface was revealed by XPS analysis. The nitridation process condition, which affected the thickness of the nitride layer, was critical in achieving well-behaved capacitor. By using optimized nitridation process, pinning-free interface between the GaAs and HfO2 was realized, resulting in excellent accumulation characteristics on both p- and n-GaAs MOS capacitors. 5.1.2 GOI and SGOI fabrication Integration of GOI (Germanium on Insulator) MOSFET with conventional Si MOSFET for SOC (System on Chip) technology requires realization of localized GOI structure on Si substrate. Using Ge SPE (Solid Phase Epitaxy) lateral growth on prepatterned Si substrate, localized GOI was achieved. XRD (X-Ray Diffraction) and TEM (Transmission Electron Microscopy) analysis suggests that solid phase epitaxy was not initialized at 600oC, however at the increased temperature of 800oC, evidence of SPE was observed and under this condition localized GOI structure was successfully fabricated. The GOI has high single crystal quality and the same crystal direction as the Si substrate, confirmed by TEM and SAD (Selected Area Diffraction) pattern. With the purpose of reducing process cost and dependence on expensive MBE (Molecular Beam Epitaxy) or UHVCVD (Ultra High Vacuum Chemical Vapor Deposition) system for epitaxial growth of SiGe, by using novel condensation of sputtered amorphous-SiGe on SOI substrate, high quality single crystal Si0.35Ge0.65OI was successfully fabricated. The calculation shows that little Ge was lost during the oxidation process. Raman analysis reveals that the SiGe involves 0.26% compressive overall strain. Anisotropy strain evaluated by HR-XRD (High Resolution X-Ray 128 Chapter 5: Conclusion Diffraction) techniques suggests the film involves 0.59% in-plane compressive stain and 0.45% out-plane tensile strain. The cyclic annealing between the temperature of 760oC and 900oC proved to be effective in reducing the defects and greatly improving the quality of SGOI, without affecting the strain involved in the film. By this condensation method, SGOI wafer with thickness as thin as 20 nm was also presented. 5.1.3 Schottky S/D transistor Low resistance S/D (Source/Drain) with low formation temperature is desired for integration of SiGe and Ge MOSFET with high-k and metal gates, due to the following issues involved in the conventional doped S/D: low dopant solubility, insufficient dopant activation, dopant loss in Ge and Ge diffusion into the high-k at high temperature S/D activation. Hence, metallic Schottky S/D is proposed and by adopting this Schottky S/D technology, high mobility channel MOSFETs integrated with HfO2/TaN were demonstrated. High performance Ni-germanide Schottky S/D MOSFET made on Si0.05Ge0.95/Si substrate showed 85% mobility enhancement over the universal hole mobility. By using photoresist trimming process, transistor with 97nm gate length was also achieved with higher driverablity compared with conventional Si MOSFET. Finally Schottky S0.35G0.65OI transistor with HfO2/TaN gate stack using conventional self-aligned top gate structure was realized with extracted peak hole mobility comparable to conventional Ge MOSFET. 5.2 Recommendations 129 Chapter 5: Conclusion Although many exciting results have been published so far, many more issues should be better understood and further investigated for improvement and possible implementation of high mobility MOSFET in future. Several possible research directions in this area could be (1) Gate Stack Engineering Gate Stack Engineering for Ge and GaAs includes an effective passivation method, an appropriate high-k gate dielectric and metal electrodes with desired work function. Existing passivation methods motioned in this thesis should be further investigated and evaluated in terms of EOT (Equivalent Oxide Thickness) scaling and process optimization. However, it should be noted that theses passivation approaches could be far from perfection and should not dampen the efforts of exploring other new and innovative methods, which could finally be implemented into production. Although there is a consensus in the academy and semiconductor industry that Hf based high-k gate dielectric is the most promising high-k candidate for Si based MOSFET (In fact, Intel will implement Hf-based high-k gate dielectric into its 45 nm technology node processors, which are scheduled for production by the end of 2007 [1]), with the introduction of new substrates such as Ge and GaAs, the selection process of a suitable high-k with appropriate deposition method is by no means easy. Fortunately, the efforts on this area are being made, although it is still in its incipient stage. Many theoretical calculations and experimental results of band offset for various oxides on Ge and GaAs could provide some basic and preliminary guidelines [2-6]. Various high-k materials have also been experimentally investigated on these substrates [7-12]. More intensive research work is needed before an optimal high-k dielectric can be identified. Finally, metal gates that can achieve suitable Vth on Ge 130 Chapter 5: Conclusion and Ga MOSFET will be needed, there are few reports on this area possibly because at the current stage, passivation and high-k technology are more urgent. (2) Novel Device Structure For Ge MOSFET, Schottky S/D could be an alternative solution to doped S/D technology. Although high performance Ge p-MOSFETs with Schottky S/D are demonstrated, performance of Ge n-MOSFET with Schottky S/D is still quite disappointing, which requires future intensive research. For better control of the short channel effects on highly scaled MOSFET, GOI and GaAs on insulator may be finally needed, the fabrication of the substrate itself requires fresh ideas and creativity. Devices with double gate or multigate structures on Ge and GaAs are also possible solutions. (2) Hetero-Substrate Integration Although high performance Ge p-MOSFETs was demonstrated by several groups [9, 13], the performance of Ge n-MOSFET is rather disappointing [14, 15], hence combination of high performance p-MOSFET on Ge substrate and high performance n-MOSFET on GaAs substrate would be a possible strategy for 22 nm node CMOS and beyond. This hetero-channel CMOS technology can be possibly implemented by selective epitaxial grow of thin film GaAs on Ge [16, 17]. Process integration for this architecture requires devoted efforts from many researchers. 131 Chapter 5: Conclusion Reference [1] www. intel.com; [2] K.-I. Seo, P.C. McIntyre, S. Sun. D.-I. Lee, P. Pianetta, K.C. Saraswat, “Chemicla States and Electronic Structure of a HfO2/Ge (001) interface,” Applied Physics letter, 87, p.042902 (2005); [3] V.V. Afanas’ev and A. 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Passlack, “1μm Enhancement Mode GaAs N-Channel MOSFETs With Transconductance Exceeding 250 mS/mm, ” IEEE Electron Device Letters, vol. 28, p.100 (2007); [12] P.D.Ye, G.D. Wilk. B.Yang, J. Kwo, S.N.G. Chu, S. Nakahara, H.-J.L. Gossmann, J.P. Mannaerts, M. Hong, K.K. Ng, and J. Bude, “GaAs Metal-OxideSemiconductor Field-Effect Transistor with Nanometer thin dielectric grown by atomic layer deposition,” Applied Physics Letters, vol. 83, p.180 (2003); [13] C.H. Huang, M.Y. Yang, A. Chin, W.J. Chen, C.X. Zhu, B.J. Chao, M.-F. Li, and D.L. Kwong, “Very Low Defects and High Performance Ge-on-Insulator pMOSFETs with Al2O3 Gate Dielectric,” Symposium on VLSI Technology Digest of Technical Papers, p.119 (2004); [14] H. Shang, K.-L. Lee, P. Kozlowski, C.D’Emic, I. Babich, E. Sikorski, M. Ieong, H.-S.P. Wong, K. Guarini, and W. Haensch, “Self-Aligned n-Channel Germanium MOSFETs With a Thin Ge Oxynitride Gate Dielectric and Tungsten Gate,” IEEE Electron Device Letters, vol. 25, p.135 (2004); [15] C.O. Chui, H. Kim. P.C. McIntyre, and K.C. Saraswat, “A Germanium NMOSFET Process Integrating Metal Gate and Improved hi-k Dielectric,” IEEE International Electron Device Meeting, p.18.3.1 (2003); 133 Chapter 5: Conclusion [17] E.A. Fitzgerald, “Epitaxial Growth of GaAs/Ge Interfaces,” Abstract of ECS 210th Meeting, p.1460 (2006). 134 Appendix List of Publication Journal Papers • Fei Gao, S.J. Lee, S. Balakumar, and D.-L. Kwong, “Enhancement-mode GaAs metal-oxide-semiconductor field-effect-transistor integrated with thin AlN surface passivation layer and silicon/phosphorus co-implanted source/drain,” Submitted to IEEE Electron Device Letters; • Fei Gao, S.J. Lee, D.Z. Chi, S. Balakumar, and D.-L. Kwong, “GaAs MetalOxide-Semiconductor Device with CVD-HfO2/TaN Gate Stack and Thermal Nitridation Surface Passivation,” Applied Physics Letters, Vol. 90, 252904 (2007); • Fei Gao, S.J. Lee, Li Rui, S.J. Wang, B.J. Cho, S. Balakumar, Chin-Hang Tung, D.Z. Chi, and D.L. Kwong, “SiGe on Insulator MOSFET Integrated with Schottky Source/Drain and HfO2/TaN Gate Stack,” Electrochemical and Solid-State Letters, Vol. 9, G222-G224 (2006); • Fei Gao, S.J. Lee, S. Balakumar, Anyan Du, Yong-Lim Foo, Dim-Lee Kwong, “Ge diffusion and solid phase epitaxy growth to form Si1-xGex/Si and Ge on Insulator Structure,” Thin Solid Films Vol. 504, pp.69-72, (2006); • F. Gao, S. Balakumar, N. Balasubramanian, S.J. Lee, C.H. Tung, R. Kumar, T. Sudhiranjan, Y.L. Foo, and D.-L. Kwong, “High Germanium Content Strained SGOI by Oxidation of Amorphous SiGe Film on SOI substrates,” Electrochemical and Solid-state Letters, Vol. 8, G337-G340, (2005); • Fei Gao, S.J. Lee, J.S. Pan, L.J. Tang, Dim-Lee Kwong, “Surface passivation using ultrathin AlNx film for Ge-metal-oxide-semiconductor devices with Hafnium oxide gate dielectric,” Applied Physics Letters, 86, 113501 (2005); • C.C Yeo, B.J. Cho, F. Gao, S.J. Lee, M.H. Lee, C.-Y. Yu, C.W. Liu, L.J. Tang and T.W. Lee, “Electron Mobility Enhancement Using Ultrathin Pure Ge on Si Substrate,” IEEE Electron Device Letters, Vol. 26, No. 10, (2005); • S. Balakumar, M.M Roy, B. Ramamurthy, C.H. Tung, Gao Fei, S. Tripathy, Chi Dong Zhi, R. Kumar, N. Balasubramanian, and D.L. Kwong, “Fabrication Aspects of Germanium on Insulator from sputtered Ge on Si-substrates” Electrochemical and Solid-State Letters, Vol. G158-G160, (2006); • S. Balakumar, C.H. Tung, G.Q. Lo, R. Kumar, N. Balasubramanian, D.L. Kwong, Gao Fei and S.J. Lee, “Solid Phase Epitaxy during Ge condensation from amorphous SiGe layer on Silicon-on-Insulator substrate,” Applied Physics Letters, Vol. 89, 032101 (2006); 135 Conference Papers • Fei Gao, S.J. Lee, Rui Li, S.J. Whang, S. Balakumar, D.Z. Chi, Chia Ching Kean, S. Vicknesh, C. H. Tung, and D.-L. Kwong, “GaAs p- and n-MOS Devices Integrated with Novel passivation (Plasma Nitridation and AlN-surface passivation) techniques and ALD-HfO2/TaN gate stack,” Technical Digest of International Electron Device Meeting, p. 833, December 2006, San Francisco, USA; • F. Gao, S. Balakumar, L. Rui, S.J. Lee, T Chi Hang, A. Du, S. Tripathy, W.S. Hwang, N. Balasubramanian, G.Q. Lo, D.Z. Chi, and D.L. Kwong, “100 nm Gate Length Pt-Germanosilicide Schottky S/D PMOSFET on SGOI substrate fabricated by novel condensation approach,” 13th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA 2006), Singapore, p.311.July 2006; • F. Gao, S.J. Lee, Rui Li, S. Balakumar, Chin-Hang Tung, Dong-Zhi Chi, and Dim-Lee Kwong, “Schottky Source/Drain Transistor on Thin SiGe on Insulator with HfO2/TaN Gate Stack,” Materials Research Conference---Spring Meeting 2006, San Francisco, USA, 0913-D01-04, April, 2006; • Fei Gao, S.J. Lee, S. Balakumar, Anyan Du, Yong-Lim Foo, Dim-Lee Kwong, “Growth of Si1-xGex/Si and Ge on insulator structure by Ge diffusion and Solid Phase Epitaxy,” 3rd International Conference on Materials for Advanced Technologies, Symposium H: Silicon Microelectronics: Processing to Packaging, MRS Singapore, July, 2005; • Fei Gao, S.J. Lee, J.S. Pan, L.J. Tang, Dim-Lee Kwong, “Thin AlNX passivation for Ge MOSFET application with high-k gate dielectric,” 3rd International Conference on Materials for Advanced Technologies, Symposium H: Silicon Microelectronics: Processing to Packaging, MRS Singapore, July 2005; • S. Balakumar, Fei Gao, S.J. Lee, C.H. Tung, R. Kumar, T. Sudhiranjan, Y.L. Foo, N. Balasubramanian and D.L. Kwong, “A Novel Approach to Fabricate High Ge content SiGe on Insulator from amorphous SiGe deposited on SOI wafers,” Extended Abstract of the 2005 International Conference on Solid State Devices and Materials, Kobe, Japan, 2005, pp.370-371; • S.J. Whang, S.J. Lee, Fei Gao, Nan Wu, C.X. Zhu, Ji Sheng Pan, Lei Jun Tang and D.L. Kwong, “Germanium p- & n-MOSFETs fabricated with Novel surface passivation (Plasma-PH3 and thin AlN) and TaN/HfO2 Gate Stack,” Proceeding of International Electron Device Meeting, 2004, p.307, San Francisco, USA, 2004; • S. Balakumar, M.M. Roy, Ramamurthy, Gao Fei, Chih-Hang, R. Kumar, N. Balasubramanian, S. Tripathy, S.J. Lee, and D.L. Kwong, “Growth and Characterization of Germanium on Insulator (GOI) from Sputtered Ge by Novel 136 Single and Dual Necking techniques,” Extended Abstract of the 2005 International Conference on Solid State Devices and Materials, Kobe, Japan, 2005, pp.770-771; • C.C Yeo, B.J. Cho, H. Yeo, F. Gao, S.J. Lee, C.Y. Yu, C.W. Liu, and L.J. Tang, "Study of pure Ge on Si substrate for nMOSFET with HfAlO as gate dielectric and its thermal stability", 3rd International Conference on Materials for Advanced Technologies, Symposium H: Silicon Microelectronics: Processing to Packaging, p. 13, MRS Singapore, July 2005; Patent • Fei GAO, C.W. Liu, S.J. Lee, D.-L. Kwong, “photodetectors” US-2006-0260676A1; 137 [...]... (Silicon Germanium on insulator) have been proposed including bonding [67] and smart-cut [68], condensation [69] Among them, Ge condensation technique has drawn great attention due to its simple process steps and easy control over Ge concentration This condensation process starts with epitaxial growth of SiGe film on SOI wafer followed by multi-step oxidation process However, since this condensation requires... to 35 nm and 1.2 nm, respectively, for Intel’s 65 nm technology processor [4], further scaling is still required to continue the performance boost In order to keep the historic trend of 17% performance improvement each year, the requirements for industry’s future technology are predicated in ITRS (International Technology Roadmap for Semiconductor) [10] , a document produced by a group of semiconductor... indicates that the Ge film on insulator is single crystal. -78 Figure 3.6 Process for condensation of amorphous SiGe on SOI wafer to form single XI crystal SGOI substrate:(A) a amorphous low Ge content SiGe layer was deposited on a SOI wafer; (B) after high temperature oxidation process, due to condensation, SPE mechanisms, high Ge concentration single crystal SGOI was formed between the BOX and... before the deposition of high- k is also discussed Then, chapter 3 covers fabrication techniques for high mobility channel on insulator structure (SGOI and GOI) In the first part of the chapter, SPE (Solid phase Epitaxy) growth method was proposed for localized GOI fabrication Then in the second part, cost effective novel condensation method would be investigated for high Germanium percentage SGOI substrate... XV Chapter 1: Introduction Chapter 1 Introduction 1.1 Introduction It is regarded by many that semiconductor technology is the foundation of IT (Information Technology) revolution The scale of the semiconductor industry has reached hundreds of billions of dollars, with the estimation that it will account for 2.6% of the world GDP by the year of 2 010 [1] Successful fabrication of the world’s first transistor... the condition that EOT and Vd meet the requirements set by ITRS, together 5 Chapter 1: Introduction with Jg,limit (gate leakage current density limit) for HP, LSP and LOP logic device application [10] Once the Jg,sim is higher the Jg, limit, it means that ITRS’ EOT and gate leakage requirements can not be met by using SiON 4 10 HP 3 10 2 2 Jg (A/cm ) 10 1 10 SiON can't meet ITRS requirement beyong this... surface oxidation of Ge. 35 Figure 2.6 Gate leakage density (normalized at Vg-Vfb=1V) as a function of EOT for AlNX/HfO2 on Ge substrate and HfO2 on Ge substrate with conventional SN treatment (The leakage data for HfO 2 on Ge substrate with SN treatment is from reference [14].)As a reference, the leakage current from SiO2 on the Si substrate is also included All the leakages are from n-type substrates.... depletion effect and challenges in controlling the short channel effects Fundamental changes on the materials and structure of the MOSFET are inevitable in order to continue the historical aggressive scaling for leading-edge logic device The high- k and metal gate technology is needed to replace the SiON and ploySi gate in the near future However, in the long-term for 32 nm technology node and beyond,... current density Jjunction junction current density Is source current of MOSFET k relative permittivity khigh-k permittivity of high- k dielectric K Boltzmann’s constant L channel length of MOSFET ND donor concentration NA acceptor concentration Ni intrinsic carrier density XIV q electronic charge Qn inversion charge density Qb bulk charge density t dielectric thickness thigh-k thickness of high- k gate dielectric... requirement for HP logic device is only 0.75 nm or less from 2009 and onwards, 0.7 nm contribution from quantum effects 6 Chapter 1: Introduction and poly-Si gate depletion is intolerably high, which poses tremendous challenges in meeting the requirement of EOT 1.3 Approaches for Further Scaling Although poly-Si/SiO2(SiON)/Si based MOSFET structure has been adopted by semiconductor industry for many decades, . STUDY ON HIGH MOBILITY CHANNEL TRANSISTORS FOR FUTURE SUB- 10 nm CMOS TECHNOLOGY Fei GAO (B. Eng, Xi’an Jiaotong University, PR CHINA) A THESIS SUBMITTED FOR. STUDY ON HIGH MOBILITY CHANNEL TRANSISTORS FOR FUTURE SUB- 10 nm CMOS TECHNOLOGY FEI GAO NATIONAL UNIVERSITY OF SINGAPORE. Si 0.05 Ge 0.95 /Si Substrate 100 4.2.1 Experiment 100 4.2.2 Results and Discussion 105 4.2.2.1 Gate Stack 105 4.2.2.2 Performance of Long Channel MOSFET 107 4.2.2.3 Performance of Short Channel MOSFET 110