Reliability modeling of ultra thin gate oxide and high k dielectrics for nano scale CMOS devices

RELIABILITY MODELING OF ULTRA-THIN GATE OXIDE AND HIGH-K DIELECTRICS FOR NANO-SCALE CMOS DEVICES LOH WEI YIP B. Eng (Hons), NUS A THESIS SUBMITTED FOR THE DEGREE OF DOCTOR OF PHILOSOPHY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING NATIONAL UNIVERSITY OF SINGAPORE 2004 Acknowledgments First and foremost, my deepest gratitude to my supervisors, Associate Professor Cho Byung Jin and Professor Li Ming Fu, who have given me guidance throughout my study in NUS. In particular, it is Assoc. Prof. Cho who have aspired me to reach for the highest standard in my researches and who have tirelessly reviewed and guided me in all my publications. It is with his help that I am able to produce credible results in the area of oxide and high-K reliability. Gratitude also goes to Prof. Li, who because of his insight and theoretical expertise is able to guide me to seek for a more theoretical understanding in all my researches. Without Assoc. Prof. Cho and Prof. Li’s kind and patient guidance, it would be difficult for me to have completed this thesis. The advices and guidance of other teaching staffs are also gratefully acknowledged. In particular, Prof. Kwong DL, Assoc. Prof. Yoo WJ, Dr. Zhu CX, Dr Lee SJ, Dr. Yeo YC and Mr. Joo MS, have all given me tremendous help, advices and encouragements. I also wish to express my sincere gratitude to my fellow students in Silicon Nano Device Lab. (SNDL) and Center for Integrated Circuits Failure Analysis and Reliability (CICFAR) who have make my stay in NUS a joyful and meaningful experience. In particular, it is most gratifying to have the support and friendship of Mr. Kim Sun Jung who has so willing lend a helpful hand in all my experiments and Dr. Lim Peng Soon who has joined me in many fruitful discussions in both work and social matters. Thanks also go to all my friends including Wu Nan, Ren Chi, Tony Low, Chee Keong, Ng TH, Zerlinda, Tan KM, Chen JH, Wang YQ, Yu HY, Whang SJ, Park CS, and many others who have went out of their way to teach and assist me in this thesis. The support and assistance from all the staffs of SNDL and NUS is also gratefully acknowledged. In particular, Mr. Patrick Tang, Mr. Yong Yu Foo, Mr. Goh Thiam Pheng, Mrs. Ho Chiow Mooi, and Mr. Walter Lim have greatly assisted me in all manners of my administrative duties and experiments. Their kind assistances are greatly appreciated. Last but not least, I wish to dedicate this thesis to my parents, sister, Sook Fen and Gabriel and my dearest Tze Chieg. Without their emotional support, care and concerns, and continuous support and love, I would not have the privilege to even embark on this journey of my life. Summary As complementary metal-oxide semiconductor (CMOS) technology advances, the dimensions of its various key device components are scaled downward, from its present day micrometer range and eventually, to its ultimate limit - the nanometer regime. In this aspect, silicon dioxide (SiO2), which forms the gate insulator for the transistor, is progressively reduced from thick to thin oxide (< 20 Å), ultra-thin ([...]... in gate leakage current is observed in these ultra- thin oxides [1.9] The degradation mechanism, modeling and reliability extrapolation in such thickness regime are necessary for commercial implementation of such ultra- thin oxides and will be studied in chapter five of this thesis Beyond the 65 nm technology node, the International Technology Roadmap for Semiconductors (ITRS) 2003 shows that high- K dielectrics. .. J M Anthony, High- K gate dielectrics : current status and material properities considerations,” J Appl Phys., vol 89, pp 5243-5275, 2001 [1.6] S Song, J H Yi, W S Kim, J S Lee, K Fujihara, H K Kang, J T Moon, and M Y Lee, CMOS Device Scaling Beyond 100nm,” IEDM Tech Dig., pp.235-238, 2000 [1.7] S H Lee, B J Cho, J C Kim, and S H Choi, “Quasi-breakdown of ultrathin gate oxide under high field stress,”... completely lost As a result, it is obvious that for gate dielectrics with equivalent oxide thickness of 13Å and below, other materials such as high- K gate dielectrics will be required [1.3],[1.4] Besides the excessive gate leakage observed in ultra- thin gate dioxides, other hosts of problems also arise from this frantic device scaling In particular, reliability has currently become an important issue... tunneling leakage current will be too high for general device applications, highK dielectrics is needed for the 65 nm technology node Chapter seven studies the reliability of high- K stacks using a novel carrier separation method A time-tobreakdown with polarity dependence, is observed under constant voltage stress and this is attributed to breakdown at different layers within the high- K stacks [1.14]... formation of SiO2 and metal silicides often occurs at the interface [1.5] This decreases the effective dielectric constant and hence its capacitive effect Other issues concerning high- K dielectrics include mobility degradation, boron penetration, thermal stability, high fixed charge density Qf and high gate leakage current [1.5] The introduction of new materials such as high- K gate dielectrics and metal gate. .. instead of 12 months Chapter 1: Introduction 3 MOSFET gate length scaling to continue, the following key issues shown below have to be addressed • Accelerated need for high- K gate dielectric solution for dealing with increased MOSFET gate leakage • Accelerated need for dual metal gate electrodes and next generation contact solutions due to incompatibility of polysilicon with high- K dielectrics and poly... the device scaling for the last thirty years It can be seen that as device channel length is aggressively scaled downward, gate oxide thickness is also scaled to avoid short channel effect and to maintain drive current capability There are, however, increasing evidences that oxide scaling may be reaching a limit due to the tradeoff in gate leakage and oxide reliability for ultra- thin oxides 4 Geometry... it can be observed that gate oxide thickness scaling and unproportionate voltage derating have been accompanied by a host of different reliability issues at each technology node With future incorporation of high- K gate dielectrics, it is expected that a different host of problems will be encountered Fig 2.4 Low-voltage conduction mechanism for thin oxide of various oxide thicknesses (After [2.11]) 2.2... electron-hole pair compensation and the reduction of localized trap region (LTR) The shaded regions represent bandgap narrowing due to formation of LTR while the thick lines show the resultant oxide energy band 107 Fig 6.1 HRTEM cross section of 13 Å gate oxide (left) and C-V measurements and simulation results (solid lines) fitting to 13 Å oxide thickness by Berkeley QMCV modeling (right) ... problems in terms of device reliability, process integration and new types of defect generation and detection The degradation and breakdown mechanism for future high- K dielectrics is presently unclear and may become a potential barrier to successful implementation of high- K dielectrics These issues will become even more critical considering the rapid changes in materials needed to keep pace with dimension . RELIABILITY MODELING OF ULTRA- THIN GATE OXIDE AND HIGH- K DIELECTRICS FOR NANO- SCALE CMOS DEVICES LOH WEI YIP B. Eng (Hons), NUS A THESIS SUBMITTED FOR THE DEGREE OF DOCTOR. thick to thin oxide (< 20 Å), ultra- thin (<15 Å) and eventually to high- K dielectrics. For high performance logic applications, gate oxide thickness scaling is driven by the need for higher. verified. Eventually, high- K dielectrics are required for continual gate dielectric scaling. The reliability for high- K stacks is examined and a novel technique for stack reliability is presented.