3 Layout Planning and Design
4.4 Design Rules for Fast Pulse Circuits
A conductor on a printed circuit will behave as a transmission line if its length l (in meters) is:
l > tr 100 nsec
wheretr= rise-time of the pulse in nsec.
If a fast pulse travels over a line, the following situations can arise:
a If the transmission line or interconnection is matched with both the source and the load, and if the transmission line is not very long, a simple delay of approximately 5 nsec/m is introduced.
a If the transmission is matched at one end, either at source or load, there may be a single reflection, either at source or at the load.
a If the transmission line is mismatched at both ends, multiple reflections will take place, which will create disturbances and considerably slow down the rise and fall times of the pulses. Therefore, a mismatch on both sides must be avoided when dealing with fast pulses.
If the mismatch is upto about ±20 per cent, the resulting pulse will be distorted and could become rounded instead of having sharp edges.
When connecting two PCBs involving connections longer than 10–20 cm, the connection must be made either with coaxial cables or at least with twisted pairs (consisting of a signal wire twisted closely with the ground wire), otherwise complex multiple reflections will take place, causing unpredictable behaviour in the circuit. The wave impedance of commonly used coaxial cables are 50 or 75 W. Twisted pairs have impedances between 100 and 150 W.
In fast pulse circuits, various types of losses and especially skin effect and dielectric losses increase their effect on the rise-time as the conductor length is increased. Therefore, the most important rule in high frequency and pulse circuits is to keep conductors as short as possible. The specific measures taken to reduce such type of losses are detailed below.
a Skin-effect losses: Increase PCB thickness and keep line length small.
a Radiation losses: Use a ground plate on one side of the PCB, decrease PCB thickness and avoid discontinuities. Run signal lines near the ground plane.
a Dielectric losses: Use a good high frequency dielectric PCB laminate.
Because of these losses, the design guidelines are: For very fast pulses (tr< 1 nsec), even matched lines have to be kept very short. Rise-times of matched lines increase by 1 to 10 psec/cm or 100 to 1000 psec/m due to these losses.
The design challenges in high frequency and fast pulse circuits can be summarized as:
a System timing: While designing high frequency PCBs, system timing plays an important role. System timing means checking whether the data get reliably transferred or not? The conductors from one component to another component should be as short as possible to achieve system timing. For example, a high frequency signal conductor with a large length may result in an unintended logic. What was supposed to be read as a 1 will be read as a 0.
a Waveform integrity: Waveform integrity means that the signal should meet electrical requirements. One should get required waveforms similar to simulation results. Waveform integrity can be achieved by calculating the proper wave impedance of signal conductors.
Wave impedance of a signal conductor depends upon the conductor width.
a Cross-talk: Like reflection, cross-talk is a transmission line phenomenon. Cross-talk can be kept low if a ground line or a ground plane is nearby. These cross-talk problems can also be solved by maintaining proper wave impedance of the signal conductor. The wave impedance of a signal conductor depends upon the conductor width. Normally the conductor width is inversely proportional to the wave impedance of a signal conductor.
4.4.1 Controlled Impedance Considerations
It has been explained above that today’s fast switching speeds or high clock rate PCB traces are treated as transmission lines whose electrical characteristics must be controlled by the PCB designer.
Obviously, the critical parameter is the characteristic impedance of the PCB trace. In practice, the trace impedance has to be controlled when designing for digital edge speeds faster than 1ns or analog frequencies greater than 300 MHz. In general, the controlled impedance has to be considered when the electrical length of the signal line exceeds 30 per cent of the signal rise time (Polar Instruments, 2001).
The devices mounted on a PCB themselves possess characteristic impedance and the impedance of the interconnecting PCB traces must be chosen to match the characteristic impedance of the logic family in use. Referring to Figure 4.17, in order to maximize signal transfer from the source (device A) to the load (device B), the trace impedance must match the output impedance of the sending device (device A) and the input impedance of the receiving device (device B). For CMOS and TTL, this will be in the region of 80 to 110 ohms. If the impedance of the PCB trace connecting two
Design Considerations for Special Circuits 173
devices does not match the devices’ characteristic impedance, multiple reflections will occur on the signal line resulting in increased switching times or random errors in the high speed digital system.
Input Output
A B
Controlledimpedance
Terminating resistance Fig. 4.17 Single-ended PCB trace
The single-ended transmission line as shown in the figure is probably the commonest way to connect two devices. In this case, a single conductor connects the source of one device to the load of another device. The reference (ground) plane provides the signal return path. This is an example of an unbalanced line. The signal and return lines differ in geometry—the cross-section of the signal conductor is different from that of the return ground plane conductor.
Controlled impedance PCBs are usually produced by using microstrip or stripline transmission lines in single-ended (unbalanced) or differential (balanced) configurations (Polar Instruments 2003C). The differential mode of operations is shown in Figure 4.18. The differential configuration is used when better noise immunity and improved timing are required in critical applications. This configuration is an example of a balanced line—the signal and return paths have similar geometry.
The lines are driven as a pair with one line transmitting a signal waveform of the opposite polarity to the other. Fields generated in the two lines will tend to cancel each other, so EMI and RFI will be lower than in the case of the unbalanced line, and problems with external noise are reduced.
Controlledimpedance
A B
Output Input
Terminating resistances
Fig. 4.18 Differential PCB trace
The impedance of a trace on a PCB can be controlled by carefully controlling the following geometrical dimensions (Bhardwaj, 2001), as shown in Figure 4.19:
a The width (w) and thickness (t) of the signal trace;
a The height (h) of core or pre-preg material on either side of the trace;
a The dielectric constant (Dk/Er) of the core and pre-preg material; and a The configuration of trace and planes.
W1
W1 T
H Er
The relation between the characteristic impedance of a trace and these physical factors is explained below.
Impedance (Z) is
a inversely proportional to trace width (Zμ 1/W);
a inversely proportional to trace thick- ness (Zμ 1/t);
a proportional to laminate height (Zμ h); and
a inversely proportional to the square root of laminate Er (Zμ 1/ Er).
The impedance of a PCB trace will be determined by its inductive and capacitive reactance, resistance and conductance. PCB impedances will typically range from 25 to 120 ohms. In practice, board designers will specify impedance values and tolerances for board traces and rely on the PCB manufacturer to conform to the specification.
Impedance calculations are usually very complex and depend upon variables that are difficult to control (UltraCAD Design, 2000). However, most applications require constant impedance traces, but not necessarily traces with the exact absolute value of the impedance, except when interfaces with backplanes and other circuit cards are required. Turn and vias generally have a minimal effect on impedance, except that moving a controlled impedance trace from one layer to another can cause significant and subtle problems unless the two layers are on immediately opposite sides of a single power distribution (reference) plane.
Most controlled impedance PCBs undergo 100 per cent testing. Impedance measurements are usually made with a time domain reflectometer (TDR). The TDR applies a fast voltage step to the coupon via a controlled impedance cable and probe. Any reflections in the pulse waveform are displayed on the TDR and indicate a change in impedance value. This is known as a discontinuity (Polar Instruments, 2003 ). The TDR is able to indicate the location and scale of discontinuity.
Using appropriate software, the TDR can be made to plot a graph of the impedance over the length of the test trace on the coupon. The resulting graphical representation of the trace characteristic impedance allows previously complex measurements to be performed in a production environment.