Irrespective of the method used for the preparation of the artwork, some basic guidelines, need to be followed. Although these guidelines are specific to the manual technique of artwork preparation, some of the important criteria like optimization of the number of pad sizes, drill diameters, route length, etc., are also relevant even in the case of automated artwork preparation procedures.
In the PCB libraries for components, major parts such as ICs and connectors are still set in an Inch-based raster. However, there is an increasing trend nowadays to lay on a millimeter raster, specially for new connectors. Therefore, there is a need to convert the information in inches to millimeters, specifically for pads, holes, tracks and clearances. Table 5.1 presents a calculator to assist in making the necessary conversion.
1mil = 1/1000 Inch => 0.0254 mm
Table 5.1 Calculator to Convert mil in mm
PADs Holes Tracks Clearances
mil mm mil mm mil mm mil mm
50 1,3 28 0,7 8 0,2 8 0,2
62 1,6 32 0,8 10 0,25 10 0,25
80 2,0 40 1 15 0,4 15 0,4
100 2,5 48 1,2 20 0,5 -- --
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5.3.1 Conductor Orientation
It is a usual practice to run the conductors basically on one side in the direction of the X-coordinate and on the other side in the direction of the Y-coordinate. This provides a fairly regularly distributed pattern with a minimum number of via holes.
Fillet
Conductor
Roundedcorner and fillets
Preferred for low-voltagecircuit No fillet Sharpcorner and no fillets
90°or greater
Sharpcorner, close spacing
High voltage between conductors
Conductor
Nonpreferred
High-voltage application
Generously rounded outercorner Preferred
Conductor R
Less than 90°
Less than 90°
No fillet pocket makes cleaning difficult
Generous outer radius,cleaning problem the same
Nonpreferred Nonpreferred
Closed-anglecircuit path
Preferred
Fig. 5.4 Conductor shapes — conductor angles
Conductor angles should be made at 45 or 90 degrees or 30/60 degrees. This is mainly adopted for the layout design of digital circuits. For analog boards, the bends are usually made in the form of arcs. Figure 5.4 shows preferred angles of taping an artwork. Although the traces could be directed at almost any angle, it is important that all traces running parallel lie at the same angle for uniformity.
It would also ensure optimum utilization of the space available and give a good appearance.
5.3.2 Conductor Routing
The following guidelines are suggested in respect of conductor routing:
a Even in circuit patterns where plenty of space is available and the conductors can be run in any direction, it is essential to give the shortest (Figure 5.5) interconnection length. This is especially true in case of high frequency PCBs.
Normally, it is a good rule to begin and end the conductors in a solder pad or in another pad.
But if this practice results in an increase in the length of the conductor, it can also be terminated by joining it to another conductor.
a The minimum angle that any trace should be placed at is 60 degrees. Angles of less than 60 degrees create a situation during the manufacturing process which could allow the etching solution to build upon the inside angle and etch away excess material as illustrated in Figure 5.6.
Nonpreferred Preferred
Fig. 5.6 Conductor routing—avoid sharp internal angles
a Conductors running parallel must preferably be at the same angle (Figure 5.7) to ensure uniformity. This eliminates the variance in the conductor to conductor spacing.
a Where one or several conductors have to pass between pads or other conductive areas, the spacing has to be equally distributed. Maximum spacing is obtained if conductors are put perpendicular to a narrow passage. Figure 5.8 shows how the available space is optimally utilized.
Not recommended Recommended
Fig. 5.5 Conductor routing — minimum conductor length
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Parallelconductors
Nonpreferred
Preferred
Preferred
Nonpreferred Fig. 5.7 Conductor routing — parallel pattern Fig. 5.8 Conductor routing — utilize available space to
optimum extent
a Closely-spaced parallel running con- ductors can result in manufacturing problems. In order to avoid this, the conductor should be as w idely spread as possible over the available area.
a Conductor routing must ensure that there is no unwanted bunching (Figure 5.9) of paths at the same point. The routing should also avoid grouping number of conductors at the same solder pad.
a Generally, the conductor widths are chosen based on the current carrying capacity required by specific signal or line. However, it is preferable to adopt standardization, and also keep the number of conductors widths used in
any layout to the minimum. The recommended widths of conductors are:
a Signals : 0.2 mm to 0.3 mm a Power Lines : 0.762 mm to 1.5 mm
(depends on current) a Ground Lines : 1,0 mm to 2.0 mm
(depends on current)
a The ground conductor width should always be greater than the power line widths. The conductor width is normally chosen while assuming temperature rise of a maximum of 20°C.
Acceptable Nonacceptable
Fig. 5.9 Conductor routing — no bunching is acceptable
a The conductor routing must generally avoid passing in between pads resulting in narrow gaps between the pad and the trace, if an alternative path can be worked out. This minimizes the rejection at the manufacturing stage. Figure 5.10 shows some of the preferred routing patterns. The aim of any routing method should be to minimize the route length.
Not recommended Recommended
Fig. 5.10 Preferred routing pattern of conductors
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a The routing pattern should preferably be distributed equally between the various layers of the PCB. For example, in a double-sided PCB, this applies to the solder and component side. This helps in the manufacturing process by way of ensuring uniform plating in case route densities are equally distributed.
Scaminaci (1994) states that the major causes of system noise begin during the artwork design stage. By incorporating the following guidelines, it is possible to keep system interconnect noise to a minimum:
a Route critical signal nets on a common signal layer. Keep line distances as short as possible.
Avoid changing layers for a single net. Layer-to-layer signal runs will cause reflections and lower line impedance.
a Run adjacent signal layers orthogonally (mutually perpendicular) to each other.
a Isolate signal layers from each other by placing ground or voltage planes between them.
a Running ground isolation traces between signal lines will reduce noise but will also slightly lower the trace impedance.
a Route parallel signal lines as far apart as possible.
a Differential pair traces must have the same length.
a Space signal lines equally in routing channels, keeping a maximum distance from connector pads.
a Run a trace directly to a connector pad without line branching. This will prevent reflections and impedance changes. Common connector points can then be made.
a Use curves or two 45-degree turns to avoid minor line reflections.
a Minimize vias or through-holes as far as possible. Every plated through-hole in a net will add to the distributed capacitance of the line. If through-holes are unavoidable, via drill size should be the same as that of the connector; this will lower fabrication costs and maintain the same aspect ratio.
a Avoid line width changes through connector pin fields, and use single trace routing if possible.
a Use the widest line width possible to reduce the dc resistance.
a Signal surface layers are the most difficult to control with respect to line width and copper thickness. Only non-critical signals should run on the outside layers.
a Pads with soldered signal traces should be tear-dropped at the pad junction.
For reference planes, the following points should be kept in mind:
a Maintain a solid ground or voltage plane for signal layers that are impedance-controlled and referenced to those layers
a Keep the ground returns common to the logic family.
a Multiple ground and voltage planes provide the current handling support and low inductance ground return to minimize ground bounce.
a Use minimum diameter clearance pads for maximum copper web within the connector fields.
a Full ground and voltage planes located back-to-back with minimum dielectric separation, develop a capacitor which helps in filtering high-frequency noise in the voltage supply.
a Soldered pads should be thermally relieved.
5.3.3 Conductor Spacing
The fundamental principle in determining the minimum spacing requirements between conductors is that spacing should be provided only when it cannot be avoided. The PCB manufacturing process specifications play an important role in spacing considerations. Mainly, the plating process must be indicated. For example, in pattern plating, a conductor width increase which can be as much as 125mm, can take place whereas in panel plating, width reduction of the same magnitude can result due to under-etching. The width change also depends upon the thickness of the copper foil in subtractive PCB processes and also on the image transfer method used, i.e. wet-film resist, dry film resist, screen printing, etc.
In order to rule out the chances of a voltage flash-over between conductors due to insulation failure, minimum spacing requirements with respect to voltage are usefully specified. The specified value must be maintained under all circumstances including the worst case tolerances of artwork generation and PCB processing.
600
500
400
300
200
100
00 2 4 6 8 10 0 2 4 6 8 10 12 14 [mm]
Conductor Spacing [V]
Voltage DCorACpeak With
protective coating
Without protective coating, normal conditions
Without protective coating, dirty and dustyconditions
Below10,000ft
Without protective coating
Without protective coating
Above10,000ft
Fig. 5.11 Minimum spacing requirements as per MIL Std. 275B (redrawn after Bosshart, 1983)
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Minimum spacing specifications are available in the standards issued by various international agencies such as IPC (Institute for Interconnecting and Packaging Electronic Circuits), IEC (International Electrotechnical Commission), MIL (US Military Standard), and UL (Under - writers Laboratories). As a guide, spacing specifications are divided for PCB applications in altitudes below and above 10,000 ft. (3048 m) and whether or not a protective coating is applied on the PCB.
Figure 5.11 shows minimum spacing requirements as per MIL 275 B.
5.3.4 Hole Diameter and Solder Pad Diameter 5.3.4.1 Hole Diameter
It is essential that the component lead should be fitted only into the hole of an appropriate diameter.
The hole must allow easy insertion of components without excessive pressure. At the same time, it must be large enough to allow gases generated at the time of wave soldering to escape, otherwise blow holes may develop at the solder joints and inside the through-holes, thereby reducing reliability.
At the same time, the number of different hole diameters on a PCB must be kept at a minimum.
Therefore, it is essential to optimize the number of drill sizes, otherwise it adds to the cost of manufacturing. For satisfactory soldering, the hole diameter of finished and plated holes should give about 0.2-0.5 mm clearance as compared with the nominal diameter of the component lead.
For the hole diameter drilling, tolerances should also be taken into consideration, which are:
For nominal drill dia < 0.8………+ 0.10 mm For nominal drill dia > 0.8……….+ 0.13 mm
Using this as a guideline, the nominal drill size is normally slated to be about 0.2-0.5 mm larger than the component lead diameter. Drill holes have been standardized as 0.8, 1.0, 1.3, 1.5 and 1.6 mm.
The degree of complexity of the circuit mainly decides the density of the conductor patterns.
Each company has its own standards of this kind. For example, Table 5.2 shows PCB classification according to complexity.
Table 5.2 PCB Classification according to Complexity*
(all figures in mm)
Item Single-sided Double-sided PTH
Consumer Professional Low Density High Density
D=most used 0.8 - 1.5 0.8 - 1.5 0.8 - 1.2 0.6 - 1.0
Hole diamter
Copper and D plus D plus D plus D plus
diameter 1.0 - 2.0 0.8 - 1.3 0.4 - 1.0 0.3 - 0.6
(Contd.)
Table 5.2 (Contd.)
Minimum path 0.8 0.5 0.35 0.15
width (excluding limited lengths)
Minimum 0.6 0.4 0.3 0.2
clearance between adjacent conductors
Overall tolerance 0.1 - 0.2 0.1 - 0.15 0.05 - 0.1 0.05 - 0.075 on hole positions
Note*Redrawn after Leonida, 1981.
It may be noted that even if four different standards are shown, yet there is no clear division between classes and that a single PCB can belong to different classes according to different factors.
Holes drilled for mounted leaded components and vias must be of the current size. If the drilled hole is plated for through-hole mounting of components, allowance for the plating thickness should be made. The preferred drill sizes such as 0.4, 0.5, 0.6, 0.8. 0.9, 1.0, 1.3, 1.6 and 2.0 mm in diameter are often specified in some standards. As a general rule, the minimum drilled hole is about one-third the board thickness. For example, for a board thickness of 1.6 mm, the hole diameter is 0.6 mm. For standard dual-in-line packages, a drill size of 0.8 mm is common. Some basic guidelines regarding holes are:
a The number of hole diameters on a PCB has to be kept at a minimum. One may vary the hole sizes within the range given to minimize the different sizes used, but remember that a hole which is larger than the ranges shown may be difficult to solder.
a Satisfactory soldering results are usually obtained, if the diameter of the finalized and plated holes gives about 0.2-0.5 mm clearance as compared with the nominal diameter of the component lead.
a Hole diameter = effective lead diameter + hole location tolerance (PTH) + 0.2 mm.
The pad or land size in relation to the hole depends upon whether the land has to support a leaded component or whether it will be plated. If D is the land or pad diameter and d is the drilled hole diameter, then the recommendations are:
D/d ≥ 40 mil (1 mm) for non-plated holes
≥ 20 mil (0.5 mm) for plated through-hole.
The board material is important in the determination of the pad and hole sizes.
D/d = 2.5 to 3.0 for non-plated holes in phenolic boards
= 1.8 to 3.0 for non-plated holes in epoxy boards
= 1.5 to 2.0 for plated through-holes.
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As illustrated in Figure 5.12, the solder mask for pads or lands used to mount through-hole leaded component must allow at least a 0.25 mm clearance around the pad. The edges of the pad are to be covered by the solder mask.
Pad area
Drilledcentre hole
Copper track Solder mask
³10 mil (0.25 mm)
Fig. 5.12 Solder mask minimum dimension overlap for a leaded component land (redrawn after Haskard, 1997)
Table 5.3 gives the lead thicknesses and spacing for the commonly used components in electronic products. Also, given in the table are minimum standard hole sizes that are required to be used for these components.
Table 5.3 Typical Component Lead Sizes (After George, 1999)
Component type Lead Lead Standard
spacing thickness hole Size
1/4 W Resistor 0.400" 0.023" 0.028"
1/4 W Carbon Comp Resistor 0.400" 0.025" 0.028"
1/2 W Carbon Comp Resistor 0.600" 0.032" 0.035"
1 W Carbon Comp Resistor 0.900" 0.041" 0.052"
2 W Carbon Comp Resistor 1.000" 0.045" 0.052"
Small Ceramic Capacitor 0.100" 0.020" 0.028"
Large Ceramic Capacitor (>0.2 uf) 0.200" 0.020" 0.028"
Small Silver Mica Capacitor 0.150" 0.015" 0.028"
Small Transistors (TO-92) 0.050" 0.018" 0.028"
Power Transistors (TO-220) 0.100" 0.036" 0.042"
T-1 3/4 LED 0.100" 0.028" 0.035"
Small Crystal 0.200" 0.018" 0.028"
(Contd.)
Table 5.3 (Contd.)
IC 0.100" 0.023" 0.028"
IC Machine Pin Socket 0.100" 0.020" 0.028"
IC Solder Socket 0.100" 0.025" 0.028"
Headers/Jumpers 0.100" 0.035" 0.042"
Large Headers 0.156" 0.063" 0.086"
D Connector 0.109" 0.035" 0.042"
#4 Clear Hole N/A 0.124" 0.125"
#6 Clear Hole N/A 0.150" 0.156"
Note*For conversion to millimeters: 1 inch = 25.3994 millimeters.
5.3.4.2. Solder Pad Diameter
Pads are the entities that interface the part pins to the copper traces of the board. The hole in the pad must be big enough to allow for variations in the pin size, in the hole size, in the hole location and in the pin location. The pad must be big enough to ensure that the hole always has some copper around it on the surfaces of the board. Therefore, the diameter of the solder pad with respect to the finished hole diameter is very important for reliable solder joints. Generally, in PCBs with plated through-holes, the widths of the annular ring should be between 0.3 to 0.6 mm. For non-plated through-hole PCBs, the solder pad size must be bigger because there is no through-plating to give mechanical strength to the solder pads. It is however, essential to provide a sufficient solder pad size in order to avoid broken annular rings because of drill position tolerances. In addition, another important consideration is the size of the solder pad and width of the joining conductor. The conductor width should always be less than the solder pad diameter, preferably about one-third as shown in Figure 5.13.
Dê3 W D
W
Not recommended Recommended
Fig. 5.13 Solder pad diameter and conductor width
Figure 5.14 gives an idea of the preferred and minimum pad sizes applicable for a range of drill diameters. For example, for a drill size of 0.85 mm to 1.3 mm, a solder pad size of 2.54 mm can be used. However, for this range of drill dia, the solder pad size of 1.98 mm meets the minimum criterion only. The solder pad size is specific to manual artwork generation only. The following are important solder pad diameter rules:
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10.16mm 0.400 in
7.92 mm 0.312 in 5.54 mm 0.218 in
4:1 1:1 Type
C B 2.54 mm A 0.100 in
1.98 mm 0.078 in 1.39mm 0.055 in
0.025 0.03 0.035 0.04 0.045 0.05 0.055 in Minimum
Preferred Minimum
Preferred
0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3mm
Solder pads Solder hole (finished diameter)
Fig. 5.14 Preferred maximum and minimum pad sizes applicable to a range of drill diameter
a In PCBs with PTH, the widths of the annular ring (Masaoka, et al, 1993) should be at least 0.5 mm, but without PTH, the annular rings must be more because there is no through-hole plating to impart mechanical strength to the solder pads.
a As a rule, the solder pad diameter is approximately three times the component lead diameter.
a The pads are always placed exactly and properly centred on grid intersections.
a The conductor width should always be less than the solder pad diameter.
a The pattern around the hole should be maintained as uniformly as possible to enable symmetrical solder points.
The main issues pertaining to pad sizes are solderability and manufacturability. Solderability is a matter of skill whereas manufacturability is concerned with the issue that the pad will not be broken when the hole is drilled in it. If a drill hole is slightly off centre, the pad may be broken at one edge, possibly leading to an open in the circuit. A standard requirement for pad sizes is a 5 mil annulus.
This means there must be 0.005" all around the hole (i.e. a 28 mil hole would require a 38 mil pad).
Something a little larger than this (maybe 10 mils) is recommended for solderability. In exceptional cases, a 2.5 mil annulus, (i.e. a 20 mil hole with only a 25 mil pad), can be used but is not usually recommended (www.leonardo.caltech.edu).
Ball grid array (BGA), fine pitch ball grid array (FBGA), and other chip-scale packages (ACSP) require special consideration for successful assembly. As package geometry continues to shrink, processing margins decrease when compared to leaded packages. Therefore, proper pad layout is essential to achieve reliable solder joint structure in such cases. A traditional BGA package has a ball grid pitch of 1.0 mm pitch or greater. An FBGA package is defined as a ball grid array (BGA) with a ball-to-ball pitch of 0.80 mm or less. In both cases, a substrate interposer is used to re- distribute the IC I§Os to the grid of solder balls. For PCB pad layout, it is recommended to follow the IPC-SM-782A, “Surface Mount Design and Land Pattern Standard” requirements. Table 5.4 gives examples of pad sizes and tolerances recommended for various components.
Table 5.4 Recommended Nominal Values (mm) for BGA (Courtesy Micron Technology Inc.)
BGA BGA Ball PCB Foil Square
pitch pad size diameter* pad size thickness aperture
1.25 0.60 0.75 0.60 0.127 0.60`
1.00 0.33 0.40 0.33 0.102 0.33
0.80 0.33 0.40 0.33 0.102 0.33
0.75 0.27 0.35 0.27 0.102 0.27
Note*Ball diameter measured prior to mounting and re-flow.
5.3.5 The Square Land/Pad
The square land/pad is a common method to designate the polarity or orientation of a component.
For polarized components that have positive or anode lead marked, the square land typically indicates where the positive lead should be placed. For components which have the negative or cathode lead marked, such as diodes or LEDs, the square land indicates where the marked negative lead should be placed.
Similarly, the square land is often used to indicate where the marked lead or pin-1 of a multi- pinned component should be placed. This facilitates proper orientation of the components on the surface board.
In case of integrated circuits, the orientation symbol is usually Pin-1 of the IC. In such cases matching orientation marks are made on the printed circuit board with silk screened symbols and markings.