3 Layout Planning and Design
4.7 High-density Interconnection Structures
The increasing use of fine pitch ball grid array (BGA), chip scale packaging (CSP) and other evolving technology factors means that new design and fabrication techniques must be adopted for PCBs to accommodate components with extremely tight pitches and small geometries. Besides, extremely fast clock speed and high signal bandwidths necessitate board configurations that overcome the negative effects exerted by radio frequency (RF) and electromagnetic interferences (EMI) on a product performance. In addition, increasingly restrictive cost targets limit the use of traditional methods for fabricating smaller, denser, lighter and faster interconnect systems. The use of PCBs incorporating microvia circuit interconnects represents a viable way of addressing solutions to these problems (Brist et al; 1997).
Microvias are vias of less than or equal to 6 mils (150 micron) in diameter. Their most typical use today is in blind and buried vias used to create interconnections through one dielectric layer within a PCB. Microvias are commonly used in blind via constructions where the outer layers of a multi- layer PCB are connected to the next adjacent signal layer. Used in all forms of electronic products, they effectively allow for the cost-effective fabrication of high-density assemblies. The IPC has selected High-Density Interconnection Structures (HDIS) as a term to refer to all the various microvia technologies (Holden, 2003a).
By using microvias, components can be placed much closer to each other thereby freeing up the trace routable area. Microvias can be placed directly in landing pads, eliminating the need for fan- out of short traces that connect pads to hole. Increasing the density of board components can sometimes make it possible to place all the components on one side of the board, thus eliminating the expense of double-sided component assembly. Figure 4.37 shows the reduction in size of the printed circuit board through the conventional and microvia way.
³150mil
~60mil chip 1
FP,XFP
'Oldway'(Fan out) Microviaway vias in pads
chip 2 FP,XFP
chip 1 FP,XFP
–30mil
chip 2 FP,XFP
Minimum chip spacing:~ 150mil Minimum chip spacing:~30mil
Fig. 4.37 Using microvias, components can be placed much closer to each other, freeing up the trace routable area (courtesy Merix Corporation)
The PCB density can be measured by its wiring capacity which is measured in inches of wiring per square inch of substrate. The total wiring capacity of a board depends on the channel width and the number of tracks per channel. Channel width is the distance between adjacent via or component pads, and tracks per channel refer to the number of traces that can be routed on one channel width.
The number of tracks per channel depend, of course, on the trace and space widths, and the pad sizes. The reduction in via pad size with microvia design makes it possible to achieve much higher wiring density.
Blind and buried vias (Figure 4.38) further help to reduce the size of the board and the layer counts. They connect only those layers that require connection. By definition, a blind via is a copper plated hole, just like a regular via, except that it interconnects only one external layer of the PCB with one or more internal layers, but does not go all the way through the board. A buried via is a copper plated hole that interconnects one or more internal layers, but does not connect to an external layer, hence the hole is completely internal or buried within the board. Today’s semiconductor packages demand more interconnections, and blind and buried vias provide a creative means of fitting those connections into less space.
Buried via
Plated through hole
Blind via
Fig. 4.38 Blind and buried vias enable to fit more interconnections in less space
4.7.1 Drivers for HDI
4.7.1.1 Density
Semiconductor complexity and increases in total gates have necessitated more pins for integrated circuits (ICs) as well as finer pin pitch. Over 2000 pins on a 1.0 mm pitch BGA is not unusual, nor is 296 pins on a 0.65 mm pitch device. As discrete components continue to get smaller and IC packages are increasingly becoming BGAs, the total number of connections on both sides of a board increases. When the average connection per square inch begins to exceed 100 pins (connections) per sq. inch, there is less room to wire up these devices. The space occupied by the SMT land pattern, the through-hole via and the traces that connect them, begin to exceed what you can put in a single square inch. Beyond around 120 connections per square inch, additional layers have to be added to complete the interconnect. The layer count begins to go up exponentially as shown in Figure 4.39.
Design Considerations for Special Circuits 187
0 10 20 30 40 50
60 Total layers
Signal layers
No.oflayers
20 40 60 80 100 120 140
Technology:pins sq. in.
Through-hole density
A,B,C
A¢,B¢,C¢
Fig. 4.39 Relationship between pin count and umber of layers. As the pins per square inch goes above 130, the total number of layers grow exponentially(after Holden, 2003a)
Faster rise-times as well as the need for signal integrity (SI) necessitate an increasing number of power and ground pins. Consequently, this creates the need for layers in multi-layer boards and the need for HDI with microvias (Holden, 2003a).
4.7.1.2 Fine Pitch Devices
1.0 mm pitch devices benefit from HDI, but the use of 0.8 mm pitch devices (Holden, 2003b) is where HDI really begins to provide advantages. The blind vias save room on inner layers and have reduced via lands, besides making via-in-lands possible. Typical of these devices is the 240 pin, 0.65 mm pitch, Digital Signal Processor (DSP).
4.7.1.3 High I/O Area Arrays
The other new components becoming more widespread are ones with very high pin counts of around 600 to 2500 pins, even at 1.27 mm and 1.0 mm pitches. While some of these are telecom digital switches, the vast majority are the new field programmable gate arrays (FPGAs). Current products have packages with 240 to 1200 pins.
4.7.2 Advantages of HDI
Microvias offer several distinct advantages over their mechanically created counterparts. These are listed below.
a Systems with higher circuit density with better electrical performance can be created by using the smallest and the most advanced components available. As a result, smaller, lighter and more robust products can be built. They enable greater track density, which, ‘in turn’, increases the potential for layer count reduction and reduced fabrication cost.
a Microvias reduce switching noise, which is attributed to the decreased inductance and capacitance of the microvia as its physical size becomes smaller and shorter. There is a reduction in signal reflection and cross-talk between traces.
a Due to increase in the routability area, it is possible to place more ground plane around components. By doing this, the size of the ground return loops decreases, resulting in a reduction of radio frequency and electromagnetic interferences.
a Microvias require the use of fewer materials and fewer processing steps, both of which reduce the cost of manufacturing the product.
a Microvias are made with photo definition, laser ablation, or plasma-etching and offer distinct advantages over their mechanically drilled counterparts.
4.7.3 Designing for HDI
IPC has developed standards with which the board designers must be thoroughly familiar. The basic information required for this purpose is as follows:
a IPC HDI Standards (IPC-2315, IPC-4104, IPC-6016, IPC-9151 [2]);
a Material selection (IPC-4104); and a Stack-up and design rules (IPC-2315).
IPC HDI Design Standards (IPC-2315): This would be helpful to select the minimum and simplest technology/architectures for the design. Figure 4.40 shows the most common microvias structures from the simplest (type 1) to the most complex (type 3) with stacked vias.
Fig. 4.40 The IPC HDI Type I to Type III are the most common microvia structures used from the simplest (Type I) to the most complex (Type III with stacked vias).
Material Selection: The most important step in HDI design is the selection of materials as they determine performance and fabrication technology. When designing for HDI, one can choose from an increasing range of new materials available that are not commonly used for conventional multi- layer boards. Glass-reinforced laminates and resin-coated copper foils are the most popular HDI materials (Holden, 1997).
Design Considerations for Special Circuits 189
Stack-up and Design Rules: The selection of signal layer stack-up and design rules determines the maximum wiring capability (Wc) for a design. The schematic and total component parts list, along with their connections, can be used to estimate the total wiring lengths required to connect this design. This is the wiring demand (Wd). The actual wring capacity is the maximum wiring capacity multiplied by the design layout efficiency (LE). The actual wiring capacity must always be larger than the wiring demand, Wd < = LE * Wc (Holden, 2003b)
The layout efficiency (LE) is the ability to deliver the design rules to the final product. The higher the layout efficiency, the smaller or fewer signal layers will be required.
Holden (2003b) suggests that if you plan to design a HDI board, start by setting up your CAD system and create a test vehicle as your first HDI board. A simple test vehicle of fine-pitch BGAs land patterns, via-in-pads, in-circuit assembly test schemes, high-frequency test structures and reliability daisy-chains will all help to answer nagging questions and provide an insight on HDI without critically obstructing some new project. The help of a typical CAD menu, which defines the HDI microvia structure in a PCB design, is always available in the packages such as the one from Mentor Graphics.
One very useful HDI design technique is to use the blind vias to open up more routing space on the inner layer. This is shown in Figure 4.41. By using blind vias, the routing space effectively doubles on the inner layers and many more traces can be used to connect pins on the inner rows of a BGA. With this technique, half to one-third the number of signal layers is required to connect a complex, high-I/O BGA.
3.5mil line and 4 mil space 5mil line and5mil space 0.8 mm (31.5 miis) Pitch
With through-holes HDIblind vias effective 1.6mm pitch on drilled holes!
Subsequent Signal Layers only 1 rowescaped
4 channels-5mil lines,5mil spaces 5channels-4 mil lines, 4 mil spaces
31.5mils
20mil 8mil
8mil 20mil
Fig. 4.41 Channel routing utilizes blind vias to create an inner-layer channel to route out interior pins on devices (courtesy Merix Corporation)
Many HDI boards have controlled impedance requirements as in conventional PCBs. When edge speeds are fast and traces are long in comparison, then impedance needs to be taken into account. In case of boards having a design for both low voltage and high speed, the noise margin will be lower and hence more susceptible to changes in impedance -causing reflections (Gaudion, 2000),