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Xây dựng bộ điều khiển và nhận dạng tiếng nói bằng sử lý tín hiệu số DSP 56002

PHUÏ LUÏC B

CODEC 4215

Input Levels : Logic 0 = 0V, Logic 1 = VD1,VD2;Full Scale Input Sine wave,No Gain , No Attenuation 1 kHz ; Conversion Rate = 48kHz;No Gain,No Attenuation , SCLK = 3.072MHz , Measurement Bandwidth is 10Hz to 20kHz ; Slave Mode;Unless otherwise specified )

Parameter* Symbol Min Typ Max Units

Analog Input Characteristics-Minimum Gain setting(0 dB); Unless otherwise specified

Instantanneous Dynamic Range :Line Inputs Mic Inputs

-dBdBTotal Harmonic Distortion : Line Inputs

Mic Inputs THD

%%Interchannel Isolation : Line to Line Inputs

Line to Mic Inputs

-dBdBInterchannel Gain Mismatch : Line Inputs

Mic Inputs

dBdBFrequency Respone (Note 1) (0 to 0.45 Fs ) -0.5 - +0.2 dBProgrammable Input Gain: Line Inputs

Mic Inputs

Offset Error Line Inputs (AC coupled)With HPF = 0 Line Inputs (DC coupled)(No Gain) Mic Inputs

With HPF=1 Line Inputs(DC coupled)(No Gain) (Notes 1,2) Mic Inputs

LSBFull Scale Input Voltage:(MLB=0) Mic Inputs

(MLB=1) Mic Inputs Line Inputs

CMOUT Output Voltage (Note 4)

Parameter* Symbol Min Typ Max Units

Analog Output Characteristics – Minimum Attenuation ;Unless Otherwise Specified

Instantanneous Dynamic Range (OLB=1) (All Outputs)

Total Harmonic Distortion: Line Out(Note 5) (OLB = 1) Headphone Out(Note 6) Speaker Out(Note 6)

%%%Interchannel Isolation : Line Out(Note 5)

Headphone Out(Note 6)

-dBdBInterchannel Gain Mismatch : Line Out

Headphone

dBdBFrequency Respone (Note 1) (0 to 0.45 Fs ) -0.5 - +0.2 dBProgrammable Attenuation (All Outputs) 0.2 - -94.7 dB

0

Full Scale Output Voltage Line Output (Note 5)

with OLB = 1 Headphone Output (Note 6) Speaker Output-Differential (Note 6)

VppVppVppExternal Load Impedance Line Output

Headphone Output Speaker Output

Out of Band Energy(22kHz to 100kHz) Line Out

5. 10kΩ ,100pF load Headphone and Speaker outputs disabled

6. 48Ω,100pF load For the Headphone outputs , THD with 10kΩ ,100pF load is 0.02%

A/D DECIMATION FILTER CHARACTERISTICS

D/A INTERPOLATON FILTER CHARACTERISTICS

High-level Output Voltage at I 0=2.0mA

Low-level Output Voltage at

Output Leakage Current

SWITCHING CHARACTERISTICS(T A =25oC ;VA1,VA2,VD1,VD2 = +5V ,outputs loaded with 30pF ;Inputs Level ; Logic 0 = 0V , Logic 1 =VD1,VD2 )

SCLK period Master Mode,XCLK=1(Note 8)

Slave Mode(XCLK=0) t sckwt sckw

-snsSCLK high time Slave Mode,XCLK

SCLK low time Slave Mode,XCLK

Output to Hi-Z state Time Slot 8 , Bit 0 t hz - - 12 nsOutput to non Hi-Z Time Slot 1 , Bit 7 t nz 15 - - nsInput Clock Frequency Crystals

CLKIN (note 10) 1.204- -- 13.527 MhzMhz

8 In Master mode with BSEL1,0 set to 64 or 128 bits per frame (bpf) ,the SCLK duty cycle is 50% When BSEL1,0 is set to 256 bpf , SCLK will have the same duty cycle as CLKOUT See Internal Clock Generation section

9 In Slave Mode ,FSYNC and SCLK must bederived from the master clock running the codec (CLKIN , XTAL1,XTAL2)

10 Sample rate specifications must not be exceeded

11 After powering up the CS4215 ,RESET should be held low for 50 ms to allow the voltage reference to settle

ABSOLUTE MAXIMUM RATINGS(AGND, DGND = 0V, all voltages with respect to 0V)

Power Supplies : Digital

Analog VD1,VD2VA1,VA2 -0.3-0.3 6.06.0 VVInput Current (Except Supply Pins) - mA

Ambient Temperature (Power Aplied) -55 OC

Power Supplies : Digital (Note 8)

Analog (Note 8) VD1,VD2VA1,VA2 4.754.75 5.05.0 VV

Note : 8 VD−VA must be less than 0.5Volts (one diode drop)

Data Sheet Conventions

This data sheet uses the following conventions :

•OVERBARS are used to indicate a signal that is active when pulled to ground (see Table 1)e.g the HREQ pin is active when pulled to ground Therefore , references to the HREQ pin will always have an overbar

•The word “assert” (see Table 1) means that a high true (active high ) signal is puulled high to VCC or that a low true (active low) signal is pulled low to ground

•The word “deassert” (see Table 1) means that a high true signal is pulled low to ground or that a low true signal is pulled high to VCC

Table 1 High True / Low True Signal Conventions

NOTES :

1 PIN is a generic term for any pin on the chip

2 Ground is an acceptable low voltage level See the DC electrical specifications for the range of acceptable low voltage levels (typically a TTL logic low)

3 VCC is an acceptable high voltage level See the DC electrical specifications for the range of acceptable high voltge levels (typically a TTL logic high)

Pin Groupings

The input and output signals of the DSP56002 are organized into functional groups as shown in Table 2

Table 2 DSP56002 functional Pin Groupings

* alternately , general purpose I/O pins** package dependent

Electrical Specifications

DSP56002 ( 5.0 Volt Operation)

The DSP56002 is fabricated in high desity CMOS with TTL compatible inputs and outputs

Table 3 Absolute Maximum Ratings (GND = 0 Vdc)

VCC +0.5

VCurrent Drain per Pin Excluding

Junctionto Case

(estimated) θJC 13 oC/W θJC 6.5 oC/W θJC 12 oC/W

Input High Voltage

•Except EXTAL , RESET , MODA , MODB , MODC

•MODA , MODB , MODC

•Except EXTAL ,MODA,MODB,MODC•EXTAL

•MODA , MODB , MODC

VVVInput Leakage Current

EXTAL, RESET ,MODA/IRQA, MODB/ IRQB , MODC/ NMI , BR , WT

Three-State(Off-State) Input Current (@2.4V / 0.4V)

Output Low Voltage(IOL = 3mA ; HREQ IOL = 6.7mA,TXD IOL = 6.7mA)

µInternal Supply Current at 66MHz(See Note3)

• in Wait Mode (See Note 1) • in Stop Mode (See Note 1)

ICCW

µPLL Supply Current (See Note 4 ) at 40MHz

at 66MHz -- 1.11 1.51.5 mAmACKOUT Supply Current at 40MHz

2 Periodically sampled and not 100% tested

3. Power Consumption in the Design Considerations section describes how to calculate

the external supply current.4 Value given are for PLL enabled.

AC Electrical Characteristics

The timing waveforms in the AC Electricl Characteristics are tested with a VIL maximum of 0.5V and a VIH minimum of 2.4V for all pins, except EXTAL, RESET, MODA, MODB, and MODC These four pins are tested using the input levels set forth in the DC Electrical Characteristics section AC timing specifications which are referenced to a device input signal aremeasured in production with respect to the 50% point of the respective input signal‘s transition DSP56002 output levels are measured with the producion test machine VOL and VOH reference level set at 0.8 V and 2.0 V respectively.

Internal Clocks

For each occurrence of TH, TL,TC or ICYC substitube with the expressions given in Table 6 ETH, ETL, and ETC are further defined in the Table 7 DF and MF are PLL devision and multiplication factors set registers.

Table 6 Internal Clocks

Internal Clock High Period-with PLL disabled

-with PLL enabled and MF≤4-with PLL enabled and MF >4

(Min) 0.48 x ETC x DF/MF(Max) 0.52 x ETC x DF/MF(Min) 0.467 x ETC x DF/MF(Max) 0.533 x ETC x DF/MF

Internal Clock Low Period-with PLL disabled

-with PLL enabled and MF≤4-with PLL enabled and MF >4

(Min) 0.48 x ETC x DF/MF(Max) 0.52 x ETC x DF/MF(Min) 0.467 x ETC x DF/MF(Max) 0.533 x ETC x DF/MF

The DSP56002 system clock may be derived from the on-chip crystal oscillator as shown in Figure 1, or it may be externally supplied An externally supplied square wave voltage sourse should be connected to EXTAL, leaving XTAL physically unconnected (see Figure 2 ) to the board or socket The rise and fall time of this external clock should be 4 ns maximum

3rd OvertoneCrystal Oscillator

C1 = 0.1µF±20%C2 = 26 pF±20%C3 = 20 pF±10%L1 = 2.37µH±10%

XTAL = 40MHz, AT cut, 20pF load, 50Ω max series resistance

Figure 1 Crystal Oscillator Circuits

NOTE: The midpoints is VILC +0.5 (VIH –VILC).

Table 7 Clock Operation

NumCharacteristicsSymbol40 MHz 66 MHz

• with PLL enabled (42.5%-57.5% duty cycle)

235.5µs ns

2 Clock Input Low (See Note)

• with PLL disabled (46.7%-53.3% duty cycle)

• with PLL enabled (42.5%-57.5% duty cycle)

EXTAL

Table 8 Phase-Locked Loop Characteristics

VCO frequency when

MF x 340MF x 380

MF x480MF x 970

NOTE:

1. The ”E” in ETH, ETL, and ETC means external.

2 MF is the PCTL Multiplication Factor bits (MF0 - MF11).DF is the PCTL Division Factor bits (DF0 – DF3).

3 The maximum VCO frequency is limitedto the internal operation frequency.

4. CPCAP is the value of the PLL capacitor (connected between PCAP pin and VCCP ) for MF = 1 The recommended value for CPCAP is 400pF for MF≤ 4 and 540pF for MF > 4

Reset, Stop, Mode Select, and Interrupt Timing

1 Delay from RESET Assertion to Address High Impedanse (periodically sampled and not 100% tested).

2 Minimum Stabilization Duration

• Internal Oscillator PLL disabled (See Note 1)

• External Clock PLL disabled (See Note 2)

• External Clock PLL Enabled (See Note 2)

-nsnsns3 Delay from Asynchronuos RESET Deassertion

to First External Address Output (Internal Reset Deassertion)

8xTC 9xTC+20 ns4 Synchronous Reset Setup Time from RESET

5 Synchronous Reset Delay Time from the CKOUT transition #1 to the First External

8 Minimum Edge – Triggered Interrupt Request Assertion Width

-nsns11 Delay from IRQA,IRQB,NMI Assertion to

General Purpose Transfer Output Valid caused

by Fisrt Interrupt Instruction Execution 11xTC+TH - ns12 Delay from Address Output Valid Caused by

Fisrt Interrupt Inctrustion to Interrupt Request Deassertion for Level Sensitive Fast

Interrupts(See Note 3)

- 2xTC+TL+

(TCxWS) -23 ns13 Delay from RD Assertion to Interrupt Request

Deassertion for Level Sensitive Fast Interrupts(See Note 3)

(TCxWS) -21ns14 Delay from WR Assertion to Interrupt Request

Deassertion for Level Sensitive Fast Interrupts• WS = 0

• WS > 0

(See Note 3)

2xTTC+TC –21L+(TCxWS) -21

nsns15 Delay from General-Purpose Output Valid to

Interrupt Request Deassertion for Level Sensitive Fast Interrupts - If second Interrupt Instruction is:

• Single Cycle• Two Cycles

(See Note 3)

-TL –31(2xTC)+TL -31

nsns

17 Synchronous Interrupt Delay Time from the CKOUT transition #2 to the First External Address Output Valid caused by the First Instruction Fetch after coming out of Wait State

13 xTC+TH 13 xTC+TH+6

ns18 Duration for IRQA Assertion to Recover from

20 xTC

13 xTC

20 Duration of Level Sensitive IRQA Assertion to ensure interrupt service (when exiting ’Stop’)

• Internal Crystal Oscillator Clock, OMR bit 6 = 0

• Stable External Clock, OMR bit 6 =1• Stable External Clock, PCTL bit 17=1 (See Note 3)

6 xTC+TL

21 Delay from Level Sensitive IRQA Assertion to Fetch of First Interrupt Instruction (when exiting ’Stop’)

• Internal Crystal Oscillator Clock, OMR bit 6 = 0

• Stable External Clock, OMR bit 6 =1• Stable External Clock, PCTL bit 17=1 (See Note 3)

20 xTC

13 xTC

1 A clock stabilization delay is required when using the on-chip crystal oscillator in two cases:

• after power-on reset, and

• when recovering from Stop mode

During this stabilization period,TC, TH, TL will not be constant Since this stabilization period varies, a delay of 75,000 x TC is typically allowed to assure that the oscillator is stable before executing programs

2 Circuit stabilization delay is required during reset when using an external clock in two cases:

• after power-on reset, and

• when recovering from Stop mode

3. When using fast interrupt and IRQA and IRQB are defined as level – sensitive, then timings 19 through 22 apply to prevent multiple interrupt service To avoid these timing restrictions, the deassertive edge-triggered mode is recommended when using fast interrupt Long interrupts are recommended when using level-sensitive mode

Host I/O Timing

1 HEN/HACKAssertion Width (See Note 1)• CVR, ICCR, ISR, RXL Read• IVR, RXH/M Read

• Write

2 HEN/HACKDeassertion Width (See Note 1)• Between Two TXL Writes(See Note2)• Between Two CVR, ICR, ISR, RXL

Reads (See Note 3)

132 x TC + 312 x TC + 31

-nsnsns3 Host Data Input Setup Time Before

HACK/

15 DMA HACK Assertion to HREQ Deassertion (See Note 4)

-nsnsns17 Delay from HEN Deassertion to HREQ

Assertion for RXL Read (See Notes 4, 5)

TL+TC+TH - ns18 Delay from HEN Deassertion to HREQ

Assertion for RXL Write (See Notes 4, 5)

19 Delay from HEN Assertion to HREQ Deassertion for RXL Read , TXL Write (See Notes 4, 5)

1. See Host Port Considerations in the section on Design Considerations.

2. This timing must be adhered to only if two consecutive writes to the TXL are executed without polling TXDE or HREQ

3. This timing must be adhered to only if two consecutive reads from one of these registers are executed without polling the corresponding status bits or HREQ

4. HREQ is pulled up by a 1KΩ resistor.

5 Specifications are periodically sampled and not 100% tested.6 May decrease to 0 ns for future versions.

Serial Communication Interface(SCI) Timing

ns9 Clock Falling Edge to Output Data Valid

12 Input Data Hold Time After Clock Rising

Table 12 SCI Asynchronous Mode Timing – 1X Clock

Unit

-5 Output Data Setup to Clock Rising Edge tACC/2 – 51 - ns

Synchronous Serial Interface (SSI) Timing

VCC = 5.0 Vdc±10%, TJ = -40oC to +105oC, CL = 50pF + 2 TTL Loads tSSIC = SSI clock cycle time

TXC(SCK pin) = Transmit ClockRXC(SC0 or SCK pin) = Receive clock

FTS(SC2 pin) = Transmit Frame SyncFSR(SC1 or SC2 pin) = Receive Frame Sync

i ck = Internal Clockx ck = External Clockg ck = Gated clock

i ck a = Internal Clock, Asynchronous Mode (Asynchronous implies that STD and SRD are two differrent clocks)

i ck s = Internal Clock, Synchronous Mode (Synchronous implies that STD and SRD are two same clocks)

bl = bit lengthwl = word length

Table 13 SSI Timing

-i ckx ck

x cki ck a

ns7 RXC Rising Edge to FSR Out(wl)

x cki ck a

ns8 RXC Rising Edge to FSR Out(wl)

9 Data In Setup Time Before RXC (SCK in Synchronous Mode)Falling Eddge

-x cki ck ai ck s

10 Data In Hold Time After RXC Falling Eddge

-x cki ck

ns11 FSR Input (bl) High Before RXC

12 FSR Input (wl) High Before RXC

-x cki ck s

ns15 Flags Input Hold Time After RXC

Falling Edge

-x cki ck s

ns16 TXC Rising Edge to FST Out(bl)

x cki ck

ns20 TXC Rising Edge to Data Out Enable

from High Impedance

x cki ck

ns21 TXC Rising Edge to Data Out Valid -

- 33.3+T22.4 H x cki ck ns22 TXC Rising Edge to Data Out High

Impedance (See Note 2) -- 35.820.8 x cki ck ns23 TXC Falling Edge to Data Out High

C+TH g ck ns24 FST input (bl) Setup Time Before

TXC Falling Edge

-x cki ck

ns25 FST input (wl) to Data Out Enable

from High Impendance