Thiết kế và lập trình hệ thống - Chương
Systems Design & Programming Memory III CMPE 3101 (Mar. 6, 2002)UMBCU M B CUNIVERSITY OF MARYLAND BALTIMORE COUNTY1 9 6 68086 - 80386SX 16-bit Memory InterfaceThese machines differ from the 8088/80188 in several ways:• The data bus is 16-bits wide.• The IO/M pin is replaced with M/IO (8086/80186) and MRDC and MWTCfor 80286 and 80386SX.•BHE, Bus High Enable, control signal is added.• Address pin A0 (or BLE, Bus Low Enable) is used differently.The 16-bit data bus presents a new problem:The microprocessor must be able to read and write data to any 16-bitlocation in addition to any 8-bit location.The data bus and memory are divided into banks:FFFFFFFFFFFD0000030000018 MB8 bitsD15-D8FFFFFEFFFFFC0000020000008 MB8 bitsD7-D0High bankLow bankOdd bytesEven bytesBHE selects BLE selects Systems Design & Programming Memory III CMPE 3102 (Mar. 6, 2002)UMBCU M B CUNIVERSITY OF MARYLAND BALTIMORE COUNTY1 9 6 68086 - 80386SX 16-bit Memory InterfaceBHE and BLE are used to select one or both:Bank selection can be accomplished in two ways: Separate write decoders for each bank (which drive CS). A separate write signal (strobe) to each bank (which drive WE).Note that 8-bit read requests in this scheme are handled by the micropro-cessor (it selects the bits it wants to read from the 16-bits on the bus).There does not seem to be a big difference between these methods althoughthe book claims that there is.Note in either method that A0 does not connect to memory and bus wire A1connects to memory pin A0, A2 to A1, etc.BHE BLE Function0 0 Both banks enabled for 16-bit transfer0 1 High bank enabled for an 8-bit transfer1 0 Low bank enabled for an 8-bit transfer1 1 No banks selected Systems Design & Programming Memory III CMPE 3103 (Mar. 6, 2002)UMBCU M B CUNIVERSITY OF MARYLAND BALTIMORE COUNTY1 9 6 680386SX 16-bit Memory Interface (Separate Decoders)A0A15O0O7 CSA20CSCSCSCSCSCSCSM/IOCSCSCSCSCSCSCSA0A15O0O7 CSBHEA17BLEG2AG2BG1ABC0123456774LS138G2AG2BG1ABC01234567(64K X 8)62512374LS138A18A19A21A22A23Data BusD0 to D7D8 to D1580386SXSeparate Decoders(64K X 8)62512WEOEMWTCOEWEAddress BusA1 to A16G2AG2BG1ABC0123456774LS138MRDC Systems Design & Programming Memory III CMPE 3104 (Mar. 6, 2002)UMBCU M B CUNIVERSITY OF MARYLAND BALTIMORE COUNTY1 9 6 6Memory InterfacesSee text for Separate Write Strobe scheme plus some examples of the integra-tion of EPROM and SRAM in a complete system.It is just an application of what we’ve been covering.80386DX and 80486 have 32-bit data buses and therefore 4 banks of memory.32-bit, 16-bit and 8-bit transfers are accomplished by different combina-tions of the bank selection signalsBE3, BE2, BE1, BE0.The Address bits A0and A1are used within the microprocessor to gener-ate these signals.They are don’t cares in the decoding of the 32-bit address outside thechip (using a PLD such as the PAL 16L8).The high clock rates of these processors usually require wait states formemory access.We will come back to this later. Systems Design & Programming Memory III CMPE 3105 (Mar. 6, 2002)UMBCU M B CUNIVERSITY OF MARYLAND BALTIMORE COUNTY1 9 6 6Pentium Memory InterfaceThe Pentium, Pentium Pro, Pentium II and III contain a 64-bit data bus.Therefore, 8 decoders or 8 write strobes are needed as well as 8 memorybanks.The write strobes are obtained by combining the bank enable signals(BEx) with the MWTC signal.MWTC is generated by combining the M/IO and W/R signals.BE7BE6BE5BE4MWTCBE3BE2BE1BE0WR7WR6WR5WR4WR3WR2WR1WR0W/RM/IO Systems Design & Programming Memory III CMPE 3106 (Mar. 6, 2002)UMBCU M B CUNIVERSITY OF MARYLAND BALTIMORE COUNTY1 9 6 6Pentium Memory InterfaceI1I2I3I4I5I6I7I8I9I1016L8O1O2O3O4O5O6O7O8A29A30A31I1I2I3I4I5I6I7I8I9I1016L8O1O2O3O4O5O6O7O8A19A20A21A22A23A24A25A26A27A28A0A15O0O7 CEOE27512D0-D7D8-D15D15-D23D24-D31D56-D63D48-D55D40-D47D32-D39A3-A18MRDCA0A15O0O7 CEOE27512A0A15O0O7 CEOE27512A0A15O0O7 CEOE27512A0A15O0O7 CEOE27512A0A15O0O7 CEOE27512A0A15O0O7 CEOE27512A0A15O0O7 CEOE27512(64K X 8)WE WE WE WEWEWEWEWEWR0WR1WR2WR3WR7WR6WR5WR4 Systems Design & Programming Memory III CMPE 3107 (Mar. 6, 2002)UMBCU M B CUNIVERSITY OF MARYLAND BALTIMORE COUNTY1 9 6 6Pentium Memory InterfaceIn order to map previous memory into addr. space FFF80000H-FFFFFFFFHUse a 16L8 to do theWR0 - WR7 decoding using MWTC and BE0 - BE7.See the text -- Figure 10-35.;pins 1 2 3 4 5 6 7 8 9 10A29 A30 A31 NC NC NC NC NC NC GND;pins 11 12 13 14 15 16 17 18 19 20U2 CE NC NC NC NC NC NC NC VCCEquations:/CE = /U2 * A29 * A30 * A31I1I2I3I4I5I6I7I8I9I1016L8O1O2O3O4O5O6O7O8A29A30A31I1I2I3I4I5I6I7I8I9I1016L8O1O2O3O4O5O6O7O8A19A20A21A22A23A24A25A26A27A28;pins 1 2 3 4 5 6 7 8 9 10A19 A20 A21 A22 A23 A24 A25 A26 A27 GND;pins 11 12 13 14 15 16 17 18 19 20A28 U2 NC NC NC NC NC NC NC VCCEquations:/U2 = A19 * A20 * A21 * A22 * A23 * A24 * A25 *A26 * A27 * A28 Systems Design & Programming Memory III CMPE 3108 (Mar. 6, 2002)UMBCU M B CUNIVERSITY OF MARYLAND BALTIMORE COUNTY1 9 6 6Memory ArchitectureIn order to build an N-word memory where each word is M bits wide (typi-cally 1, 4 or 8 bits), a straightforward approach is to stack memory:This approach is not practical.What can we do?S0S1S2SN-2SN-1N wordsWord 0Word 1Word 2Storage cellWord N-2Word N-1Input-Output(M bits)A word is selected by setting exactlyone of the select bits, Sx, high.This approach works well for smallmemories but has problems for largeFor example, to build a 1Mwordmemories.(where word = 8 bits) memory, requires1M select lines, provided by someoff-chip device. Systems Design & Programming Memory III CMPE 3109 (Mar. 6, 2002)UMBCU M B CUNIVERSITY OF MARYLAND BALTIMORE COUNTY1 9 6 6Memory ArchitectureAdd a decoder to solve the package problem:This does not address the memory aspect ratio problem:The memory is 128,000 time higher than wide (220/23) !Besides the bizarre shape factor, the design is extremely slow since the ver-tical wires are VERY long (delay is at least linear to length).S0S1S2SN-2SN-1Word 0Word 1Word 2Storage cellWord N-2Word N-1Input-Output(M bits)DecoderA0A1A2AK-1K = log2None-hotBinary encoded addressThis reduces thenumber of externaladdress pins from1M to 20. Systems Design & Programming Memory III CMPE 31010 (Mar. 6, 2002)UMBCU M B CUNIVERSITY OF MARYLAND BALTIMORE COUNTY1 9 6 6Memory ArchitectureThe vertical and horizontal dimensions are usually very similar, for an aspectratio of unity.Multiple words are stored in each row and selected simultaneously:S0S1S2SN-2SN-1Storage cellInput-Output(M bits)AKAK+1AK+2AL-1Column address =A0AK-1Bit lineWord lineA0 to AK-1Row address =AK to AL-1A column decoder is added toselect the desired word from a row.Column decoderRow DecoderSense ampsand driversnot shown [...]... Design & Programming MO UN TI RE COUNT Y M YLAND BA L 196 6 U M B C AR CAS A0 A1 A2 A3 A4 A5 A6 A7 A8 RAS WE Row Latches Memory III 256-to-1 MUX 256-to-1 MUX 256-to-1 MUX Dir S1 S0 13 (Mar 6, 2002) DIN DOUT 256-to-1 MUX 64K array (256 X 256) Block 0 CMPE 310 These signals provide the block address A9(A0 from input pin on RAS) A8 A0-A7 8 256K X 1 DRAM A10-A17 Block 3 Block 2 Block 1 255 254 64K array 64K... depending on the address This drives a 16-bit word onto the High and Low data buses (if WE is low) or writes an 8 or 16 bit word into the memory otherwise the memories (AL) and 9 Address High (AH) bits of the 82C08 9 of each of these are strobed onto the address wires A0 through A8 to DRAM Controllers: Intel 82C08: Microprocessor bits A1 through A18 (18 bits) drive the 9 Address Low Systems Design & Programming... Y High Data Bus M YLAND BA L 196 6 U M B C AR I1 I2 I3 I4 I5 I6 I7 I8 I9 I10 O1 O2 O3 O4 O5 O6 O7 O8 UMBC WE A0 A20 A21 A22 A23 M/IO IVERSITY O F 16L8 Memory III CMPE 310 18 (Mar 6, 2002) Equations: /LWR = /A0 * /WE /HWR = /BHE * /WE /PE = /A20 * /A21 * /A22 * /A23 * MIO ;pins 1 2 3 4 5 6 7 8 9 10 PE WE BHE A0 A20 A21 A22 A23 NC NC GND HWR ;pins 11 12 13 14 15 16 17 18 19 20 LWR MIO CE NC NC NC NC LWR... III CMPE 310 M YLAND BA L 196 6 U M B C AR UMBC 12 (Mar 6, 2002) For a 256K X 1 DRAM with 256 rows, a refresh must occur every 15.6us (4ms/256) For the 8086, a read or write occurs every 800ns This allows 19 memory reads/writes per refresh or 5% of the time The capacitors are recharged for the selected row by reading the bits out internally and then writing them back A RAS-only cycle strobes a row address... & Programming MO UN TI RE COUNT Y AL8 AH0 AL0 A8 A0 M YLAND BA L TI MO 196 6 U M B C AR UMBC M/IO BHE A0 A20 A21 A22 A23 O1 O2 O3 O4 O5 O6 O7 O8 16L8 WAIT R2 R1 17 A0 O0 A8 O7 Memory III A0 O0 A8 O7 WE RAS CAS WE RAS CAS IVERSITY O F I1 I2 I3 I4 I5 I6 I7 I8 I9 I10 AH8 S0 RD RAS0 WR S1 CAS0 RESET RAS1 CLK PCTL CAS1 PE AA/XA A 19 BS WE RFRQ PD1 A18 A1 82C08 DRAM Controllers UN (Mar 6, 2002) WE RAS... read and three for the next three 64-bit words, for a total of 7 bus cycles EDO and SDRAM Memory Synchronous Dynamic RAM: However, this improves performance again, particularly for reads into cache block sizes of 256 bits Systems Design & Programming MO UN TI RE COUNT Y IVERSITY O F Memory III CMPE 310 M YLAND BA L 196 6 U M B C AR UMBC 16 map onto 1 MByte range (000000H-0FFFFFH) (Mar 6, 2002) Address bit...Memory III CMPE 310 IVERSITY O F M YLAND BA L 196 6 U M B C AR UMBC Address: [Row][Block][Col] Global Data bus Block Address Column Address Row Address Block 0 11 Global amplifier/driver I/O Block selector Block i (Mar 6, 2002) Block P-1 Memory Architecture This strategy works well for memories up to 64 Kbits to 256 Kbits Larger memories start... Decoder UMBC Column Latches Dynamic RAM IVERSITY O F MUX Systems Design & Programming MO UN TI RE COUNT Y IVERSITY O F Memory III CMPE 310 M YLAND BA L 196 6 U M B C AR UMBC 14 (Mar 6, 2002) However, these access times only apply to the 2nd, 3rd and 4th 64-bit reads the first takes the same time as a standard DRAM Synchronous Dynamic RAM: Access times are 10ns (for use with 66MHz bus) and 8ns (for use... refresh or 5% of the time The capacitors are recharged for the selected row by reading the bits out internally and then writing them back A RAS-only cycle strobes a row address into the DRAM, obtained by 7- or 8bit binary counter This special refresh occurs transparently while other memory components operate and is called transparent refresh or cycle stealing Dynamic RAM DRAM requires refreshing every 2... memory: Any memory access in an EDO memory (including a refresh) stores the 256 bits in a set of latches Systems Design & Programming MO UN TI RE COUNT Y IVERSITY O F Memory III CMPE 310 M YLAND BA L 196 6 U M B C AR UMBC 15 (Mar 6, 2002) These devices tend to get very complex We will focus on a simpler device, the Intel 82C08, which can control two banks of 256K X 16 DRAM memories for a total of 1 MB . InterfaceI1I2I3I4I5I6I7I8I9I1016L8O1O2O3O4O5O6O7O8A29A30A31I1I2I3I4I5I6I7I8I9I1016L8O1O2O3O4O5O6O7O8A19A20A21A22A23A24A25A26A27A28A0A15O0O7......CEOE27512D0-D7D8-D15D15-D23D24-D31D56-D63D48-D55D40-D47D32-D39A3-A18MRDCA0A15O0O7......CEOE27512A0A15O0O7......CEOE27512A0A15O0O7......CEOE27512A0A15O0O7......CEOE27512A0A15O0O7......CEOE27512A0A15O0O7......CEOE27512A0A15O0O7......CEOE27512(64K. simultaneously:S0S1S2SN-2SN-1Storage cellInput-Output(M bits)AKAK+1AK+2AL-1Column address =A0AK-1Bit lineWord lineA0 to AK-1Row address =AK to AL-1A column decoder