Thiết kế và lập trình hệ thống - Chương
Systems Design & Programming 8086/88 Chip Set CMPE 3101 (Feb. 20, 2002)UMBCU M B CUNIVERSITY OF MARYLAND BALTIMORE COUNTY1 9 6 68086/88 Device SpecificationsBoth are packaged in DIP (Dual In-Line Packages).• 8086: 16-bit microprocessor with a 16-bit data bus• 8088: 16-bit microprocessor with an 8-bit data bus.Both are 5V parts:• 8086: Draws a maximum supply current of 360mA.• 8086: Draws a maximum supply current of 340mA.• 80C86/80C88: CMOS version draws 10mA with temp spec -40 to 225degF.Input/Output current levels:Yields a 350mV noise immunity for logic 0 (Output max can be as high as450mV while input max can be no higher than 800mV).This limits the loading on the outputs.Logic levelVoltage Current00.8V max+/- 10uA max12.0V min+/- 10uA maxLogic levelVoltage Current00.45V max+2mA max12.4V min- 400uA maxINPUTOUTPUT Systems Design & Programming 8086/88 Chip Set CMPE 3102 (Feb. 20, 2002)UMBCU M B CUNIVERSITY OF MARYLAND BALTIMORE COUNTY1 9 6 68086/88 PinoutGNDCLKINTRNMIAD0AD1AD2AD3AD4AD5AD6AD7AD8AD9AD10AD11AD12AD13AD14GNDRESETREADYTEST(QS1)(QS0)(S0)(S1)(S2)(LOCK)(RQ/GT1)(RQ/GT0)RDMN/MXBHE/S7A19/S6A18/S5A17/S4A16/S3AD15VCCWRHLDAHoldM/IODT/RDENALEINTAMIN MODE (MAX MODE)123456789101112131415161718192040393837363534333231302928272625242322218086 CPU Systems Design & Programming 8086/88 Chip Set CMPE 3103 (Feb. 20, 2002)UMBCU M B CUNIVERSITY OF MARYLAND BALTIMORE COUNTY1 9 6 68086/88 PinoutPin functions: AD15-AD0Multiplexed address(ALE=1)/data bus(ALE=0). A19/S6-A16/S3 (multiplexed)High order 4 bits of the 20-bit address OR status bits S6-S3. M/IOIndicates if address is a Memory or IO address.RDWhen 0, data bus is driven by memory or an I/O device.WRMicroprocessor is driving data bus to memory or an I/O device. When 0,data bus contains valid data. ALE (Address latch enable)When 1, address data bus contains a memory or I/O address. DT/R (Data Transmit/Receive)Data bus is transmitting/receiving data. DEN (Data bus Enable)Activates external data bus buffers. Systems Design & Programming 8086/88 Chip Set CMPE 3104 (Feb. 20, 2002)UMBCU M B CUNIVERSITY OF MARYLAND BALTIMORE COUNTY1 9 6 68086/88 PinoutPin functions: S7, S6, S5, S4, S3, S2, S1, S0S7: Logic 1, S6: Logic 0.S5: Indicates condition of IF flag bits.S4-S3: Indicate which segment is accessed during current bus cycle:S2, S1, S0: Indicate function of current bus cycle (decoded by 8288).S4S3 Function00Extra segment01Stack segment1011Code or no segmentData segmentS2S1 Function00Interrupt Ack01I/O Read1011I/O WriteHaltS00000S2S1 Function00Opcode Fetch01Memory Read1011Memory WritePassiveS01111 Systems Design & Programming 8086/88 Chip Set CMPE 3105 (Feb. 20, 2002)UMBCU M B CUNIVERSITY OF MARYLAND BALTIMORE COUNTY1 9 6 68086/88 PinoutPin functions: INTRWhen 1 and IF=1, microprocessor prepares to service interrupt.INTAbecomes active after current instruction completes.INTAInterrupt Acknowledge generated by the microprocessor in response toINTR. Causes the interrupt vector to be put onto the data bus. NMINon-maskable interrupt. Similar to INTR except IF flag bit is not con-sulted and interrupt is vector 2. CLKClock input must have a duty cycle of 33% (high for 1/3 and low for 2/3s) VCC/GNDPower supply (5V) and GND (0V). Systems Design & Programming 8086/88 Chip Set CMPE 3106 (Feb. 20, 2002)UMBCU M B CUNIVERSITY OF MARYLAND BALTIMORE COUNTY1 9 6 68086/88 PinoutPin functions: MN/MXSelect minimum (5V) or maximum mode (0V) of operation.BHEBus High Enable. Enables the most significant data bus bits (D15-D8)during a read or write operation. READYUsed to insert wait states (controlled by memory and IO for reads/writes) into the microprocessor. RESETMicroprocessor resets if this pin is held high for 4 clock periods.Instruction execution begins at FFFF0H and IF flag is cleared.TESTAn input that is tested by the WAIT instruction.Commonly connected to the 8087 coprocessor. Systems Design & Programming 8086/88 Chip Set CMPE 3107 (Feb. 20, 2002)UMBCU M B CUNIVERSITY OF MARYLAND BALTIMORE COUNTY1 9 6 68086/88 PinoutPin functions: HOLDRequests a direct memory access (DMA). When 1, microprocessor stopsand places address, data and control bus in high-impedance state. HLDA (Hold Acknowledge)Indicates that the microprocessor has entered the hold state.RO/GT1 and RO/GT0Request/grant pins request/grant direct memory accesses (DMA) dur-ing maximum mode operation.LOCKLock output is used to lock peripherals off the system. Activated byusing the LOCK: prefix on any instruction. QS1 and QS0The queue status bits show status of internal instruction queue. Pro-vided for access by the numeric coprocessor (8087). Systems Design & Programming 8086/88 Chip Set CMPE 3108 (Feb. 20, 2002)UMBCU M B CUNIVERSITY OF MARYLAND BALTIMORE COUNTY1 9 6 68284A Clock GeneratorBasic functions: Clock generation. RESET synchronization. READY synchronization. Peripheral clock signal.Connection of the 8284 and the 8086.1234567891817161514131211108284ACLKCSYNCRESETF/CX2X1 CrystalOSC15MHz8086CLKRESET Systems Design & Programming 8086/88 Chip Set CMPE 3109 (Feb. 20, 2002)UMBCU M B CUNIVERSITY OF MARYLAND BALTIMORE COUNTY1 9 6 68284A Clock GeneratorGNDCLKAEN2RDY2READYRDY1AEN1PCLKCSYNCRESETRESOSCF/CEFIASYNCX2X1VCC1234567891817161514131211108284AD QRESETRESOSCXTALOSCX1X2+2PCLKF/CEFI+3CSYNCCLKD QREADYD QRDY1AEN1AEN2RDY2ASYNCSchmitttrigger(EFI inputto other8284As)div-by-3cnterdiv-by-2cnter2-to-1 mux Systems Design & Programming 8086/88 Chip Set CMPE 31010 (Feb. 20, 2002)UMBCU M B CUNIVERSITY OF MARYLAND BALTIMORE COUNTY1 9 6 68284A Clock GeneratorClock generation:Crystal is connected to X1 and X2.XTAL OSC generates square wave signal at crystal’s frequency whichfeeds: An inverting buffer (output OSC) which is used to drive the EFI inputof other 8284As. 2-to-1 MUXF/C selects XTAL or EFI external input.The MUX drives a divide-by-3 counter (15MHz to 5MHz).This drives: The READY flipflop (READY synchronization). A second divide-by-2 counter (2.5MHz clk for peripheral components). The RESET flipflop.CLK which drives the 8086 CLK input. [...]... access cycle Systems Design & Programming MO UN TI RE COUNT Y IVERSITY O F M YLAND BA L 1966 U M B C AR AD15-AD0 Tw Data Setup Data In S7-S3 T3 16 Bus Timing for a Read Operation Float T2 800ns 8086/88 Chip Set A19-A16 T1 200ns Address setup UMBC RD DEN READY DT/R ALE M/IO AD15-AD0 A19-A16/S6-S3 CLK BUS Timing Bus Timing: Systems Design & Programming MO UN TI RE COUNT Y Float (Feb 20, 2002) T4 CMPE... UN TI RE COUNT Y IVERSITY O F 8086/88 Chip Set M YLAND BA L 1966 U M B C AR CMPE 310 UMBC 12 BHE: Selects the high-order memory bank Data bus buffers must be bi-directional buffers (BB) Control and A16-A19 + BHE are buffered separately All signals MUST be buffered Latches buffer for A0-A15 (Feb 20, 2002) The Address and Data bus are multiplexed (shared) due to pin limitations on the 8086 The ALE pin... YLAND BA L 1966 U M B C AR Data In Data In Float UMBC 19 (Feb 20, 2002) Sampled again Wait State timing Text discusses role of 8284A and timing requirements for the 8086 Fail Float READY AD15-AD0 OK IVERSITY O F AD15-AD0 READY CLK lengthen the bus cycle For example, this extends a 460ns bus cycle (at 5MHz clock) to 660ns 800ns 200ns Tw T3 T2 T1 T4 BUS Timing READY: An input to the 8086 that causes wait... AEN CEN IOB Control Input S0 S1 S2 8288 Bus Controller 8086 Status Systems Design & Programming MO UN TI RE COUNT Y IVERSITY O F M YLAND BA L 1966 U M B C AR GND S0 S1 S2 UMBC INT AD0-AD15 8086 CPU CLK READY RESET IRQ 0-7 8284A RES MAX Mode 8086 System VCC Systems Design & Programming MO UN TI RE COUNT Y 22 T OE 8286 Transceiver Latches STB S0 CLK MRDC S1 MWTC S2 8288 DEN IORC DT/R IOWC ALE INTA 8086/88... reset timing requires that the RESET input to the microprocessor becomes a logic 1 NO LATER than 4 clocks after power up and stay high for at least 50us RESET 8284A Clock Generator RESET: Negative edge-triggered flipflop applies the RESET signal to the 8086 on the falling edge The 8086 samples the RESET pin on the rising edge CSYNC: Used with multiple processors 18 X1 CSYNC 1 Crystal 17 2 OSC 16 3 15MHz . QRDY1AEN1AEN2RDY2ASYNCSchmitttrigger(EFI inputto other8284As)div-by-3cnterdiv-by-2cnter2-to-1 mux Systems Design & Programming 8086/88 Chip Set CMPE. Timing:T1T2T3T4RDM/IOCLKBus Timing for a Read OperationA19-A16/S6-S3A19-A16S7-S3AD15-AD0FloatData InFloatTwAD15-AD0ALEDT/RDENREADY800ns200nsDataSetupAddress setup Systems