Thiết kế và lập trình hệ thống - Chương6

... QRESETRESOSCXTALOSCX1X2+2PCLKF/CEFI+3CSYNCCLKD QREADYD QRDY1AEN1AEN2RDY2ASYNCSchmitttrigger(EFI inputto other8284As)div-by-3cnterdiv-by-2cnter2-to-1 mux Systems Design & Programming 8086/88 Chip Set CMPE 31010 (Feb. 20, 2002)UMBCU ... 8284As. 2-to-1 MUXF/C selects XTAL or EFI external input.The MUX drives a divide-by-3 counter (15MHz to 5MHz).This drives: The READY flipflop (READY synchroni...

Ngày tải lên: 15/11/2012, 11:07

... Program AreaRead-Only Memory 0-3 4-7 8-B1 0-1 3C-F1 4-1 71 8-1 B1D-1F2 0-2 32 4-2 72 8-2 B2C-2F3 0-3 33 4-3 73 8-3 B3C-3F4 0-4 34 4-4 74 8-4 B4C-4F5 0-5 35 4-5 75 8-5 B5C-5F6 0-6 36 4-6 76 8-6 B6C-6F7 0-7 37 4-7 77 8-7 B7C-7FDivide by zeroSingle ... architecture:20-bits (8086/8088)24-bits (80286/80386SX)25-bits (80386SL/SLC/EX)32-bits (80386DX/804...

Ngày tải lên: 15/11/2012, 11:07

... IndexEIPEFLAGSIPFLAGSInstruction PointerFlagsCodeDataExtraStackCSDSESSSFSGS80386-Pentium III only16-bitregisters32-bitextensionsAH ALAX8-bit16-bitnames Systems Design and Programming Micro. Arch. I CMPE 3103 ... DS:ECX, DS:EDX, DS:EDI, DS:ESI, DS:8-bit_literal,DS:32-bit_literal• ES:EDI• FS and GS have no default.It is illegal to place an offset larger than FFFF into the 80386 32-bit registers...

Ngày tải lên: 15/11/2012, 11:07

... D=0, instructions are 16-bit instructions, with 16-bit offsets and 16-bitregisters. Stacks are assumed 16-bit wide and SP is used.• When D=1, 32-bits are assumed.Allows 808 6-8 0286 programs to run.• ... selector.Bit 0-1 5, 1 6-1 9: Although the limit is still 20 bits (and the G bit is also valid),segments larger than 64KB don’t make sense!Limit015391640Base(1 5-0 )(2 3-0 )P00000104...

Ngày tải lên: 15/11/2012, 11:07

... the 80386 and up.Allows a linear address (virtual address) of a program to be located in any por-tion of physical memory.The paging unit is controlled by the microprocessors control registers:311211 ... appropriate page table and (finally) one tothe desired data or code item. Ouch!A Translation Look-aside Buffer (TLB) is used to cache page directoryand page table entries to reduce the number o...

Ngày tải lên: 15/11/2012, 11:07

... privilege lev-els.They define entry points in more privileged code to which control can be trans-ferred.Destination Offset015391640Destination Selector(1 5-0 )P000110047Destination Offset(3 1-1 6)63360003132WC Systems ... about a task in the TSS.More on this later as time permits.Limit015391640Base(1 5-0 )(2 3-0 )P00010014748(1 9-5 556Base(3 1-2 4)16)515263G000Lim ... general, the...

Ngày tải lên: 15/11/2012, 11:07

... 64-bit wide data bus.The 30-pin and 72-pin SIMMs are not used on these systems.Rather, 64-bit DIMMs (Dual In-line Memory Modules) are the standard.These organize the memory 64-bits wide.The board has ... 4B1A 1B 2A 2B 3A 3B 4A 4BRASA074157 (2-to-1MUX)A1A2A3A4A5A6A71Y 2Y 3Y 4Y 1Y 2Y 3Y 4YAddress BUSInputs to DRAM0: latch A to Y1: latch B to YSS74157 (2-to-1MUX) Systems Design & Programming...

Ngày tải lên: 15/11/2012, 11:07

... )X16G X( )-- -- - -- - -- - -- - -- - -- - -- - -X27X26X25X24X22X21X18+ + + + + +X16X15X21+ + +-- -- - -- - -- - -- - -- - -- - -- - -- - -- - -- - -- - -- - -- - -- - -- - -- - -- - -- - -- - -- - -- - -- - -- - -- - -- - -- - -- - -- - -- - -- - -- - -- - -- - -- - -- - =X16X15X21+ ... 15.Therefore, no more than 2 bytes are needed independent of the data block size.CRCM X( )XnG X( )--...

Ngày tải lên: 15/11/2012, 11:07

... pin on RAS)A8S1S0MUX256-to-1MUX256-to-1MUX256-to-1MUX256-to-164K array(256 X 256)2552541064K array(256 X 256)64K array(256 X 256)64K array(256 X 256)256K X 1 DRAMA0-A7A10-A17Block 0Block 1Block ... InterfaceI1I2I3I4I5I6I7I8I9I1016L8O1O2O3O4O5O6O7O8A29A30A31I1I2I3I4I5I6I7I8I9I1016L8O1O2O3O4O5O6O7O8A19A20A21A22A23A24A25A26A27A28A0A15O0O7......CEOE27512D0-D7D8-D15D15-D23D24-D31D56-D63D48-D55D40-...

Ngày tải lên: 15/11/2012, 11:07

... Function 0 0 1 10101I/O Port AssignmentsPort A (PA7-PA0) and upperhalf of port C (PC7 - PC4)Group APort B (PB7-PB0) and lowerhalf of port C (PC3 - PC0)Group BPort APort BPort CCommand RegisterPA1PA2PA3PA4PA5PA6PA7PA0PB1PB2PB3PB4PB5PB6PB7PB0PC1PC2PC3PC4PC5PC6PC7PC0 Systems ... addresses)D 7-- D08 Systems Design and Programming Basic I/O II CMPE 3104 (Apr. 10, 2002)UMBCU M B CUNIVERSI...

Ngày tải lên: 15/11/2012, 11:07