Acer aspire 5020 WISTRON BOLSENA

5 See 'TEXT' in 0MEMO or 1MEMO property in component Dummy when 'USE EZ4' Bolsena Block Diagram Dummy when 'NO EZ4' 91.4C501.001 (04243) Dummy when use '10/100' Dummy when use 'GIGA' D 200-PIN DDR SODIMM CLK GEN IDT CV1373 Dummy when use 'UMA' AMD CPU Dummy when use 'DIS' Dummy when use 'IDE' 28 AGTL+ CPU I/F + UMA PCI Express x16 11,12,13,14 1* Slot Cardbus 1* 1394 CardReader ATI M26/M24 RGB CRT 50,51,52 PCI-Express x2 28 26,27 PCI ACPI 2.0 B 1000Mb 30 6xUSB 2.0 TXFM 10/100Mb 30 16 24 USB x 24 CODEC ALC655 MODEM MDC Card RJ11 CONN 30 24 Line In 33 MIC In 32 6-CH AC97 2.2 PCI LAN Realtek RTL8110SBL 1000/100/10 RTL8100C 100/10 29 CRT BlueTooth miniUSB AC97 TXFM Power Block Diag -> Page 40 DVI-D (EZ4 only ) 15 SB400 31 30 17 C TMDS VRAM x4 ATI RJ45 LCD CH7301C 15 (M26/M24 diff.) 53,54 PCI Bus / 33MHz Mini-PCI 802.11a/b/g TVOUT 16 RS480M TI PCI 7411 SM/MMC/SD in LVDS ATI PWR SW TSP2220A 1394 4pin Conn 28 SVIDEO/COMP HyperTransport 6.4GB/S 16b/8b Dummy when use ''M24' C D 4,5,6,7 Dummy when use ''M26' PCMCIA SLOT PCMCIA I/F Support TypeII 28 MS/xD DDR x2 8,9,10 17 LEDs RTC BAT 18 BUTTONs 35 Dummy when use 'SATA' DDR 333/400 35W/25W OP AMP G1421 Line Out33 33 Int SPKR33 B LPC Bus / 33MHz LPC I/F HDD DVD/ CD-RW 25 25 Thermal & Fan G792 23 NS SIO PC87392 SIDE SATA 18,19,20,21,22 PIDE ATA 133 37 25 FIR 34 Touch Pad 37 XBUS KBC KB3910 35 Int KB ISA ROM 35 36 A A Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Port Replicator (124 PIN) AC RJ45-11 IN SEARIAL PORT CRT PS2 MIC LINE IN LINE TV OUT OUT PRINTER DVI Title PCIeX2 SMBUS BLOCK DIAGRAM Size A3 Document Number Rev -1 Bolsena Date: Tuesday, April 12, 2005 Sheet 1 of 58 PCI Routing IDSEL MiniPCI 21 LAN 7411 IRQ REQ/GNT F 23 H 22 E (CardBus) 7411 22 G (1394) 7411 22 E (FlashMedia) D D C C B A B Ref function schematic BOM U81 cpu socket 62.10055.091 (DON'T CHANGE) (3mm high) U80 north bridge 71.RS48M.00U 71.RS48M.B0U (ver A22) U43 south bridge 71.SB400.B0U 71.SB400.D0U (ver A32) U32 clock gen 71.00137.A0W 71.00137.B0W U70 VGA M24 71.0M26P.00U 71.00M24.C0U U64 VRAM FOR M24 72.55732.B0U 72.52832.E05 U65 VRAM FOR M24 72.55732.B0U 72.52832.E05 U69 VRAM FOR M24 72.55732.B0U 72.52832.E05 U71 VRAM FOR M24 72.55732.B0U 72.52832.E05 U70 VGA M26 71.0M26P.00U (DON'T CHANGE) U64 VRAM FOR M26 72.55732.B0U (DON'T CHANGE) U65 VRAM FOR M26 72.55732.B0U (DON'T CHANGE) U69 VRAM FOR M26 72.55732.B0U (DON'T CHANGE) U71 VRAM FOR M26 72.55732.B0U (DON'T CHANGE) U66 BIOS SOCKET 72.39040.G03 62.10002.032 (NO NEED WHEN PD) U66 BIOS IC 72.39040.G03 72.39040.H03 (DIP STAGE IN LAB, SMT IN PD) LOUT1 AUDIO 22.10257.001 22.10147.031 (NO SPDIF) U75 GIGA LAN 71.08110.00G 71.08110.A0G U75 10/100 LAN 71.08110.00G 71.08100.C0G HDD1 20.80175.044 20.80592.044 SATA1 20.F0614.022 20.F0665.022 EZ4 20.80579.120 20.80591.120 (AFTER SB) Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title CHANGE HISTORY Size A3 Document Number Bolsena Date: Thursday, March 31, 2005 A Rev -1 Sheet of 58 A B C D E 3D3V_S0 C415 SC10U10V5ZY C398 SCD1U16V L12 0R0603-PAD C418 SCD1U16V SC 0308 C414 SC10U10V5ZY 3D3V_CLK_VDDA 1 C397 SCD1U16V C423 SCD1U16V 2 C421 SCD1U16V SC 0308 3D3V_CLK_VDD L14 0R0603-PAD 3D3V_S0 RN56 C420 SCD1U16V C417 SCD1U16V 2 C416 SCD1U16V C419 3D3V_S0 SCD1U16V 3D3V_CLK_VDD U32 3D3VDD48_S0 L13 0R0603-PAD SC 0308 XI_CLK C400 SC33P50V2JN 57 SMBC_SB_EZ4 57 SMBD_SB_EZ4 R278 DUMMY-R3 XO_CLK C422 SC33P50V2JN 1 26 CLK48_CARDBUS 21 CLK48_USB 1 8,21 SMBC_SB 8,21 SMBD_SB R261 R260 SC 0309 21 SB_OSC_CLK 32 CLK14_AUDIO R279 R280 33R2 33R2 33R2 33R2 USB_48M SMBC_CLK SMBD_CLK 2 1 X2 X-14D318MHZ-1-U1 RN120 C399 SC2D2U16V5ZY 1 Dummy when 'NO EZ4' SRN33-2-U2 SRN33-2-U2 SBLINK_CLK# 13 SBLINK_CLK 13 RN45 SRN33-2-U2 SBSRC_CLK# 18 SBSRC_CLK 18 CLK_PCIE_DOCK1# 57 CLK_PCIE_DOCK1 57 1 1 3D3V_CLK_VDDA R264 22R2 R263 22R2 39 32 VDD_48 VDDA VDD_SRC 21 14 35 VDD_SRC VDD_SRC VDD_SRC 56 51 43 48 VDD_REF VDD_PC1 VDD_CPU VDD_HTT XIN XOUT USB_48 SCL SDA 10 11 CLKREQ0# CLKREQ1# 53 54 SEL24/24_48# REF1 REF0 SRCC0 SRCT0 SRCC3 SRCT3 SRCC4 SRCT4 SRCC5 SRCT5 SRCC6 SRCT6 SRCC7 SRCT7 33 34 25 24 23 22 19 18 17 16 13 12 CPUC1 CPUT1 CPUC0 CPUT0 40 41 44 45 SRC_CLK0# SRC_CLK0 SRC_CLK3# SRC_CLK3 SRC_CLK4# SRC_CLK4 SRC_CLK5# SRC_CLK5 RN46 2 SRN33-2-U2 RN47 CLK_PCIE_DOCK2# 57 CLK_PCIE_DOCK2 57 SRN33-2-U2 Dummy when no EZ4 CPUCLKJ_CY CPUCLK_CY R296 R297 15R2J 15R2J CPUCLK# CPUCLK RN55 SRCC1 SRCT1 SRCC2 SRCT2 29 30 28 27 VSS_SRC VSS_SRC RESET# TURBO1 36 20 15 26 VSS_CPU VSS_PCI VSS_HTT VSS_SRC VSSA VSS_48 VSS_REF 42 49 46 31 38 55 ATI_CLK0# ATI_CLK0 ATI_CLK1# ATI_CLK1 NBSRC_CLK# 13 NBSRC_CLK 13 SRN33-2-U2 RN44 SC 0309 13 CLK14_NB 37 CLK14_SIO 13 HTREF_CLK 1 R277 33R2 R274 33R2 R273 75R2F FS2 FS1 FS0 CLK_REF2 52 CLK_HTT66 47 50 R272 475R2F R298 100R2F 37 REF2 HTT66 PCI0 IREF 1 IREF_CLKGEN NC#6 GFX_CLK# 49 GFX_CLK 49 CLK_PCIE_DOCK1# R253 CLK_PCIE_DOCK1 R254 49D9R2F 49D9R2F R255 49D9R2F R256 49D9R2F CLK_PCIE_DOCK2# SRN33-2-U2 Dummy when use UMA CLK_PCIE_DOCK2 Dummy when no EZ4 R294 IDTCV137PAG CHANGE TO 71.00137.B0W SBLINK_CLK# SBLINK_CLK R295 SBSRC_CLK# R251 SBSRC_CLK R252 GFX_CLK# R249 GFX_CLK R250 SB 0219 49D9R2F 49D9R2F 49D9R2F 49D9R2F 49D9R2F 49D9R2F Dummy when use UMA 2 NBSRC_CLK# R292 NBSRC_CLK R293 49D9R2F 49D9R2F 3D3V_CLK_VDD DY R281 2K2R2 1 R275 2K2R2 1 DY FS1 DUMMY-R2 R276 R257 FS0 DUMMY-R2 R299 DY 2K2R2 DUMMY-R2 R258 for ICS FS2 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title CLKGEN_IDTCV137 Size A3 Document Number Rev A B C D -1 Bolsena Date: Thursday, March 31, 2005 Sheet E of 58 A B C D E 4 HTT for CPU sideB Receive power and NB sideA Transmit power HTT for CPU sideA Transmit power and NB sideA Receive power U81A C246 SCD22U16V3ZY C247 SCD22U16V3ZY NB0CADOUT15 NB0CADOUTJ15 NB0CADOUT14 NB0CADOUTJ14 NB0CADOUT13 NB0CADOUTJ13 NB0CADOUT12 NB0CADOUTJ12 NB0CADOUT11 NB0CADOUTJ11 NB0CADOUT10 NB0CADOUTJ10 NB0CADOUT9 NB0CADOUTJ9 NB0CADOUT8 NB0CADOUTJ8 NB0CADOUT7 NB0CADOUTJ7 NB0CADOUT6 NB0CADOUTJ6 NB0CADOUT5 NB0CADOUTJ5 NB0CADOUT4 NB0CADOUTJ4 NB0CADOUT3 NB0CADOUTJ3 NB0CADOUT2 NB0CADOUTJ2 NB0CADOUT1 NB0CADOUTJ1 NB0CADOUT0 NB0CADOUTJ0 11 NB0CADOUT[15 0] 11 NB0CADOUTJ[15 0] Used SideB Power Plane 1D2V_HT0B_S0 11 11 11 11 NB0HTTCLKOUT1 NB0HTTCLKOUTJ1 NB0HTTCLKOUT0 NB0HTTCLKOUTJ0 1 R176 49D9R2F R177 49D9R2F 11 NB0HTTCTLOUT 11 NB0HTTCTLOUTJ T25 R25 U27 U26 V25 U25 W27 W26 AA27 AA26 AB25 AA25 AC27 AC26 AD25 AC25 T27 T28 V29 U29 V27 V28 Y29 W29 AB29 AA29 AB27 AB28 AD29 AC29 AD27 AD28 VLDT0_A VLDT0_A VLDT0_A VLDT0_A VLDT0_A VLDT0_A VLDT0_A L0_CADIN_H15 L0_CADIN_L15 L0_CADIN_H14 L0_CADIN_L14 L0_CADIN_H13 L0_CADIN_L13 L0_CADIN_H12 L0_CADIN_L12 L0_CADIN_H11 L0_CADIN_L11 L0_CADIN_H10 L0_CADIN_L10 L0_CADIN_H9 L0_CADIN_L9 L0_CADIN_H8 L0_CADIN_L8 L0_CADIN_H7 L0_CADIN_L7 L0_CADIN_H6 L0_CADIN_L6 L0_CADIN_H5 L0_CADIN_L5 L0_CADIN_H4 L0_CADIN_L4 L0_CADIN_H3 L0_CADIN_L3 L0_CADIN_H2 L0_CADIN_L2 L0_CADIN_H1 L0_CADIN_L1 L0_CADIN_H0 L0_CADIN_L0 VLDT0_B VLDT0_B VLDT0_B VLDT0_B VLDT0_B VLDT0_B VLDT0_B AH29 AH27 AG28 AG26 AF29 AE28 AF25 LAYOUT: Place bypass cap on topside of board near HTT power pins that are not connected directly to HTT device, but connected internally to other HTT power pins 1 D29 D27 D25 C28 C26 B29 B27 1D2V_HT0B_S0 C245 SCD22U16V3ZY 1 C244 SCD22U16V3ZY 2 1D2V_S0 L0_CADOUT_H15 L0_CADOUT_L15 L0_CADOUT_H14 L0_CADOUT_L14 L0_CADOUT_H13 L0_CADOUT_L13 L0_CADOUT_H12 L0_CADOUT_L12 L0_CADOUT_H11 L0_CADOUT_L11 L0_CADOUT_H10 L0_CADOUT_L10 L0_CADOUT_H9 L0_CADOUT_L9 L0_CADOUT_H8 L0_CADOUT_L8 L0_CADOUT_H7 L0_CADOUT_L7 L0_CADOUT_H6 L0_CADOUT_L6 L0_CADOUT_H5 L0_CADOUT_L5 L0_CADOUT_H4 L0_CADOUT_L4 L0_CADOUT_H3 L0_CADOUT_L3 L0_CADOUT_H2 L0_CADOUT_L2 L0_CADOUT_H1 L0_CADOUT_L1 L0_CADOUT_H0 L0_CADOUT_L0 N26 N27 L25 M25 L26 L27 J25 K25 G25 H25 G26 G27 E25 F25 E26 E27 N29 P29 M28 M27 L29 M29 K28 K27 H28 H27 G29 H29 F28 F27 E29 F29 CPUCADOUT15 CPUCADOUTJ15 CPUCADOUT14 CPUCADOUTJ14 CPUCADOUT13 CPUCADOUTJ13 CPUCADOUT12 CPUCADOUTJ12 CPUCADOUT11 CPUCADOUTJ11 CPUCADOUT10 CPUCADOUTJ10 CPUCADOUT9 CPUCADOUTJ9 CPUCADOUT8 CPUCADOUTJ8 CPUCADOUT7 CPUCADOUTJ7 CPUCADOUT6 CPUCADOUTJ6 CPUCADOUT5 CPUCADOUTJ5 CPUCADOUT4 CPUCADOUTJ4 CPUCADOUT3 CPUCADOUTJ3 CPUCADOUT2 CPUCADOUTJ2 CPUCADOUT1 CPUCADOUTJ1 CPUCADOUT0 CPUCADOUTJ0 C242 downstream SC4D7U10V5ZY CPUCADOUT[15 0] 11 CPUCADOUTJ[15 0] 11 Used SideA Power Plane NB0HTTCLKOUT1 NB0HTTCLKOUTJ1 NB0HTTCLKOUT0 NB0HTTCLKOUTJ0 Y25 W25 Y27 Y28 L0_CLKIN_H1 L0_CLKIN_L1 L0_CLKIN_H0 L0_CLKIN_L0 L0_CLKOUT_H1 L0_CLKOUT_L1 L0_CLKOUT_H0 L0_CLKOUT_L0 J26 J27 J29 K29 CPUHTTCLKOUT1 CPUHTTCLKOUTJ1 CPUHTTCLKOUT0 CPUHTTCLKOUTJ0 CPUHTTCLKOUT1 CPUHTTCLKOUTJ1 CPUHTTCLKOUT0 CPUHTTCLKOUTJ0 CPUHTTCTLIN1 CPUHTTCTLINJ1 NB0HTTCTLOUT NB0HTTCTLOUTJ R27 R26 T29 R29 L0_CTLIN_H1 L0_CTLIN_L1 L0_CTLIN_H0 L0_CTLIN_L0 L0_CTLOUT_H1 L0_CTLOUT_L1 L0_CTLOUT_H0 L0_CTLOUT_L0 N25 P25 P28 P27 CPUHTTCTLOUT0 CPUHTTCTLOUTJ0 CPUHTTCTLOUT0 11 CPUHTTCTLOUTJ0 11 11 11 11 11 62.10055.091 SB 0127 ME : 60.10055.091 (3MM HEIGHT) 1 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title CPU(1/4)_HyperTransport I/F Size A3 Document Number Rev A B C D -1 Bolsena Date: Thursday, March 31, 2005 Sheet E of 58 A B C D E VREF_DDR_MEM NOTE: Test with passive probes only 1D25V_S3 U81B VTT_SENSE 2D5V_S3 C441 SCD1U AG12 R206 R205 VREF_DDR_MEM 34D8R2F 34D8R2F MEMZN MEMZP D14 C14 MEMVREF1 MEMZN MEMZP VTT_A VTT_A VTT_A VTT_A VTT_B VTT_B VTT_B VTT_B D17 A18 B17 C17 AF16 AG16 AH16 AJ17 R291 100R2F VREF_DDR_CLAW M_DATA[63 0] LAYOUT: Locate close to DIMMs NOTE: Remove to bypass op-amp VREF_DDR_CLAW C309 SCD1U VREF_DDR_CLAW R198 100R2F C311 SCD1U 2 1 R197 100R2F 2D5V_S3 C312 SC1000P50V2KX LAYOUT: Locate close to CPU Place it near CPU R203 R204 121R2F M_CLK7 M_CLK#7 121R2F M_CLK6 M_CLK#6 M_ADM[7 0] R199 121R2F M_CLK5 M_CLK#5 R200 121R2F M_CLK4 M_CLK#4 M_DQS[7 0] M_DATA63 M_DATA62 M_DATA61 M_DATA60 M_DATA59 M_DATA58 M_DATA57 M_DATA56 M_DATA55 M_DATA54 M_DATA53 M_DATA52 M_DATA51 M_DATA50 M_DATA49 M_DATA48 M_DATA47 M_DATA46 M_DATA45 M_DATA44 M_DATA43 M_DATA42 M_DATA41 M_DATA40 M_DATA39 M_DATA38 M_DATA37 M_DATA36 M_DATA35 M_DATA34 M_DATA33 M_DATA32 M_DATA31 M_DATA30 M_DATA29 M_DATA28 M_DATA27 M_DATA26 M_DATA25 M_DATA24 M_DATA23 M_DATA22 M_DATA21 M_DATA20 M_DATA19 M_DATA18 M_DATA17 M_DATA16 M_DATA15 M_DATA14 M_DATA13 M_DATA12 M_DATA11 M_DATA10 M_DATA9 M_DATA8 M_DATA7 M_DATA6 M_DATA5 M_DATA4 M_DATA3 M_DATA2 M_DATA1 M_DATA0 A16 B15 A12 B11 A17 A15 C13 A11 A10 B9 C7 A6 C11 A9 A5 B5 C5 A4 E2 E1 A3 B3 E3 F1 G2 G1 L3 L1 G3 J2 L2 M1 W1 W3 AC1 AC3 W2 Y1 AC2 AD1 AE1 AE3 AG3 AJ4 AE2 AF1 AH3 AJ3 AJ5 AJ6 AJ7 AH9 AG5 AH5 AJ9 AJ10 AH11 AJ11 AH15 AJ15 AG11 AJ12 AJ14 AJ16 MEMDATA63 MEMDATA62 MEMDATA61 MEMDATA60 MEMDATA59 MEMDATA58 MEMDATA57 MEMDATA56 MEMDATA55 MEMDATA54 MEMDATA53 MEMDATA52 MEMDATA51 MEMDATA50 MEMDATA49 MEMDATA48 MEMDATA47 MEMDATA46 MEMDATA45 MEMDATA44 MEMDATA43 MEMDATA42 MEMDATA41 MEMDATA40 MEMDATA39 MEMDATA38 MEMDATA37 MEMDATA36 MEMDATA35 MEMDATA34 MEMDATA33 MEMDATA32 MEMDATA31 MEMDATA30 MEMDATA29 MEMDATA28 MEMDATA27 MEMDATA26 MEMDATA25 MEMDATA24 MEMDATA23 MEMDATA22 MEMDATA21 MEMDATA20 MEMDATA19 MEMDATA18 MEMDATA17 MEMDATA16 MEMDATA15 MEMDATA14 MEMDATA13 MEMDATA12 MEMDATA11 MEMDATA10 MEMDATA9 MEMDATA8 MEMDATA7 MEMDATA6 MEMDATA5 MEMDATA4 MEMDATA3 MEMDATA2 MEMDATA1 MEMDATA0 M_ADM8 M_ADM7 M_ADM6 M_ADM5 M_ADM4 M_ADM3 M_ADM2 M_ADM1 M_ADM0 M_DQS8 M_DQS7 M_DQS6 M_DQS5 M_DQS4 M_DQS3 M_DQS2 M_DQS1 M_DQS0 R1 A13 A7 C2 H1 AA1 AG1 AH7 AH13 T1 A14 A8 D1 J1 AB1 AJ2 AJ8 AJ13 MEMDQS17 MEMDQS16 MEMDQS15 MEMDQS14 MEMDQS13 MEMDQS12 MEMDQS11 MEMDQS10 MEMDQS9 MEMDQS8 MEMDQS7 MEMDQS6 MEMDQS5 MEMDQS4 MEMDQS3 MEMDQS2 MEMDQS1 MEMDQS0 C267 SC1000P50V2KX For REGISTED DIMM Only UNBUFFER DIMM NC AG10 MEMRESET# M_CKE#0 M_CKE#1 M_CKE#0 8,9 M_CKE#1 8,9 D10 C10 E12 E11 AF8 AG8 AF10 AE10 V3 V4 K5 K4 R5 P5 P3 P4 M_CLK7 M_CLK#7 M_CLK6 M_CLK#6 M_CLK5 M_CLK#5 M_CLK4 M_CLK#4 M_CLK7 M_CLK#7 M_CLK6 M_CLK#6 M_CLK5 M_CLK#5 M_CLK4 M_CLK#4 MEMCS_L7 MEMCS_L6 MEMCS_L5 MEMCS_L4 MEMCS_L3 MEMCS_L2 MEMCS_L1 MEMCS_L0 D8 C8 E8 E7 D6 E6 C4 E5 M_CS#7 M_CS#6 M_CS#5 M_CS#4 M_CS#3 M_CS#2 M_CS#1 M_CS#0 M_CS#3 M_CS#2 M_CS#1 M_CS#0 MEMRASA_L MEMCASA_L MEMWEA_L H5 D4 G5 M_ARAS# M_ACAS# M_AWE# M_ARAS# 8,9 M_ACAS# 8,9 M_AWE# 8,9 MEMBANKA1 MEMBANKA0 K3 H3 M_ABS#1 M_ABS#0 M_ABS#1 8,9 M_ABS#0 8,9 NC_E13 NC_C12 MEMADDA13 MEMADDA12 MEMADDA11 MEMADDA10 MEMADDA9 MEMADDA8 MEMADDA7 MEMADDA6 MEMADDA5 MEMADDA4 MEMADDA3 MEMADDA2 MEMADDA1 MEMADDA0 E13 C12 E10 AE6 AF3 M5 AE5 AB5 AD3 Y5 AB4 Y3 V5 T5 T3 N5 RSVD_M_AA15 RSVD_M_AA14 M_AA13 M_AA12 M_AA11 M_AA10 M_AA9 M_AA8 M_AA7 M_AA6 M_AA5 M_AA4 M_AA3 M_AA2 M_AA1 M_AA0 MEMRASB_L MEMCASB_L MEMWEB_L H4 F5 F4 M_BRAS# M_BCAS# M_BWE# M_BRAS# 8,9 M_BCAS# 8,9 M_BWE# 8,9 MEMBANKB1 MEMBANKB0 L5 J5 M_BBS#1 M_BBS#0 M_BBS#1 8,9 M_BBS#0 8,9 NC_E14 NC_D12 MEMADDB13 MEMADDB12 MEMADDB11 MEMADDB10 MEMADDB9 MEMADDB8 MEMADDB7 MEMADDB6 MEMADDB5 MEMADDB4 MEMADDB3 MEMADDB2 MEMADDB1 MEMADDB0 E14 D12 E9 AF6 AF4 M4 AD5 AC5 AD4 AA5 AB3 Y4 W5 U5 T4 M3 RSVD_M_BA15 RSVD_M_BA14 M_BA13 M_BA12 M_BA11 M_BA10 M_BA9 M_BA8 M_BA7 M_BA6 M_BA5 M_BA4 M_BA3 M_BA2 M_BA1 M_BA0 MEMCHECK7 MEMCHECK6 MEMCHECK5 MEMCHECK4 MEMCHECK3 MEMCHECK2 MEMCHECK1 MEMCHECK0 N3 N1 U3 V1 N2 P1 U1 U2 MEMCKEA MEMCKEB 1 C439 SC1000P50V2KX C440 SCD1U C266 SCD1U AE8 AE7 MEMRESET_L R290 100R2F DDRVTT_SENSE AE13 TP47 TPAD30 NOTE: Install to bypass op-amp 2D5V_S3 MEMCLK_H7 MEMCLK_L7 MEMCLK_H6 MEMCLK_L6 MEMCLK_H5 MEMCLK_L5 MEMCLK_H4 MEMCLK_L4 MEMCLK_H3 MEMCLK_L3 MEMCLK_H2 MEMCLK_L2 MEMCLK_H1 MEMCLK_L1 MEMCLK_H0 MEMCLK_L0 2D5V_S3 RN36 M_CLK#1 M_CLK#0 M_CLK1 M_CLK0 M_CLK1 M_CLK#1 M_CLK0 M_CLK#0 SRN10K-2 8,9 8,9 8,9 8,9 M_AA[13 0] 8,9 AMD suggested M_AA13 connect to DIMM pin123 M_DQS8 M_ADM8 MEMRESET# M_CS#7 M_CS#6 M_CS#5 M_CS#4 RSVD_M_AA15 RSVD_M_AA14 RSVD_M_BA15 RSVD_M_BA14 M_BA[13 0] 8,9 C TPAD30 TPAD30 TPAD30 TPAD30 TPAD30 TPAD30 TPAD30 TPAD30 TPAD30 NOT SUPPORT ECC CHECK AMD suggested remove PULL-HI resistor CB7 CB6 CB5 CB4 CB3 CB2 CB1 CB0 TP60 TP90 TP59 TP83 TP89 TP88 TP84 TP85 TPAD30 TPAD30 TPAD30 TPAD30 TPAD30 TPAD30 TPAD30 TPAD30 D Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title CPU(2/4)_DDR Document Number Rev -1 Bolsena Date: Thursday, March 31, 2005 B TP44 TP53 TP54 TP49 TP61 TP50 TP55 TP51 TP52 AMD suggested M_BA13 connect to DIMM pin123 Size A3 A TP86 TPAD30 TP87 TPAD30 Sheet E of 58 A B C D E 2D5V_CPUA_S0 DY differentially impedance 100 C790 SC3900P50V3KX C789 SC3900P50V3KX CPUCLK# 820R3 820R3 1D25V_S3 R189 R190 R606 1 680R3F 680R3F 680R3F 2D5V_S0 AE12 AF12 AE11 VDDIOFB_H VDDIOFB_L VDDIO_SENSE CLKIN AJ21 AH21 CLKIN_H CLKIN_L AJ23 AH23 NC_AJ23 NC_AH23 AE24 AF24 NC_AE24 NC_AF24 C16 AG15 VTT_A VTT_B SRN680-U DY DY R207 C15 NC_C15 E20 E17 B21 A21 TMS TCK TRST_L TDI NC_C18 C18 NC_C18 NC_A19 A19 NC_A19 DY 680R3F DY CHANGE FROM 1KR3 TO 680R2 FOR AMD CHECK LIST NC_AG17 NC_AJ18 NC_D18 NC_B19 NC_C19 NC_D20 NC_C21 RN31 SRN680-U Validation Test Points LAYOUT: Place close to the CPU RN33 NC_C15 NC_AE23 NC_AF23 NC_AF22 NC_AF21 SRN680-U TP56 TP42 TP39 TP41 TP40 TPAD30 TPAD30 TPAD30 TPAD30 TPAD30 VID4 VID3 VID2 VID1 VID0 VID4 VID3 VID2 VID1 VID0 NC_AG18 NC_AH18 NC_AG17 NC_AJ18 AG18 AH18 AG17 AJ18 NC_AG18 NC_AH18 NC_AG17 NC_AJ18 41 TP37 TPAD30 TP36 TPAD30 LAYOUT: Route FBCLKOUT_H/L differentially impedance 80 FBCLKOUT FBCLKOUT_H FBCLKOUT_L FBCLKOUTJ R191 NC_AE23 NC_AF23 NC_AF22 NC_AF21 C1 J3 R3 AA2 D3 AG2 B18 AH1 AE21 C20 AG4 C6 AG6 AE9 AG9 NC_C1 NC_J3 NC_R3 NC_AA2 NC_D3 NC_AG2 NC_B18 NC_AH1 NC_AE21 NC_C20 NC_AG4 NC_C6 NC_AG6 NC_AE9 NC_AG9 AE19 DBREQJ NC_D20 NC_C21 NC_D18 NC_C19 NC_B19 D20 C21 D18 C19 B19 NC_D20 NC_C21 NC_D18 NC_C19 NC_B19 TDO A22 TDO NC_AF18 AF18 DUMMY-R3 2D5V_S3 Connect to VDDIO for AMD suggest KEY1 KEY0 AE23 AF23 AF22 AF21 R617 80D6R2F AH19 AJ19 NC_D22 NC_C22 D22 C22 THERMTRIP#Level shift to SB400 2D5V_S0 SRN680-U 2D5V_S3 THERMDP 23 THERMDN 23 VID[4 0] AG13 AF14 AG14 AF15 AE15 DBRDY TMS TCK TRST_L TDI NC_AE23 NC_AF23 NC_AF22 NC_AF21 RN32 THERMTRIP# R156 680R3F A26 A27 DBREQ_L NC_C15 R155 680R3F DBREQJ DBRDY TCK TMS TDI TRST_L TDO AH17 A28 AJ28 DY C160 SCD1U A20 THERMDA THERMDC CLKIN# NC_AJ23 NC_AH23 NC_AE24 NC_AF24 R193 680R3F R194 680R3F 2 DY RN28 2 VDDIOFB VDDIOFBJ VDDIOSENSE DBRDY 2D5V_S0 L0_REF1 L0_REF0 COREFB_H COREFB_L CORE_SENSE 2D5V_S0 LDT_RST# SB_CPUPWRGD LDT_STP# AF27 AE26 A23 A24 B23 R618 169R2F 2 RESET_L PWROK LDTSTOP_L COREFB COREFB# CORE_SENSE 2D5V_S3 R616 R605 AF20 AE18 AJ27 THERMTRIP_L NC_B13 NC_B7 NC_C3 NC_K1 NC_R2 NC_AA3 NC_F3 NC_C23 NC_AG7 NC_AE22 NC_C24 NC_A25 NC_C9 R192 680R3F B13 B7 C3 K1 R2 AA3 F3 C23 AG7 AE22 C24 A25 C9 THERMTRIP# Q10 MMBT3904-U1 CPU_THERMTRIP# 23 1 CPUCLK SANYO, NT$:6.1 Iripple=1.1A,ESR=70mohm 3.5/2.8/2.0 77.21071.031 VDDA1 VDDA2 AMD suggest voltege from 2D5V_S0 to 2D5V_S3 41 COREFB 41 COREFB# C212 SC1000P50V2KX U81C C241 SCD22U16V3ZY13,18 LDT_RST# 18 SB_CPUPWRGD 13,18 LDT_STP# C211 SC1000P50V2KX R2 DY DY L0_REF1 L0_REF0 KEMET,NT:5.7, B2 size ST100U4VBM-1 (80.10716.321) Iripple=1.1A,ESR=70mohm R152 20KR2F C734 SC1U10V3KX Vout = 1.25*(1+ R1/R2) C210 SC1U10V3KX R1 2 DY G913C-U 44D2R2F 44D2R2F AMD SUGGEST TO USE 2D5V_CPUA_S0 AH25 AJ25 R153 R154 C243 SC3300P50V2KX C240 SC4D7U10V5ZY 1D2V_HT0B_S0 TC3 SC 0308 ST100U4VBM-U DY LAYOUT: Route VDDA trace approx 50 mils wide (use 2x25 mil traces to exit ball field) and 500 mils long R175 0R0805-PAD LAYOUT: Route trace 50 mils wide and 500 to 750 mils long between these caps R174 0R3-U 1 2D5V_VDDA_S0 2D5V_CPUA_S0 Change L270H SET OUT DY 2 C239 SC10U10V5ZY 2D5V_CPUR_S0 R173 0R0603-PAD SC 0308 SHDN# GND IN 2D5V_VDDA_VREF 1 U73 DY R604 20KR2F C733 SC22P50V2JN-1 Iomax=120mA AMD SUGGEST TO USE 100 ~ 300UH 3D3V_S0 2D5V_S0 2D5V_VDDA_S0 2D5V_S0 NS3 R195 1KR2 SB 0201 LDT_RST# CLKIN CLKIN# CORE_SENSE VDDIOFB VDDIOFBJ VDDIOSENSE NC_AE24 NC_AF24 TP38 TP34 TP35 TP43 TP46 TP45 TP48 TP27 TP26 TPAD30 TPAD30 TPAD30 TPAD30 TPAD30 TPAD30 TPAD30 TPAD30 TPAD30 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title CPU(3/4)_Control & Debug Size A3 Document Number Rev A B C D -1 Bolsena Date: Thursday, March 31, 2005 Sheet E of 58 A B C D E U81E U81D 1 SC10U10V5ZY C793 SC10U10V5ZY C817 2 SC10U10V5ZY C272 C315 SC10U10V5ZY C818 SCD22U16V3ZY 1 C318 SCD22U16V3ZY C316 SCD22U16V3ZY SCD22U16V3ZY 2 C791 SCD22U16V3ZY 1 C269 SCD22U16V3ZY C271 LAYOUT: Place on backside of processor 2 1 C816 C813 C794 C815 C814 C792 SCD22U16V3ZY SCD22U16V3ZY SCD22U16V3ZY SCD22U16V3ZY SC10U10V5ZY SC10U10V5ZY VCC_CORE_S0 10u x 0.22u x DY DY DY 2D5V_S3 DY 4.7u x SC4D7U10V5ZY C366 C367 SC4D7U10V5ZY C317 SC4D7U10V5ZY 1 SC4D7U10V5ZY C365 C314 SC4D7U10V5ZY SC10U10V5ZY 10u x C313 SC4D7U10V5ZY 1 C320 4.7u x SC4D7U10V5ZY C265 SC4D7U10V5ZY 0.22u x C276 C274 C275 SCD22U16V3ZY 1D25V_S3 1D25V_S3 C341 C319 SCD22U16V3ZY C273 SCD22U16V3ZY C339 SCD22U16V3ZY C340 SCD22U16V3ZY C268 SCD22U16V3ZY VCC_CORE_S0 2D5V_S3 N28 U28 AA28 AE27 R7 U7 W7 K8 M8 P8 T8 V8 Y8 J9 N9 R9 U9 W9 AA9 H10 K10 M10 P10 T10 Y10 AB10 G11 J11 AA11 AC11 H12 K12 Y12 AB12 J13 AA13 AC13 H14 AB26 E28 J28 10u x 0.22u x SCD22U16V3ZY VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD LAYOUT: Place in uPGA socket cavity VCC_CORE_S0 E4 G4 J4 L4 N4 U4 W4 AA4 AC4 AE4 D5 AF5 F6 H6 K6 M6 P6 T6 V6 Y6 AB6 AD6 D7 G7 J7 AA7 AC7 AF7 F8 H8 AB8 AD8 D9 G9 AC9 AF9 F10 AD10 D11 AF11 F12 AD12 D13 AF13 F14 AD14 F16 AD16 D15 R4 VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD L7 AC15 H18 B20 E21 H22 J23 H24 F26 N7 L9 V10 G13 K14 Y14 AB14 G15 J15 AA15 H16 K16 Y16 AB16 G17 J17 AA17 AC17 AE17 F18 K18 Y18 AB18 AD18 AG19 E19 G19 AC19 AA19 J19 F20 H20 K20 M20 P20 T20 V20 Y20 AB20 AD20 G21 J21 L21 N21 R21 U21 W21 AA21 AC21 F22 K22 M22 P22 T22 V22 Y22 AB22 AD22 E23 G23 L23 N23 R23 U23 W23 AA23 AC23 B24 D24 F24 K24 M24 P24 T24 V24 Y24 AB24 AD24 AH24 AE25 K26 P26 V26 SCD22U16V3ZY VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 2D5V_S3 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCC_CORE_S0 Y17 K17 H17 F17 E18 AJ26 AE29 AC16 AA16 J16 G16 E16 AH14 AD15 AB15 K15 E15 D16 AE14 AC14 AA14 J14 G14 AF17 AD13 AB13 Y13 K13 H13 F13 AH12 AC12 AA12 G12 B12 AD11 AB11 Y11 K11 H11 F11 AH10 AC10 W10 U10 R10 N10 L10 J10 G10 B10 AD9 Y9 V9 T9 P9 M9 K9 H9 F9 AH8 AC8 W8 U8 R8 N8 L8 J8 G8 B8 AD7 AB7 V7 T7 P7 M7 K7 H7 F7 AH6 AC6 AA6 U6 R6 N6 L6 J6 G6 B6 AH4 B4 AH2 AD2 AB2 Y2 V2 T2 P2 M2 K2 H2 F2 C29 AH28 AF28 AC28 W28 R28 L28 N20 L20 J20 AF19 AD19 AB19 Y19 K19 H19 F19 D19 AC18 AA18 G18 B16 AD17 AB17 H15 F15 G28 D28 B28 C27 AH26 AF26 AD26 Y26 T26 M26 H26 D26 B26 C25 B25 AJ24 AG24 AC24 AA24 W24 U24 R24 N24 J24 G24 E24 AG23 AD23 AB23 Y23 V23 T23 P23 K23 H23 F23 D23 AJ22 AH22 AG22 AC22 AA22 AG29 U22 R22 N22 L22 J22 G22 E22 B22 AG21 AD21 Y21 V21 T21 P21 M21 K21 H21 F21 D21 AJ20 AG20 AE20 AC20 AA20 W20 U20 R20 G20 J18 AE16 Y15 B14 J12 AA10 AB9 AA8 Y7 W6 AF2 D2 AG27 AG25 L24 M23 W22 AB21 AH20 B2 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title CPU(4/4)_Power Size A3 Document Number Rev A B C D -1 Bolsena Date: Thursday, March 31, 2005 Sheet E of 58 A B C BA0 BA1 M_DATA_R_0 M_DATA_R_1 M_DATA_R_2 M_DATA_R_3 M_DATA_R_4 M_DATA_R_5 M_DATA_R_6 M_DATA_R_7 M_DATA_R_8 M_DATA_R_9 M_DATA_R_10 M_DATA_R_11 M_DATA_R_12 M_DATA_R_13 M_DATA_R_14 M_DATA_R_15 M_DATA_R_16 M_DATA_R_17 M_DATA_R_18 M_DATA_R_19 M_DATA_R_20 M_DATA_R_21 M_DATA_R_22 M_DATA_R_23 M_DATA_R_24 M_DATA_R_25 M_DATA_R_26 M_DATA_R_27 M_DATA_R_28 M_DATA_R_29 M_DATA_R_30 M_DATA_R_31 M_DATA_R_32 M_DATA_R_33 M_DATA_R_34 M_DATA_R_35 M_DATA_R_36 M_DATA_R_37 M_DATA_R_38 M_DATA_R_39 M_DATA_R_40 M_DATA_R_41 M_DATA_R_42 M_DATA_R_43 M_DATA_R_44 M_DATA_R_45 M_DATA_R_46 M_DATA_R_47 M_DATA_R_48 M_DATA_R_49 M_DATA_R_50 M_DATA_R_51 M_DATA_R_52 M_DATA_R_53 M_DATA_R_54 M_DATA_R_55 M_DATA_R_56 M_DATA_R_57 M_DATA_R_58 M_DATA_R_59 M_DATA_R_60 M_DATA_R_61 M_DATA_R_62 M_DATA_R_63 13 17 14 18 19 23 29 31 20 24 30 32 41 43 49 53 42 44 50 54 55 59 65 67 56 60 66 68 127 129 135 139 128 130 136 140 141 145 151 153 142 146 152 154 163 165 171 175 164 166 172 176 177 181 187 189 178 182 188 190 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 CKE0 CKE1 96 95 DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS8 11 25 47 61 133 147 169 183 77 M_DQS_R0 M_DQS_R1 M_DQS_R2 M_DQS_R3 M_DQS_R4 M_DQS_R5 M_DQS_R6 M_DQS_R7 DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 DM8 12 26 48 62 134 148 170 184 78 M_ADM_R0 M_ADM_R1 M_ADM_R2 M_ADM_R3 M_ADM_R4 M_ADM_R5 M_ADM_R6 M_ADM_R7 CK0 /CK0 CK1 /CK1 CK2 /CK2 35 37 160 158 89 91 DDR_CLK0 DDR_CLK#0 SCL SDA 195 193 SMBC_SB SMBD_SB SA0 SA1 SA2 194 196 198 VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD 10 21 22 33 34 36 45 46 57 58 69 70 81 82 92 93 94 113 114 131 132 143 144 155 156 157 167 168 179 180 191 192 15 16 27 28 38 39 40 51 52 63 64 75 76 87 88 90 103 104 125 126 137 138 149 150 159 161 162 173 174 185 186 202 85 86 97 98 123 124 200 NC#85 NC#86/(RESET#) NC#97/A13 NC#98/BA2 NC#123 NC#124 NC#200 5,9 M_ARAS# 5,9 M_ACAS# 5,9 M_AWE# 118 120 119 /RAS /CAS /WE VREF_DDR_MEM 197 199 VREF VREF VDDSPD VDDID VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 201 GND GND 71 73 79 83 72 74 80 84 M_AA13 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 1 C458 SCD1U 2 Layout trace 20 mil 3D3V_S0 C456 SCD1U TP62 TPAD30 M_CS#0 5,9 M_CS#1 5,9 M_CKE#0 M_CKE#0 5,9 M_ADM#0 M_ADM#1 M_ADM#2 M_ADM#3 M_ADM#4 M_ADM#5 M_ADM#6 M_ADM#7 M_CLK5 M_CLK#5 M_CLK7 M_CLK#7 2D5V_S3 NOT SUPPORT ECC CHECK AMD suggested pull-low M_BA0 M_BA1 M_BA2 M_BA3 M_BA4 M_BA5 M_BA6 M_BA7 M_BA8 M_BA9 M_BA10 M_BA11 M_BA12 112 111 110 109 108 107 106 105 102 101 115 100 99 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 / AP A11 A12 M_BBS#0 M_BBS#1 117 116 BA0 BA1 M_DATA_R_0 M_DATA_R_1 M_DATA_R_2 M_DATA_R_3 M_DATA_R_4 M_DATA_R_5 M_DATA_R_6 M_DATA_R_7 M_DATA_R_8 M_DATA_R_9 M_DATA_R_10 M_DATA_R_11 M_DATA_R_12 M_DATA_R_13 M_DATA_R_14 M_DATA_R_15 M_DATA_R_16 M_DATA_R_17 M_DATA_R_18 M_DATA_R_19 M_DATA_R_20 M_DATA_R_21 M_DATA_R_22 M_DATA_R_23 M_DATA_R_24 M_DATA_R_25 M_DATA_R_26 M_DATA_R_27 M_DATA_R_28 M_DATA_R_29 M_DATA_R_30 M_DATA_R_31 M_DATA_R_32 M_DATA_R_33 M_DATA_R_34 M_DATA_R_35 M_DATA_R_36 M_DATA_R_37 M_DATA_R_38 M_DATA_R_39 M_DATA_R_40 M_DATA_R_41 M_DATA_R_42 M_DATA_R_43 M_DATA_R_44 M_DATA_R_45 M_DATA_R_46 M_DATA_R_47 M_DATA_R_48 M_DATA_R_49 M_DATA_R_50 M_DATA_R_51 M_DATA_R_52 M_DATA_R_53 M_DATA_R_54 M_DATA_R_55 M_DATA_R_56 M_DATA_R_57 M_DATA_R_58 M_DATA_R_59 M_DATA_R_60 M_DATA_R_61 M_DATA_R_62 M_DATA_R_63 13 17 14 18 19 23 29 31 20 24 30 32 41 43 49 53 42 44 50 54 55 59 65 67 56 60 66 68 127 129 135 139 128 130 136 140 141 145 151 153 142 146 152 154 163 165 171 175 164 166 172 176 177 181 187 189 178 182 188 190 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 REVERSE TYPE 9.2MM 117 116 121 122 /CS0 /CS1 121 122 CKE0 CKE1 96 95 DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS8 11 25 47 61 133 147 169 183 77 M_DQS_R0 M_DQS_R1 M_DQS_R2 M_DQS_R3 M_DQS_R4 M_DQS_R5 M_DQS_R6 M_DQS_R7 DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 DM8 12 26 48 62 134 148 170 184 78 M_ADM_R0 M_ADM_R1 M_ADM_R2 M_ADM_R3 M_ADM_R4 M_ADM_R5 M_ADM_R6 M_ADM_R7 CK0 /CK0 CK1 /CK1 CK2 /CK2 35 37 160 158 89 91 SCL SDA 195 193 SA0 SA1 SA2 194 196 198 VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD 10 21 22 33 34 36 45 46 57 58 69 70 81 82 92 93 94 113 114 131 132 143 144 155 156 157 167 168 179 180 191 192 15 16 27 28 38 39 40 51 52 63 64 75 76 87 88 90 103 104 125 126 137 138 149 150 159 161 162 173 174 185 186 202 85 86 97 98 123 124 200 NC#85 NC#86/(RESET#) NC#97/A13 NC#98/BA2 NC#123 NC#124 NC#200 5,9 M_BRAS# 5,9 M_BCAS# 5,9 M_BWE# 118 120 119 /RAS /CAS /WE VREF_DDR_MEM 197 199 VREF VREF VDDSPD VDDID VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 201 GND GND 71 73 79 83 72 74 80 84 1ST 62.10017.701 - 2ND 62.10017.201 M_BA13 Part Number = 62.10017.201 DDR-SODIMM-R-U2 Layout trace 20 mil ME : 62.10017.201 2nd :62.10017.701 M_ABS#0 M_ABS#1 /CS0 /CS1 C497 SCD1U 2 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 / AP A11 A12 112 111 110 109 108 107 106 105 102 101 115 100 99 M_AA0 M_AA1 M_AA2 M_AA3 M_AA4 M_AA5 M_AA6 M_AA7 M_AA8 M_AA9 M_AA10 M_AA11 M_AA12 D 3D3V_S0 C498 SCD1U TP63 TPAD30 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 M_CS#2 5,9 M_CS#3 5,9 M_CKE#1 5,9 ! NOT THIS LIBRARY M_ADM_R[7 0] M_ADM#0 M_ADM#1 M_ADM#2 M_ADM#3 M_ADM#4 M_ADM#5 M_ADM#6 M_ADM#7 M_DATA_R_[63 0] M_DQS_R[7 0] B C M_AA[13 0] 5,9 M_ABS#[1 0] 5,9 M_BA[13 0] 5,9 M_CLK4 M_CLK#4 M_CLK6 M_CLK#6 DDR_CLK1 DDR_CLK#1 M_BBS#[1 0] 5,9 SMBC_SB 3,21 SMBD_SB 3,21 DM_SA0 R312 4K7R2 3D3V_S0 2D5V_S3 RN62 DDR_CLK#1 DDR_CLK#0 DDR_CLK1 DDR_CLK0 SRN10K-2 SB 0203 AMD CPU MD63 SMA11 2D5V_S3 DDR1(Reverse 5.2mm) DDR2(Reverse 9.2mm) SMA10 SMA0 SMA14 SMA12 MD0 Pin 199 Pin Pin 200 Pin Pin 199 Pin Pin 200 Pin (Bottom view) Wistron Corporation 62.10017.391 ME : 62.10017.391 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title DDR SO-DIMM SKT Size A3 Document Number Rev D -1 Bolsena Date: Thursday, March 31, 2005 SKT-SODIMM2006U1 A E DDR2 REVERSE TYPE 5.2MM DDR1 Sheet E of 58 A B C D SERIES DAMPING PARALLEL TERMINATION PLACE RNs CLOSE TO FIRST DIMM, < 0.75" STRICT EQUAL LENGTH LIMITATION WITH DQS, CB PINS SRN10J-3 M_DATA4 M_DATA5 M_ADM0 M_DATA6 M_DATA7 M_DATA13 M_DATA12 M_ADM1 10 11 12 13 14 15 16 M_DATA_R_4 M_DATA_R_5 M_ADM_R0 M_DATA_R_6 M_DATA_R_7 M_DATA_R_13 M_DATA_R_12 M_ADM_R1 RN49 PULL HIGH STUBS < 0.8", PLACE RPs CLOSE TO SECOND DM ( DM2 ) NO EQUAL LENGTH LIMITATION M_DATA37 M_DATA36 M_ADM4 M_DATA39 M_DATA32 M_DATA33 M_DQS4 M_DATA34 10 11 12 13 14 15 16 M_DATA_R_1 M_DATA_R_0 M_DQS_R0 M_DATA_R_2 M_DATA_R_3 M_DATA_R_8 M_DATA_R_9 M_DQS_R1 M_DATA35 M_DATA41 M_DATA40 M_DQS5 M_DATA42 M_DATA43 M_DATA49 M_DATA48 SRN10J-3 M_DATA_R_14 M_DATA_R_15 M_DATA_R_21 M_DATA_R_20 M_ADM_R2 M_DATA_R_23 M_DATA_R_22 M_DATA_R_28 M_DATA38 M_DATA45 M_DATA44 M_ADM5 M_DATA47 M_DATA46 M_DATA53 M_DATA52 SRN10J-3 M_DATA24 M_DQS3 M_DATA26 M_DATA27 M_DATA_R_38 M_DATA_R_45 M_DATA_R_44 M_ADM_R5 M_DATA_R_47 M_DATA_R_46 M_DATA_R_53 M_DATA_R_52 10 11 12 13 14 15 16 M_DQS_R6 M_DATA_R_50 M_DATA_R_51 M_DATA_R_56 M_DATA_R_57 M_DQS_R7 M_DATA_R_58 M_DATA_R_59 10 11 12 13 14 15 16 M_ADM_R6 M_DATA_R_54 M_DATA_R_55 M_DATA_R_61 M_DATA_R_60 M_ADM_R7 M_DATA_R_62 M_DATA_R_63 SRN10J-3 10 11 12 13 14 15 16 M_DATA_R_11 M_DATA_R_10 M_DATA_R_17 M_DATA_R_16 M_DQS_R2 M_DATA_R_19 M_DATA_R_18 M_DATA_R_25 M_DQS6 M_DATA50 M_DATA51 M_DATA56 M_DATA57 M_DQS7 M_DATA58 M_DATA59 RN39 M_DATA29 M_ADM3 M_DATA31 M_DATA30 10 11 12 13 14 15 16 RN53 1D25V_S3 RN43 RN51 SRN10-1 M_DATA_R_29 M_ADM_R3 M_DATA_R_31 M_DATA_R_30 M_DATA_R_24 M_DQS_R3 M_DATA_R_26 M_DATA_R_27 SRN10J-3 M_ADM6 M_DATA54 M_DATA55 M_DATA61 M_DATA60 M_ADM7 M_DATA62 M_DATA63 RN54 1D25V_S3 SRN68J-1 M_ADM_R1 M_DATA_R_13 M_DATA_R_12 M_DATA_R_7 M_DATA_R_6 M_ADM_R0 M_DATA_R_5 M_DATA_R_4 10 11 12 13 14 15 16 M_DATA_R_32 M_DATA_R_33 M_DQS_R4 M_DATA_R_35 M_DATA_R_1 M_DATA_R_0 M_DQS_R0 M_DATA_R_2 M_DATA_R_3 M_DATA_R_8 M_DATA_R_9 M_DQS_R1 M_DATA_R_28 M_DATA_R_23 M_DATA_R_22 M_ADM_R2 M_DATA_R_21 M_DATA_R_20 M_DATA_R_15 M_DATA_R_14 10 11 12 13 14 15 16 10 11 12 13 14 15 16 RN59 SRN68J-1 M_DATA_R_36 M_DATA_R_37 M_ADM_R4 M_DATA_R_38 M_BA12 M_BA5 1 M_DATA_R_31 M_DATA_R_30 M_ADM_R3 M_DATA_R_29 M_DQS_R[7 0] SRN47J-1-U M_AA11 M_AA9 M_AA7 M_AA5 M_AA4 M_AA8 M_AA6 M_AA3 10 11 12 13 14 15 16 M_DATA_R_48 M_DATA_R_49 M_DATA_R_43 M_DATA_R_42 M_DQS_R5 M_DATA_R_41 M_DATA_R_40 M_DATA_R_34 10 11 12 13 14 15 16 M_DATA_R_39 M_DATA_R_44 M_DATA_R_45 M_ADM_R5 M_DATA_R_46 M_DATA_R_47 M_DATA_R_52 M_DATA_R_53 M_ABS#[1 0] 5,8 M_BA[13 0] 5,8 M_BBS#[1 0] 5,8 M_AWE# 5,8 M_ACAS# 5,8 M_ARAS# 5,8 RN64SRN47-1 M_BWE# 5,8 M_BCAS# 5,8 M_BRAS# 5,8 RN109 10 11 12 13 14 15 16 10 11 12 13 14 15 16 5 10 11 12 13 14 15 16 M_CS#0 M_CS#1 M_CS#2 M_CS#3 SRN47J 5,8 5,8 5,8 5,8 RN70 M_BA3 M_BA7 M_DATA_R_59 M_DATA_R_58 M_DQS_R7 M_DATA_R_57 M_DATA_R_56 M_DATA_R_51 M_DATA_R_50 M_DQS_R6 M_AA1 M_AA10 M_AA2 M_AA0 M_ABS#1 M_ARAS# M_CS#2 M_BA13 M_BA9 M_BA6 M_BA10 M_BA1 M_BA2 M_BA0 M_BBS#0 M_BWE# 3 SRN47J SRN47J-1-U 10 11 12 13 14 15 16 5,8 M_CKE#0 M_CKE#0 5,8 M_CKE#1 M_CKE#1 RN65 SRN47J-1-U RN69 SRN68J-1 RN61 SRN68-1 RN67 M_AWE# M_ABS#0 M_AA[13 0] 5,8 10 11 12 13 14 15 16 M_CS#3 M_BCAS# M_BRAS# M_BBS#1 M_DQS[7 0] RN63 RN111 SRN68J-1 RN60 M_DATA_R_27 M_DATA_R_26 M_DQS_R3 M_DATA_R_25 M_DATA_R_[63 0] RN68 SRN68J-1 RN114 SRN68J-1 M_DATA_R_11 M_DATA_R_10 M_DATA_R_16 M_DATA_R_17 M_DQS_R2 M_DATA_R_19 M_DATA_R_18 M_DATA_R_24 M_ADM[7 0] M_DATA[63 0] RN57 SRN47J SRN68J-1 RN40 SRN10-1 M_ADM_R6 M_DATA_R_54 M_DATA_R_55 M_DATA_R_60 M_DATA_R_61 M_ADM_R7 M_DATA_R_62 M_DATA_R_63 10 11 12 13 14 15 16 RN71 SRN47-1 RN112 M_BA4 M_BA8 M_BA11 M_CKE#1 RN115SRN68-1 2 RN110SRN68-1 SRN68J-1 M_ADM_R[7 0] SRN47J M_CKE#0 M_AA12 RN66 SRN68-1 RN113 M_DATA_R_35 M_DATA_R_41 M_DATA_R_40 M_DQS_R5 M_DATA_R_42 M_DATA_R_43 M_DATA_R_49 M_DATA_R_48 10 11 12 13 14 15 16 SRN10J-3 10 11 12 13 14 15 16 RN50 M_DATA11 M_DATA10 M_DATA17 M_DATA16 M_DQS2 M_DATA19 M_DATA18 M_DATA25 M_DATA_R_32 M_DATA_R_33 M_DQS_R4 M_DATA_R_34 RN42 3 8 RN38 M_DATA14 M_DATA15 M_DATA21 M_DATA20 M_ADM2 M_DATA23 M_DATA22 M_DATA28 RN52 SRN10-1 M_DATA_R_37 M_DATA_R_36 M_ADM_R4 M_DATA_R_39 RN41 SRN10-1 SRN10J-3 SRN10J-3 M_DATA1 M_DATA0 M_DQS0 M_DATA2 M_DATA3 M_DATA8 M_DATA9 M_DQS1 E RN108 SRN47-1 M_AA13 M_CS#0 M_CS#1 M_ACAS# RN58 1 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title DDR DAMPING & TERMINATION 05/10 Remove the damping resistor for AMD suggest Size A3 Document Number Date: Thursday, March 31, 2005 A B C D Rev -1 Bolsena Sheet E of 58 A B C D E 4 LAYOUT:Place altemating caps to GND and 2D5_S3 C310 SCD1U DY DY DY DY C337 SCD1U C362 SCD1U C361 SCD1U C385 SCD1U C386 SCD1U C404 SCD1U C405 SCD1U C437 SCD1U C436 SCD1U C496 SCD1U C878 SCD1U C876 SCD1U C874 SCD1U C872 SCD1U C870 SCD1U C868 SCD1U DY C455 SCD1U DY DY DY DY DY DY C387 SCD1U C454 SCD1U C338 SCD1U C438 SCD1U C406 SCD1U C407 SCD1U C388 SCD1U C364 SCD1U C363 SCD1U C871 SCD1U C869 SCD1U C867 SCD1U C877 SCD1U C875 SCD1U C873 SCD1U 1D25V_S3 2D5V_S3 C308 SCD1U DY 3 2D5V_S3 DY DY DY DY C448 SCD1U C449 SCD1U C412 SCD1U C390 SCD1U C371 SCD1U C343 SCD1U C322 SCD1U C411 SCD1U C370 SCD1U C504 SCD1U C884 SCD1U C880 SCD1U C890 SCD1U C888 SCD1U C886 SCD1U C882 SCD1U DY C502 SCD1U C457 SCD1U C463 SCD1U C462 SCD1U C459 SCD1U C460 SCD1U C465 SCD1U DY DY DY DY DY DY C466 SCD1U C447 SCD1U C410 SCD1U C408 SCD1U C389 SCD1U C369 SCD1U C342 SCD1U C321 SCD1U C409 SCD1U C368 SCD1U C503 SCD1U C889 SCD1U C887 SCD1U C885 SCD1U C883 SCD1U C881 SCD1U C879 SCD1U 2 1D25V_S3 1D25V_S3 DY DY DY DY DY DY DY C467 SCD1U DY 2 LAYOUT:Place close to Power Pin of DDR socket 2D5V_S3 LAYOUT:Place at end of the DIMMs 2D5V_S3 DY C445 SCD22U16V3ZY C464 SCD22U16V3ZY C443 SCD22U16V3ZY C501 SCD22U16V3ZY C446 DY SCD22U16V3ZY C500 SCD22U16V3ZY C444 SCD22U16V3ZY C461 SCD22U16V3ZY C442 SCD22U16V3ZY C499 SCD22U16V3ZY C891 SC10U10V5ZY C865 SC10U10V5ZY C892 SC10U10V5ZY TC26 SE100U10VM TC17 ST100U4VBM-U 2 1D25V_S3 C866 SC10U10V5ZY 79.10711.4C1 DY DY SB DY 0.22u x 10 1 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title DDR DECOUPLING Size A3 Document Number Rev A B C D -1 Bolsena Date: Thursday, March 31, 2005 Sheet E 10 of 58 (2D5V=>CH1 , 1D2V=>CH2 , 1D8V =>CH3) For 1.2V SETTING=1.2172V C840 SC4700P50V3KX C352 R653 4K32R2F close to IC R234 2KR2F close to IC 5130_5V_LDO C378 SC3300P50V3KX C374 SC5600P50V3KX 330R2 5130_FB2 78.56224.2B1 19K6R3F Condition R231 2KR2F Voltage H : Auto PWM/SKIP PWM_SEL 1 L : PWM fixed (300KHz) 1D8V_OCP R222 5130_OUT1U 45 5130_OUT1D 45 SC 10 5130_SS_STBY2 5130_SS_STBY1 PM_SLP_S5 1D2V_S0_EN# R657 100KR2 5130_FB1 5130_SS_STBY1 5130_INV2 5130_FB2 5130_SS_STBY2 5130_PWMSEL 5130_CT PM_SLP_S3# DUMMY-R2 5130_REF 2 SC4700P50V3KX R658 R656 100KR2 C379 DCBATOUT_5130 R235 100KR2 STBY_REF 5130_STBY_LDO 10 11 12 5130_LH2 C354 LL2 OUT2_U LH2 VIN VREF3.3 VREF5 REG5V_IN LDO_IN LDO_CUR LDO_GATE LDO_OUT INV_LDO 5130_LL2 45,56 36 35 34 33 32 31 30 29 28 27 26 25 close to IC 5130_LH3 2N7002DW 5130_OUT2U 5130_REGIN 5130_OUT2U 45 R651 0R0805-PAD 5130_3D3V_LDO 5130_5V_LDO C355 SCD1U50V3KX R660 10KR2 S5PWR_ENABLE 23,43 5130_SS_STBY3 DY 84.27002.03F C384 SC1500P50V3KX 43 5130_PGOUT 5V_AUX_S5 5130_3D3V_LDO GAP-CLOSE ZZ.CON2C.XX1 SC 0310 C357 SC4D7U10V5ZY 78.47593.411 C356 SC4D7U10V5ZY 78.47593.411 0R3-U B 5130_OUT3D 45 5130_OUT3U 45 C358 5130_LL3 45,56 SCD1U50V3KX SC 0310 5130_5V_LDO PWM_SEL * 83.00054.L03 Condition Voltage H : Auto PWM/SKIP 2.2V(Min)~ L : PWM fixed (300KHz) ~0.3V(Max) DCBATOUT_5130 BAT54-1 5130_TRIP3 A 5130_REF C382 SC2200P50V2KX Wistron Corporation DY 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C R661 0R0402-PAD DY 5130_STBY_LDO 0R2-0 1 R659 PM_SLP_S3# SB 0201 A 18,21,34,38,39,43,55,57 C 5V_S5 SC 0308 5130_PG_DELAY 2 G79 TPS5130PT-U D13 R664 TPS5130_1D8V_EN# 100KR2 GAP-CLOSE-PWR G83 5130_SS_STBY3 5130_FB3 5130_INV3 5V_S0 1 SB 0201 13 14 15 16 17 18 19 20 21 22 23 24 C380 SC47P50V2JN 78.47034.1F1 TSLCX14MTC-L-U U89 GAP-CLOSE-PWR G84 GAP-CLOSE ZZ.CON2C.XX1 G114 DCBATOUT_5130 SS_STBY3 FB3 INV3 PGOUT PG_DELAY TRIP3 VIN_SENSE3 LH3 OUT3_U LL3 OUT3_D OUTGND3 5130_CT 5130_OUT3D 5130_LL3 5130_OUT3U 5V_AUX_S5 1 5130_LL2 SCD1U50V3KX R650 1D2V_S0_EN# GAP-CLOSE-PWR G77 SC 0310 14 G113 TPS5130 B GAP-CLOSE-PWR G80 U26 FB1 SS_STBY1 INV2 FB2 SS_STBY2 PWM_SEL CT GND REF STBY_VREF5 STBY_VREF3.3 STBY_LDO 3D3V_AUX_S5 39 1D2V_S0_EN D GAP-CLOSE ZZ.CON2C.XX1 LDO SETTING U54D GAP-CLOSE-PWR G81 5130_OUT2D 45 48 47 46 45 44 43 42 41 40 39 38 37 SC1500P50V3KX 5130_3D3V_LDO 11 GAP-CLOSE-PWR G78 OCP 8.4A=>R229=12.65K 10A=>R229=22K 21,34,57 PM_SLP_S5# 2N7002DW 14 U54E TSLCX14MTC-L-U 5130_OUT2D INV1 FLT LH1 OUT1_U LL1 OUT1_D OUTGND1 TRIP1 VIN_SENSE12 TRIP2 OUTGND2 OUT2_D U88 GAP-CLOSE-PWR SCD1U close to IC 5130_FLT 5130_INV1 C375 SCD01U16V2KX T(soft)=1.736ms 3D3V_AUX_S5 DCBATOUT_5130 12K1R2F C359 DCBATOUT_5130 5130_FLT C377 5130_TRIP1 5130_TRIP2 C OCP 8.4A=>R226=13K 10A=>R226=22K 5130_TRIP3 ~0.3V(Max) C376 5130_INV1 SC3900P50V3KX 5130_FB1 SB 0201 SCD1U close to IC 5130_LL1 45,56 5130_OUT1U 5130_OUT1D 2.2V(Min)~ close to IC * C353 5130_LL1 SCD1U50V3KX DCBATOUT_5130 C351 D11 83.00054.L03 BAT54-1 BAT54-1 5130_LH1 R655 GAP-CLOSE-PWR G82 2 11K3R2F 5130_TRIP2 SC 0310 R649 10KR2F-U 5130_INV2 2D5V_PWR R232 R220 SC 83.00054.L03 OCP 12A=>R225=18K 18A=>R225=28K 1D2V_OCP D12 For 2.5V SETTING=2.516V SCD1U 5130_5V_LDO C383 5130_INV3 SC3900P50V3KX 5130_FB3 2 680R3F 10KR2F-U 2 close to IC DCBATOUT_5130 18KR2F D 5130_TRIP1 R233 G76 R221 SC 1D2V_PWR R654 R652 2KR2F DCBATOUT_5130 2D5V_OCP 1 C360 SC5600P50V3KX 78.56224.2B1 R663 11K5R2F DCBATOUT Vo=(R1*0.85)/R2+0.85 R236 680R3F R662 10KR2F-U 2 1D8V_PWR 1 TI TPS5130 for 2.5V, 1.2V, 1.8V For 1.8V SETTING=1.8275V C381 SC1U10V3ZY SB 0201 Title TPS5130 1D2V/1D8V2D5V/ (1/2) SC 0308 Size A3 SB 0201 (Power Team) Document Number Rev Bolsena Date: Thursday, March 31, 2005 -1 Sheet 44 of 58 TI TPS5130 for 2D5V, 1D2V, 1D8V (2D5V=>CH1 , 1D2V=>CH2 , 1D8V =>CH3) 2D5V_PWR L28 IND-4D7UH-16-GP 68.4R71B.101 2 D D D D SB 0127 2D5V Iomax=9A OCP>18A TC12 ST220U4VDM-10 TC13 ST330U6D3VDM-7 5130_OUT1D DCBATOUT_5130 C 1 GAP-CLOSE-PWR G28 GAP-CLOSE-PWR G22 GAP-CLOSE-PWR G26 GAP-CLOSE-PWR G25 GAP-CLOSE-PWR G23 GAP-CLOSE-PWR G24 SC 0310 SC 0310 D GAP-CLOSE-PWR G27 DY KEMET, NTD:10.5 (Q1) ESR=25mohm Iripple=2.2A 7.3*4.3*1.9 SC 0310 44 5130_OUT1D SC 0310 G S S S U86 AO4422 2D5V_S3 G21 1 5130_OUT1U 5130_LL1 Imax=9.3A Rdson=19.6~24mohm 44 5130_OUT1U 44,56 5130_LL1 2D5V_PWR C841 SC10U35V0ZY-L D D D D G S S S U91 AO4422 C839 SCD1U D 1 DCBATOUT_5130 C C837 SCD1U C838 SC10U35V0ZY-L SB 0127 D D D D U84 AO4422 GAP-CLOSE-PWR 1D2V_PWR 1D2V_S0 G S S S 44 5130_OUT2U 44,56 5130_LL2 Imax=9.3A Rdson=19.6~24mohm 1D2V_PWR L27 5130_OUT2U 5130_LL2 TC11 ST220U4VDM-10 GAP-CLOSE-PWR G19 GAP-CLOSE-PWR G16 GAP-CLOSE-PWR G17 GAP-CLOSE-PWR G18 GAP-CLOSE-PWR G14 GAP-CLOSE-PWR G15 SB 0127 Imax=9.3A Rdson=19.6~24mohm 5130_OUT2D G S S S Imax=9.3A Rdson=19.6~24mohm 1D8V_PWR L29 5130_OUT3U 5130_LL3 G S S S A Imax=5.5A DCR=40mOhm 7*7*3.0 44 5130_OUT3D 5130_OUT3D Imax=9.3A Rdson=19.6~24mohm GAP-CLOSE-PWR B 1D8V Iomax=5A OCP>10A TC14 ST220U4VDM-13 KEMET, NTD:7.8 (Q1) ESR=25mohm Iripple=2.2A 7.3*4.3*1.9 GAP-CLOSE-PWR G34 GAP-CLOSE-PWR G33 GAP-CLOSE-PWR G32 GAP-CLOSE-PWR G31 GAP-CLOSE-PWR G30 GAP-CLOSE-PWR G29 U93 AO4422 D D D D IND-4D7UH-16-GP G65 1D8V_S5 SB 0127 44 5130_OUT3U 44,56 5130_LL3 GAP-CLOSE-PWR G35 C848 SC10U35V0ZY-L D D D D 1D8V_PWR U92 AO4422 GAP-CLOSE-PWR DCBATOUT_5130 C847 SCD1U 1 B 44 5130_OUT2D 1D2V_VGA_S0 G66 G S S S 1D2V Iomax=5A OCP>10A Imax=6A DCR=30mOhm 7*7*3.0 D D D D IND-3D3UH-35 U87 AO4422 1D2V_S0 G20 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title GAP-CLOSE-PWR (Power Team) A TPS5130 1D2V/1D8V2D5V/ (2/2) Size A3 Document Number Date: Thursday, March 31, 2005 Rev -1 Bolsena Sheet 45 of 58 A B C D E 3D3V_G913_S5 3D3V_G913_S5 C965 U103 1 Output = 3.5V output=1.25(1+(Rx/Ry)) Ra change from 169K to 182K for output = 3.4827V output=1.235(1+(Ra/Rb)) 3D3V_AUX_S5 R135 3D3V_G913_S5 D54 2 182KR2F Ra 3D3V_AUX_LP2951_S5 1 C156 LP2951ACM_FB SC330P50V2KX DCBATOUT CH521S-30 CH521S-30 OUT INPUT SENSE FB SD 5V/TAP 100mA GND ERROR C157 DUMMY-C5 R136 100KR2F LP2951ACM C158 SC1U50V5ZY 78.10594.411 Rb 2 C154 SC1U10V3ZY C155 SCD1U U19 Ry D55 R762 10KR2F-U C967 2 G913C-U 4 3D3V_G913_SET OUT 3D3V_AUX_S5 SET SC1U10V3KX SHDN# GND IN C966 SC1U10V3KX 1 5V_S5 Rx R761 18KR2F SC22P50V2JN-1 DY 21,34 RSMRST#_KBC 3 SD 0303 5V_S5 C895 SC10U10V5ZY 78.10693.411 2D5V_S3 DY C902 SCD1U 1D25V_S3 Iomax=1.5A G95 GAP-CLOSE-PWR G97 GAP-CLOSE-PWR NC NC NC DY G96 GAP-CLOSE-PWR 1D25V_S3 G94 GAP-CLOSE-PWR GND GND TC27 SE100U10VM 2 C897 SCD1U VOUT C898 SC22U10V6ZY-L SB 0127 79.10711.4C1 2 R684 1KR2F VIN VREF VCNTL APL5331_1D25V_VREF 1D25V_LDO U96 Vo(cal.)=1.250V R683 1KR2F 2 C896 SC10U10V5ZY 78.10693.411 2 2D5V_S3 APL5331KAC-TR SO-8-P SB 0127 KEMET 100uF / 4V / B2 Size / NTD:5.615 Iripple=1.1A / ESR=70mohm Trace Length=1cm (500mils) Trace Width=8mils Trace Resistance>25mohm 1 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title 1D2V_S3 / 3D3V_AUX Size A3 (Power Team) A B C D Document Number Date: Thursday, March 31, 2005 Rev -1 Bolsena Sheet E 46 of 58 BT+ DCBATOUT For EMI C430 SCD1U G51 G52 R285 DUMMY-R3 SC 0308 C687 SC1U50V5ZY MAX1909_ACIN Close to MAX1909 pin 24 R283 D46 CCV CCI CCS MAX8725ETI C844 SCD1U16V3KX C842 SCD1U16V3KX 1 SC10U25V0KX SC10U25V6KX SC10U25V0KX 1 G115 GAP-CLOSE G116 GAP-CLOSE SB 0127 MAX1909_LDO R289 68KR2F R286 34,48 BAT_THERMAL MAX1909_CLS SC 0310 PKPRES# 0R0402-PAD R287 100KR2 90W ADAPTER 2 R673 63K4R3F 64.63425.651 Rx C431 BAT+SENSE 48 From Battery Connector MAX1909_LDO 2 8 D D D D GAP-CLOSE-PWR R674 49K9R2F C854 SC1U10V3KX GAP-CLOSE-PWR 17 16 15 CSIN BATT GND 18 V_REF :4.2235V ( 2.089V > AC DETECT MAX1909_PDL U35 S S S G 2 AO4407 D01R2512F-1-GP R518 1 AD+_TO_SYS 1 R513 100KR2F S S S G Rx U62 D D D D AD+ DY MAX1909_ACOK ISOURCE_MAX = (0.075/Rx)*(VCLS/VREF) TOTAL_POWER : Adapter=65W,Total_Power=58.5W C853 SC1U10V3KX Wistron Corporation R665 15KR2F 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C 2 TSLCX14MTC-L-U 1 34 AC_IN# R288 10KR2 U54C 14 3D3V_AUX_S5 Title SC 0302 CHARGER MAX8725 Size Custom (Power Team) Document Number Rev Bolsena Date: Thursday, March 31, 2005 -1 Sheet 47 of 58 A B C D E Adaptor in to generate DCBATOUT SB 0127 R8 0R5J-1 R729 0R5J-1 R730 0R5J-1 1 DOCK_AD+ AD_JK_1 D31 G48 GAP-CLOSE-PWR Dummy when 'USE EZ4' AD+ PZM24NB1 AD_JK_1 AD_JK C670 SCD1U AO4407 R502 ID = -10A/70deg Rds(ON) = 24mohm SO-8 1 DC-JACK75-U 1 22.10037.701 ME : 22.10037.701 Q2 PDTA124EU 100KR2 C7 SCD1U50V3ZY 2 Dummy when no EZ4 MH1 D D D D SBM1040CT-13 SCD1U50V3ZY AD+_2 C662 SCD1U50V3ZY 2 1 C661 DY U63 S S S G B R503 56KR3F C Q1 DTC124EUA-U1 G49 GAP-CLOSE-PWR 2 DC1 G50 GAP-CLOSE-PWR 2 D29 E G47 GAP-CLOSE-PWR 22 K 34 AD_OFF R9 1KR2 22 K 5V_AUX_S5 D45 BATTERY CONNECTOR D44 DY 83.00099.L01 BAV99-2 1 SC10P50V2JN-1 SC1000P50V2KX C849 SC1000P50V2KX SC10P50V2JN-1 1 SCD1U50V3ZY 2 SCD1U50V3ZY C852 ME : 20.80269.007 SD 0324 HTH GND LTH 11.25V (Low) VCC RESET#/RESET Turn Off LOW3_OFF 23 DY R266 15KR2F G680LT1 Output type: DY Open-Drain RESET# 1 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C DY Title SB AD/BATT CONN Size A3 R265 110KR2F Document Number Rev B C D -1 Bolsena Date: Thursday, March 31, 2005 A 20.80269.007 2 U31 HTH C851 SYN-CON7-9 EC11 Turn On DY HTH C850 EC12 12.78V (High) 1 DY C403 SCD1U10V2MX-1 R267 1MR2 BTSMCLK BTSMDATA MAX1999_LDO5 DCBATOUT L3# at 11.25V Put close to battery connector DY 1 Low3 Circuit : R672 0R0402-PAD SD 0324 83.00099.L01 BAV99-2 R671 27R3F R676 27R3F DY 34 BAT_SCL_5 34 BAT_SDA_5 BT+ 34,47 BAT_THERMAL 47 BAT+SENSE BAT1 3 CHANGE TO 20.80605.007 Sheet E 48 of 58 U70A 3D3V_S0 1 3D3V_S0 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 SCD1U16V C195 C193 C194 C192 C190 C188 C191 C189 C187 C185 C183 C181 C186 C184 C182 C180 C178 C176 C179 C177 C175 C173 C171 C169 C174 C172 C170 C168 C166 C164 C167 C165 PEG_TXP0_VGA PEG_TXP1_VGA PEG_TXP2_VGA PEG_TXP3_VGA PEG_TXP4_VGA PEG_TXP5_VGA PEG_TXP6_VGA PEG_TXP7_VGA PEG_TXP8_VGA PEG_TXP9_VGA PEG_TXP10_VGA PEG_TXP11_VGA PEG_TXP12_VGA PEG_TXP13_VGA PEG_TXP14_VGA PEG_TXP15_VGA R123 DUMMY-R2 R118 10KR2 AF26 PEG_TXN0_VGA AE26 AC25 PEG_TXN1_VGA AB25 AC27 PEG_TXN2_VGA AB27 AC26 PEG_TXN3_VGA AB26 Y25 PEG_TXN4_VGA W25 Y27 PEG_TXN5_VGA W27 Y26 PEG_TXN6_VGA W26 U25 PEG_TXN7_VGA T25 U27 PEG_TXN8_VGA T27 U26 PEG_TXN9_VGA T26 P25 PEG_TXN10_VGA N25 P27 PEG_TXN11_VGA N27 P26 PEG_TXN12_VGA N26 L25 PEG_TXN13_VGA K25 L27 PEG_TXN14_VGA K27 L26 PEG_TXN15_VGA K26 PCIE_TX0P PCIE_TX0N PCIE_TX1P PCIE_TX1N PCIE_TX2P PCIE_TX2N PCIE_TX3P PCIE_TX3N PCIE_TX4P PCIE_TX4N PCIE_TX5P PCIE_TX5N PCIE_TX6P PCIE_TX6N PCIE_TX7P PCIE_TX7N PCIE_TX8P PCIE_TX8N PCIE_TX9P PCIE_TX9N PCIE_TX10P PCIE_TX10N PCIE_TX11P PCIE_TX11N PCIE_TX12P PCIE_TX12N PCIE_TX13P PCIE_TX13N PCIE_TX14P PCIE_TX14N PCIE_TX15P PCIE_TX15N DVPCNTL_0 DVPCNTL_1 DVPCNTL_2 DVPCNTL_3 VREFG PCIE_REFCLKP PCIE_REFCLKN PCIE_CALP_VGA PCIE_CALN_VGA PCIE_CALI_VGA AC23 AB24 AB23 PCIE_CALRP PCIE_CALRN PCIE_CALI PCIE_TESTIN AE25 PCIE_TESTIN AD25 AD24 PERSTb PERSTb_MASK AH21 R2SET AK21 AJ22 AK22 Y_G C_R_PR COMP_B_PB 2 150R2F R551 150R2F R542 150R2F R541 715R3F 3D3V_S0 RN22 SRN10KJ AJ24 AK24 VGA_SMB_CLK VGA_SMB_DAT 54 VGA_SMB_CLK 54 VGA_SMB_DAT 13,17 EDID_CLK 13,17 EDID_DAT PWRGD_MASK RN23 SRN0-2-U 1 R553 R120 10KR2 10KR2 VGA_SSIN VGA_SSOUT XTALIN_M24 SB 0127 A TP75 R122 R77 R69 1KR2 1KR2 1KR2 TESTEN TP18 STERE0SYNC H2SYNC V2SYNC AG22 AG23 DDC3CLK DDC3DATA AJ23 AH24 SSIN SSOUT AH28 XTALIN AJ29 XTALOUT AH27 E8 B6 AF25 TESTEN TEST_YCLK TEST_MCLK PLLTEST AH25 STEREOSYNC TMDS 13 AG_RST# The PERSTB must deplay 4ms from M24 bug R101 57 DIS_LUMA 57 DIS_CRMA 57 DIS_COMP 10KR2 DAC1 R111 THERM SC 0308 150R2F 100R2F 10KR2F-U DAC2 R121 0R0402-PAD R119 DUMMY-R2 R97 R144 R110 CLK SS PWRGD_MASK STERE0SYNC B 1D2V_VGA_S0 3D3V_S0 1 1 1D8V_S0 0R0402-PAD 0R0402-PAD 0R0402-PAD 0R0402-PAD 2 2 TXOUT_L0N TXOUT_L0P TXOUT_L1N TXOUT_L1P TXOUT_L2N TXOUT_L2P TXOUT_L3N TXOUT_L3P TXCLK_LN TXCLK_LP TXOUT_U0N TXOUT_U0P TXOUT_U1N TXOUT_U1P TXOUT_U2N TXOUT_U2P TXOUT_U3N TXOUT_U3P TXCLK_UN TXCLK_UP DIGON BLON AE12 AG12 ATI_LCDVDD_ON BL_ON 13,34 TX0M TX0P TX1M TX1P TX2M TX2P TXCM TXCP AK13 AJ13 AJ14 AJ15 AK15 AK16 AJ12 AK12 TMDS_DIS_TX0TMDS_DIS_TX0+ TMDS_DIS_TX1TMDS_DIS_TX1+ TMDS_DIS_TX2TMDS_DIS_TX2+ TMDS_DIS_TXCTMDS_DIS_TXC+ DDC2CLK DDC2DATA AE13 AE14 HPD1 AF12 R G B AK27 AJ27 AJ26 HSYNC VSYNC AJ25 AK25 RSET AH26 DDC1DATA DDC1CLK AG25 AF24 GPIO_AUXWIN AG24 DPLUS DMINUS AF11 AE11 ATI_TXAOUT0ATI_TXAOUT0+ ATI_TXAOUT1ATI_TXAOUT1+ ATI_TXAOUT2ATI_TXAOUT2+ ATI_TXAOUT3TP74 ATI_TXAOUT3+ TP17 ATI_TXBOUT3ATI_TXBOUT3+ DEFAULT CAL_BG_BACKUP GPIO0 GPIO1 PCIE_MODE(1:0) GPIO(3:2) 00 CAL_OFF GPIO4 BYPASS_PLL GPIO5 ICOMP GPIO6 GPIO8 SB 0219 SB 0219 ROMIDCFG(3:0) GPIO(9,13:11) 0000 MULTIFUNC(1:0) LCDDATA(17:16) 00 VIP_DEVICE LCDDATA(20) DWNGR0 LCDDATA(21) (internal pull-down) C ATI Ref Datasheets(page 3-32) DOC.NO.:CHS-216M24-03 GPIO[0 13] are internal pull-down TMDS_DIS_TX0TMDS_DIS_TX1TMDS_DIS_TX2TMDS_DIS_TXC- R83 1 1 R95 R96 R98 R94 2 2 330R2 330R2 330R2 330R2 TMDS_DIS_TX0+ TMDS_DIS_TX1+ TMDS_DIS_TX2+ TMDS_DIS_TXC+ SC 0225 DVPDATA_2, 0 0 1 0 1 0 1 1 1 ATI_TXACLK- 54 ATI_TXACLK+ 54 ATI_TXBOUT0- 54 ATI_TXBOUT0+ 54 ATI_TXBOUT1- 54 ATI_TXBOUT1+ 54 ATI_TXBOUT2- 54 ATI_TXBOUT2+ 54 TP14 TP13 PIN PLL_CAL_FORCE_EN R84 100R2F 54 54 54 54 54 54 1, 64MB 64MB 64MB 64MB 128MB 128MB 128MB 128MB Hynix Samsung X brand Y brand Hynix Samsung X brand Y brand FOR M24 FOR M26 B ATI_TXBCLK- 54 ATI_TXBCLK+ 54 RN25 TMDS_DIS_TX0TMDS_DIS_TX0+ TMDS_DIS_TXC+ TMDS_DIS_TXC- 54 SRN0-1-U TMDS_DIS_TX2TMDS_DIS_TX2+ TMDS_DIS_TX1TMDS_DIS_TX1+ TMDS_EZ4_TX0TMDS_EZ4_TX0+ TMDS_EZ4_TXC+ TMDS_EZ4_TXC- 15,57 15,57 15,57 15,57 TMDS_EZ4_TX2TMDS_EZ4_TX2+ TMDS_EZ4_TX1TMDS_EZ4_TX1+ 15,57 15,57 15,57 15,57 RN24 SB 0213 SRN0-1-U DIS_DVI_DDC_C DIS_DVI_DDC_D 15 15 RN17 Place Near To EZPORT4 DVI_HPD 15 DIS_R 57 DIS_G 57 DIS_B 57 DIS_HS 16 DIS_VS 16 R552 GPIO_AUXWIN 54 470R2F SC 0228 DIS_CRT_DDC_D DIS_CRT_DDC_C 16 16 VGA_LOCAL_DP 23,54 VGA_LOCAL_DN 23,54 VGA_GPIO11 VGA_GPIO10 VGA_GPIO9 VGA_GPIO6 VGA_GPIO7 SRN10K-2 RN18 R93 100KR2 SC 0228 A SRN10K-2 Wistron Corporation R117 10KR2 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title Dummy when use ''M24' ATI M26 PCIE LVDS (1/3) Size A3 M26-P-1 (M24)71.00M24.C0U - (M26)71.0M26P.00U STRAPS VGA_VREFG AH15 AH16 AJ16 AJ17 AJ18 AK18 AJ20 AJ21 AK19 AJ19 AG16 AG17 AF16 AF17 AE18 AE19 AF19 AF20 AG19 AG20 D DEBUG_ACCESS TP6 TP5 C82 AF27 AE27 GFX_CLK GFX_CLK# M26 : HYNIX 128MB 1.8V,64MB 1.8V M24 : HYNIX 64MB 1.8V AJ10 DVPCNTL0_VGA AK10 DVPCNTL1_VGA AJ11 DVPCNTL2_VGA AH11 DVPCNTL3_VGA AG4 DUMMY-R2 3D3V_S0 SC 0225 SC 0308 R543 R532 R539 R540 R81 DUMMY-R2 Dummy when use ''M24' VGA_SDA1 VGA_SCL1 DUMMY-R2 C 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 DUMMY-R2 VGA_GPIO5 PEG_TXP0 PEG_TXN0 PEG_TXP1 PEG_TXN1 PEG_TXP2 PEG_TXN2 PEG_TXP3 PEG_TXN3 PEG_TXP4 PEG_TXN4 PEG_TXP5 PEG_TXN5 PEG_TXP6 PEG_TXN6 PEG_TXP7 PEG_TXN7 PEG_TXP8 PEG_TXN8 PEG_TXP9 PEG_TXN9 PEG_TXP10 PEG_TXN10 PEG_TXP11 PEG_TXN11 PEG_TXP12 PEG_TXN12 PEG_TXP13 PEG_TXN13 PEG_TXP14 PEG_TXN14 PEG_TXP15 PEG_TXN15 adjust SWING at 1.2v DUMMY-R2 VGA_GPIO3 R527 NO USE DVPDATA 100R2F R85 105R3F DVPDATA_0 R533 CHECK VRAM TYPE AND SIZE DVPDATA_1 R528 CHECK VRAM TYPE AND SIZE DVPDATA_2 R529 1KR2 CHECK VRAM TYPE AND SIZE VGA_GPIO2 R530 1 C53 SC270P50V AE10 AH6 AJ6 AK6 AH7 AK7 AJ7 AH8 AJ8 AH9 AJ9 AK9 AH10 AE6 AG6 AF6 AE7 AF7 AE8 AG8 AF8 AE9 AF9 AG10 AF10 3D3V_S0 3.3V MODE to 1.8V 1.8V MODE 2 C54 SCD01U16V2KX XTALIN_M24 DVOMODE DVPDATA_0 DVPDATA_1 DVPDATA_2 DVPDATA_3 DVPDATA_4 DVPDATA_5 DVPDATA_6 DVPDATA_7 DVPDATA_8 DVPDATA_9 DVPDATA_10 DVPDATA_11 DVPDATA_12 DVPDATA_13 DVPDATA_14 DPVDATA_15 DVPDATA_16 DVPDATA_17 DVPDATA_18 DVPDATA_19 DVPDATA_20 DVPDATA_21 DVPDATA_22 DVPDATA_23 SB 0215 for REVERSE LANE VGA_GPIO0 R531 10KR2 VGA_GPIO4 R526 10KR2 1 620R2F R86 180R2F R53 ORIGNAL P2779A-08TT USE W180-01 GEOMETRY C698 SCD1U P2779A-08ST 71.02779.00A 1 SC27P50V2JN C83 SC 0308 3D3V_SS_S0 P2779A_REF VGA_GPIO16 VDD REF MODOUT VSS 1 12 XIN/CLKIN XOUT PD# LF VGA_GPIO0 3D3V_S0 VGA_GPIO1 R758 10KR2 VGA_GPIO2 for EYE DIAGRAM SC 0219 VGA_GPIO3 VGA_GPIO4 VGA_GPIO5 VGA_GPIO6 VGA_GPIO7 VGA_GPIO8 VGA_GPIO9 TP10 MUST TO CHECK VGA_GPIO10 VGA_GPIO11 DVOMODE=VSS VGA_GPIO12 TP11 VGA_GPIO13 TP9 DVOMODE=VDDC VGA_ALERT# VGA_ALERT# 54 R82 GPIO_PWRCNTL 55 DVOMODE=GND 0R0402-PAD SC 0309 VGA_GPIO16 VGA_DVOMODE R92 0R0402-PAD SCD1U16V X-27MHZ-7-U P2779A_XO 1MR2 R55 AJ5 AH5 AJ4 AK4 AH4 AF4 AJ3 AK3 AH3 AJ2 AH2 AH1 AG3 AG1 AG2 AF3 AF2 R554 102R2F R549 102R2F R550 102R2F X1 GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO_PWRCNTL GPIO_MEMSSIN Part of DVO / EXT TMDS / GPIO P2779A_XI 1 U14 C58 SC27P50V2JN D R534 0R0805-PAD PCIE_RX0P PCIE_RX0N PCIE_RX1P PCIE_RX1N PCIE_RX2P PCIE_RX2N PCIE_RX3P PCIE_RX3N PCIE_RX4P PCIE_RX4N PCIE_RX5P PCIE_RX5N PCIE_RX6P PCIE_RX6N PCIE_RX7P PCIE_RX7N PCIE_RX8P PCIE_RX8N PCIE_RX9P PCIE_RX9N PCIE_RX10P PCIE_RX10N PCIE_RX11P PCIE_RX11N PCIE_RX12P PCIE_RX12N PCIE_RX13P PCIE_RX13N PCIE_RX14P PCIE_RX14N PCIE_RX15P PCIE_RX15N LVDS 3D3V_S0 12 PEG_TXP[15 0] 12 PEG_TXN[15 0] 12 PEG_RXP[15 0] 12 PEG_RXN[15 0] AH30 AG30 AG29 AF29 AE29 AE30 AD30 AD29 AC29 AB29 AB30 AA30 AA29 Y29 W29 W30 V30 V29 U29 T29 T30 R30 R29 P29 N29 N30 M30 M29 L29 K29 K30 J30 PCI EXPRESS Dummy when use UMA (WHOLE PAGE) PEG_RXP0 PEG_RXN0 PEG_RXP1 PEG_RXN1 PEG_RXP2 PEG_RXN2 PEG_RXP3 PEG_RXN3 PEG_RXP4 PEG_RXN4 PEG_RXP5 PEG_RXN5 PEG_RXP6 PEG_RXN6 PEG_RXP7 PEG_RXN7 PEG_RXP8 PEG_RXN8 PEG_RXP9 PEG_RXN9 PEG_RXP10 PEG_RXN10 PEG_RXP11 PEG_RXN11 PEG_RXP12 PEG_RXN12 PEG_RXP13 PEG_RXN13 PEG_RXP14 PEG_RXN14 PEG_RXP15 PEG_RXN15 Document Number Rev -1 Bolsena Date: Thursday, March 31, 2005 Sheet 49 of 58 C D LPVDD TPVDD AF13 AF14 TXVDDR#AF13 TXVDDR#AF14 SC 0308 SC1U10V3KX C151 C150 1 R114 0R0603-PAD SC1U10V3KX SC 0308 SC10U10V5ZY SC10U10V5ZY 2 C149 C148 R116 0R0603-PAD R115 0R0603-PAD AF21 AE20 A2VDD#AF21 A2VDD#AE20 1D8V_A2VDDQ_S0 AF23 A2VDDQ 1D8V_AVDD AH23 AVDD R112 21D8V_DDQ 0R0603-PAD AE23 AE22 VDD1DI VDD2DI SC 0308 1D8V_PVDD_S0 AK28 PVDD 1D8V_A2VDD_S0 1D8V_S0 A7 MPVDD LVSSR#AF18 LVSSR#AH17 LVSSR#AG15 LVSSR#AG18 AF18 AH17 AG15 AG18 LPVSS TPVSS AH18 AH12 TXVSSR#AH12 TXVSSR#AG13 TXVSSR#AG14 AH14 AG13 AG14 A2VSSN#AH20 A2VSSN#AG21 AH20 AG21 A2VSSQ AF22 AVSSN AH22 VSS1DI VSS2DI AE24 AE21 PVSS AJ28 MPVSS M26-P-1 (M24)71.00M24.C0U - (M26)71.0M26P.00U 1 1 1 1 1 SCD01U16V2KX SCD01U16V2KX SCD01U16V2KX SCD01U16V2KX SCD01U16V2KX SCD01U16V2KX SCD01U16V2KX SC1U10V3KX SC1U10V3KX ST100U6D3VDM-5 SCD01U16V2KX A6 DIODE SUPPLIES POWER TO VDDC RAIL WHILE VDDC REGULATOR STABALIZES DURING POWER ON C109 SC1U10V3KX C102 SC1U10V3KX C96 SC1U10V3KX 1 1 1 1 SCD01U16V2KX SC330P50V2KX SC10U10V5ZY 2 1 C140 C141C718C139 SC 0308 C146 C147C720 SCD01U16V2KX SC1U10V3KX C719 SCD01U16V2KX 2 AD22 DIODE SUPPLIES POWER TO VDDC RAIL WHILE VDDC REGULATOR STABALIZES DURING POWER ON R557 0R0603-PAD SC 0308 PCIE_PVDD_12 M22 Power 150mA + margin (transition, 4us duration) andUP 90mA + margin (continuous) Squence 3D3_VDDR3 T1 < 1mS 3D3_VDDR4 T2 < 1mS T3 < 1uS 2D5_VDDR1 T4 < 100nS 1D2_VDDC 1D8V_S0 C142 PCIE_VDDR_12 T5 < 100nS PCIE_PVDD_12 T6 < 1uS C145 C143 C144 SC10U10V5ZY C107 R113 0R0603-PAD SC330P50V2KX F19 M6 R558 0R0603-PAD 1D2V_VGA_PVDD AVSSQ VSSRH0 VSSRH1 SCD01U16V2KX 1 SCD01U16V2KX SCD01U16V2KX SC10U10V5ZY SCD01U16V2KX 1 C196 C197 VDDRH0 VDDRH1 C714 C715 2 C721 SCD01U16V2KX F18 N6 SC1U10V3KX SC10U10V5ZY 2 SC 0308 C103 1D2V_VGA_S0 1D2V_VGA_VDDR SCD01U16V2KX AH19 AH13 C99 PCIE_VDDR_12 1.6A + margin (transition, 4us duration) and 1.1A + margin (continuous) SC 0308 SCD01U16V2KX LVDDR_25#AE16 LVDDR_25#AE17 LVDDR_18#AF15 LVDDR_18#AE15 SC10U10V5ZY D9 D13 D19 D25 E4 T4 AB4 C81 1D8V_VGA_PVDD 1D8V_TVDD_S0 C119 C111 1 R545 0R0603-PAD R67 0R0603-PAD NC#D9 NC#D13 NC#D19 NC#D25 NC#E4 NC#T4 NC#AB4 1D8V_S0 2D5V_S0 U23 T23 V23 W23 C80 SCD01U16V2KX SC100P50V2JN 2 SC1U10V3KX 1 C118 C117 SC 0308 AE16 AE17 AF15 AE15 C100 C106 C97 R80 0R0603-PAD 1 R100 0R0603-PAD SC100P50V2JN C116 PCIE_PVDD_18#U23 PCIE_PVDD_18#T23 PCIE_PVDD_18#V23 PCIE_PVDD_18#W23 3D3V_VDDR4 SC 0308 N24 N23 P23 SC 0308 C722 C752 SC1U10V3KX SC1U10V3KX SC330P50V2KX 1 R99 0R0603-PAD C105 C110 C98 C137 R559 0R0603-PAD 1D8V_S0 PCIE_PVDD_12#N24 PCIE_PVDD_12#N23 PCIE_PVDD_12#P23 3D3V_S0 3D3V_VDDR3 SB 0201 DY 1D5V_VGA_S0 SCD01U16V2KX C115 AG26 AK29 AJ30 AG28 AG27 TC20 C112 SB 0R3-U PCIE_VDDR_12#AG26 PCIE_VDDR_12#AK29 PCIE_VDDR_12#AJ30 PCIE_VDDR_12#AG29 PCIE_VDDR_12#AH29 C114 DY R544 CHANGE TO 74.05308.E31 AG7 AD9 AC9 AC10 AD10 C113 SSM5818SL SC1U10V3KX 2D5V_S0 VDDR4#AG7 VDDR4#AD9 VDDR4#AC9 VDDR4#AC10 VDDR4#AD10 C101 DY 3D3V_S0 SSM5818SL VGA_CORE_S0 D33 APL5308-15AC-TR VDDR3#AD7 VDDR3#AD19 VDDR3#AD21 VDDR3#AC22 VDDR3#AC8 VDDR3#AC21 VDDR3#AC19 AD7 AD19 AD21 AC22 AC8 AC21 AC19 3D3V_S0 DY SC1U10V3KX 2 SC1U10V3KX DY 0R3-U DY P8 Y8 AC11 AC20 H20 H11 M23 Y23 SC10U10V5ZY C121 VDD15#P8 VDD15#Y8 VDD15#AC11 VDD15#AC20 VDD15#H20 VDD15#H11 VDD15#M23 VDD15#Y23 C104 1 R546 AC13 AD13 AD15 AC15 AC17 I/O POWER VOUT VIN GND SCD1U16V 2D5V_2D8V_LVDDR_S0 C122 2D8V_S0 U17 DY 3D3V_S0 VDDC#AC13 VDDC#AD13 VDDC#AD15 VDDC#AC15 VDDC#AC17 2D8V_S0 VDDR1#T7 VDDR1#R4 VDDR1#R1 VDDR1#N8 VDDR1#N7 VDDR1#M4 VDDR1#L8 VDDR1#K23 VDDR1#K24 VDDR1#N4 VDDR1#J8 VDDR1#J7 VDDR1#J4 VDDR1#J1 VDDR1#H10 VDDR1#H13 VDDR1#H15 VDDR1#H17 VDDR1#T8 VDDR1#V4 VDDR1#V7 VDDR1#V8 VDDR1#AA1 VDDR1#AA4 VDDR1#AA7 VDDR1#AA8 VDDR1#A3 VDDR1#A9 VDDR1#A15 VDDR1#A21 VDDR1#A28 VDDR1#B1 VDDR1#B30 VDDR1#D26 VDDR1#D23 VDDR1#D20 VDDR1#D17 VDDR1#D14 VDDR1#D11 VDDR1#D8 VDDR1#D5 VDDR1#E27 VDDR1#F4 VDDR1#G7 VDDR1#G10 VDDR1#G13 VDDR1#G15 VDDR1#G19 VDDR1#G22 VDDR1#G27 VDDR1#H22 VDDR1#H19 VDDR1#AD4 VDDR1#L23 2 ST100U6D3VDM-5 TC2 T7 R4 R1 N8 N7 M4 L8 K23 K24 N4 J8 J7 J4 J1 H10 H13 H15 H17 T8 V4 V7 V8 AA1 AA4 AA7 AA8 A3 A9 A15 A21 A28 B1 B30 D26 D23 D20 D17 D14 D11 D8 D5 E27 F4 G7 G10 G13 G15 G19 G22 G27 H22 H19 AD4 L23 Part of 2 SCD01U16V2KX C76 C135 SC10U10V5ZY SC1U10V3KX C74 SC1U10V3KX C95 SCD01U16V2KX 1 SCD01U16V2KX SCD01U16V2KX 1 C79 SC1U10V3KX C77 2 SCD01U16V2KX C136 C78 SCD01U16V2KX C92 C75 C94 SCD01U16V2KX 1 SCD01U16V2KX C93 current of power to VDDC on M26 is up to 10A + margin (25% or more) U70D 1D8V_S0 E D32 SC1U10V3KX B SC10U10V5ZY A Dummy when use UMA (WHOLE PAGE) SC 0308 T7 < 100nS VDD_15 PCIE_PVDD_18 PCIE_PVDDR_18 800mA + margin (transition, 4us duration) and 330mA + margin (continuous) ADD ASIC DECOUPLING FOR ALL POWER AS REQUIRED PLACED CLOSE TO THE POWER/GND PINS WITH AS MANY AS POSSIBLE PLACED UNDER THE ASIC Wistron Corporation 1D8V_MPVDD_S0 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C SC 0308 Title ATI M26 POWER (2/3) Size A3 Document Number Date: Thursday, March 31, 2005 Rev -1 Bolsena Sheet 50 of 58 RASA# A19 CASA# E18 CASA# 52 WEA# E19 WEA# 52 CSA0# E20 CSA1# F20 CKEA B19 CKEA R90 10KR2 CKEB R78 10KR2 RASA# 52 CSA#0 52 CSA#1 CSA#1 52 CKEA 52 B21 C20 CLKA0 52 CLKA#0 52 CLKA1 CLKA1# C18 A18 CLKA1 52 CLKA#1 52 1D8V_S0 SB 0201 CLKA0 CLKA0# ATI_MVREFS D30 DIMA_0 B13 DIMA_1 1D8V_S0 R71 100R2F TP16 TP12 SB 0201 C73 SCD1U16V DIMA_0 DIMA_1 B8 ATI_MVREFD MVREFS B7 MVREFD R70 100R2F R68 100R2F 2 R89 100R2F C91 SCD1U16V As close to CHIP as possible DQMB#0 DQMB#1 DQMB#2 DQMB#3 DQMB#4 DQMB#5 DQMB#6 DQMB#7 E6 B2 J5 G3 W6 W2 AC6 AD2 DQMB#0 DQMB#1 DQMB#2 DQMB#3 DQMB#4 DQMB#5 DQMB#6 DQMB#7 QSB0 QSB1 QSB2 QSB3 QSB4 QSB5 QSB6 QSB7 F6 B3 K6 G1 V5 W1 AC5 AD1 QSB0 QSB1 QSB2 QSB3 QSB4 QSB5 QSB6 QSB7 MAB[13 0] 53 VGA_CORE_S0 U70F QSB[7 0] 53 RASB# R2 RASB# 53 CASB# T5 CASB# 53 WEB# 53 WEB# T6 CSB0# R5 CSB1# R6 CSB#0 53 CSB#1 CKEB R3 CKEB 53 N1 N2 CLKB0 53 CLKB#0 53 CLKB1 CLKB1# T2 T3 CLKB1 53 CLKB#1 53 DIMB_0 DIMB_1 E3 AA3 TP3 TP4 TPAD30 TPAD30 ROMCS# AF5 TP7 TPAD30 C6 C7 MEMTEST C8 VGA_CORE_S0 R91 SC 0308 M22,24,26P :Not connected MEMORY CHANNEL B M24 use 45ohm 1% M26 use 240ohm 1% R75 45R2F R76 240R2F W16 M15 R19 T12 C108 SC330P50V2KX 1D8V_S0 R74 When use M22/24P DY 10KR2 R73 M26-P-1 (M24)71.00M24.C0U - (M26)71.0M26P.00U M16 N16 N15 P15 P16 R18 R17 R16 R15 R14 R13 R12 T13 T14 T15 W15 V16 V15 U15 U16 T19 T18 T17 T16 VDDC#P17Part of VSS#M16 VDDC#P18 VSS#N16 VDDC#P19 VSS#N15 VDDC#U12 VSS#P15 VDDC#U13 VSS#P16 VDDC#U14 VSS#R18 VDDC#U17 VSS#R17 VDDC#U18 VSS#R16 VDDC#U19 VSS#R15 VDDC#V19 VSS#R14 VDDC#V18 VSS#R13 VDDC#V17 VSS#R12 VDDC#V14 VSS#T13 VDDC#V13 VSS#T14 VDDC#V12 VSS#T15 VDDC#N18 VSS#W15 VDDC#N17 VSS#V16 VDDC#N14 VSS#V15 VDDC#W17 VSS#U15 VDDC#W18 VSS#U16 VDDC#W12 VSS#T19 VDDC#W13 VSS#T18 VDDC#W14 VSS#T17 VDDC#N13 VSS#T16 VDDC#N19 VDDC#M19 VDDC#M18 VDDC#M12 VDDC#N12 VDDC#M13 VDDC#M14 VDDC1#W16 VDDC#P12 VDDC1#M15 VDDC#P13 VDDC1#R19 VDDC#P14 VDDC1#T12 VDDC#M17 VDDC#W19 M26-P-1 (M24)71.00M24.C0U - (M26)71.0M26P.00U VGA_CORE_VDDCI 0R0603-PAD CSB#1 53 CLKB0 CLKB0# MEMVMODE_0 MEMVMODE_1 P17 P18 P19 U12 U13 U14 U17 U18 U19 V19 V18 V17 V14 V13 V12 N18 N17 N14 W17 W18 W12 W13 W14 N13 N19 M19 M18 M12 N12 M13 M14 P12 P13 P14 M17 W19 DQMB#[7 0] 53 R72 10KR2 PIN C6 C7 1.8V = PD PU 2.5V = PU PD 10KR2 R51 10KR2 DY Dummy when use ''M26' *When use M26, pin C6 = GPIO_17, C7 = NC M22,24,26P :Not connected MEMORY CHANNEL A MAB0 MAB1 MAB2 MAB3 MAB4 MAB5 MAB6 MAB7 MAB8 MAB9 MAB10 MAB11 MAB12 MAB13 CENTER ARRAY J27 F30 F24 B27 E16 B16 B11 F10 QSA[7 0] 52 N5 M1 M3 L3 L2 M2 M5 P6 N3 K2 K3 J2 P5 P3 P2 MAB0 MAB1 MAB2 MAB3 MAB4 MAB5 MAB6 MAB7 MAB8 MAB9 MAB10 MAB11 MAB12 MAB13 MAB14 Part of QSA0 QSA1 QSA2 QSA3 QSA4 QSA5 QSA6 QSA7 QSA0 QSA1 QSA2 QSA3 QSA4 QSA5 QSA6 QSA7 DQMA#[7 0] 52 DQB0 DQB1 DQB2 DQB3 DQB4 DQB5 DQB6 DQB7 DQB8 DQB9 DQB10 DQB11 DQB12 DQB13 DQB14 DQB15 DQB16 DQB17 DQB18 DQB19 DQB20 DQB21 DQB22 DQB23 DQB24 DQB25 DQB26 DQB27 DQB28 DQB29 DQB30 DQB31 DQB32 DQB33 DQB34 DQB35 DQB36 DQB37 DQB38 DQB39 DQB40 DQB41 DQB42 DQB43 DQB44 DQB45 DQB46 DQB47 DQB48 DQB49 DQB50 DQB51 DQB52 DQB53 DQB54 DQB55 DQB56 DQB57 DQB58 DQB59 DQB60 DQB61 DQB62 DQB63 DQMA#0 DQMA#1 DQMA#2 DQMA#3 DQMA#4 DQMA#5 DQMA#6 DQMA#7 D7 F7 E7 G6 G5 F5 E5 C4 B5 C5 A4 B4 C2 D3 D1 D2 G4 H6 H5 J6 K5 K4 L6 L5 G2 F3 H2 E2 F2 J3 F1 H3 U6 U5 U3 V6 W5 W4 Y6 Y5 U2 V2 V1 V3 W3 Y2 Y3 AA2 AA6 AA5 AB6 AB5 AD6 AD5 AE5 AE4 AB2 AB3 AC2 AC3 AD3 AE1 AE2 AE3 DQMA#0 DQMA#1 DQMA#2 DQMA#3 DQMA#4 DQMA#5 DQMA#6 DQMA#7 J25 F29 E25 A27 F15 C15 C11 E11 MDB0 MDB1 MDB2 MDB3 MDB4 MDB5 MDB6 MDB7 MDB8 MDB9 MDB10 MDB11 MDB12 MDB13 MDB14 MDB15 MDB16 MDB17 MDB18 MDB19 MDB20 MDB21 MDB22 MDB23 MDB24 MDB25 MDB26 MDB27 MDB28 MDB29 MDB30 MDB31 MDB32 MDB33 MDB34 MDB35 MDB36 MDB37 MDB38 MDB39 MDB40 MDB41 MDB42 MDB43 MDB44 MDB45 MDB46 MDB47 MDB48 MDB49 MDB50 MDB51 MDB52 MDB53 MDB54 MDB55 MDB56 MDB57 MDB58 MDB59 MDB60 MDB61 MDB62 MDB63 MAA0 MAA1 MAA2 MAA3 MAA4 MAA5 MAA6 MAA7 MAA8 MAA9 MAA10 MAA11 MAA12 MAA13 M26-P-1 (M24)71.00M24.C0U - (M26)71.0M26P.00U E E22 B22 B23 B24 C23 C22 F22 F21 C21 A24 C24 A25 E21 B20 C19 MAA[13 0] 52 MAA0 MAA1 MAA2 MAA3 MAA4 MAA5 MAA6 MAA7 MAA8 MAA9 MAA10 MAA11 MAA12 MAA13 MAA14 Part of DQA0 DQA1 DQA2 DQA3 DQA4 DQA5 DQA6 DQA7 DQA8 DQA9 DQA10 DQA11 DQA12 DQA13 DQA14 DQA15 DQA16 DQA17 DQA18 DQA19 DQA20 DQA21 DQA22 DQA23 DQA24 DQA25 DQA26 DQA27 DQA28 DQA29 DQA30 DQA31 DQA32 DQA33 DQA34 DQA35 DQA36 DQA37 DQA38 DQA39 DQA40 DQA41 DQA42 DQA43 DQA44 DQA45 DQA46 DQA47 DQA48 DQA49 DQA50 DQA51 DQA52 DQA53 DQA54 DQA55 DQA56 DQA57 DQA58 DQA59 DQA60 DQA61 DQA62 DQA63 MEMORY INTERFACE A H28 H29 J28 J29 J26 H25 H26 G26 G30 D29 D28 E28 E29 G29 G28 F28 G25 F26 E26 F25 E24 F23 E23 D22 B29 C29 C25 C27 B28 B25 C26 B26 F17 E17 D16 F16 E15 F14 E14 F13 C17 B18 B17 B15 C13 B14 C14 C16 A13 A12 C12 B12 C10 C9 B9 B10 E13 E12 E10 F12 F11 E9 F9 F8 MEMORY INTERFACE B U70B MDA0 MDA1 MDA2 MDA3 MDA4 MDA5 MDA6 MDA7 MDA8 MDA9 MDA10 MDA11 MDA12 MDA13 MDA14 MDA15 MDA16 MDA17 MDA18 MDA19 MDA20 MDA21 MDA22 MDA23 MDA24 MDA25 MDA26 MDA27 MDA28 MDA29 MDA30 MDA31 MDA32 MDA33 MDA34 MDA35 MDA36 MDA37 MDA38 MDA39 MDA40 MDA41 MDA42 MDA43 MDA44 MDA45 MDA46 MDA47 MDA48 MDA49 MDA50 MDA51 MDA52 MDA53 MDA54 MDA55 MDA56 MDA57 MDA58 MDA59 MDA60 MDA61 MDA62 MDA63 D U70C 52 MDA[63 0] C 53 MDB[63 0] B A Dummy when use UMA (WHOLE PAGE) K28 L28 M27 M26 M24 M25 M28 P28 N28 R25 R23 R24 R26 R27 R28 T28 T24 U28 V24 V26 V27 V25 V28 Y28 W24 W28 AA26 AA27 AA23 AA24 AA25 AA28 AB28 AC28 AD28 AD26 AD27 AE28 AF28 AH29 CORE GND Part of VSS#U4 VSS#U8 VSS#W7 VSS#W8 VSS#Y4 VSS#AB8 VSS#AB7 VSS#AB1 VSS#AC4 VSS#AC12 VSS#AC14 VSS#AD16 VSS#AC16 VSS#AC18 VSS#AD18 VSS#AK2 VSS#AJ1 U70E PCIE_VSS#K28 PCIE_VSS#L28 PCIE_VSS#M27 PCIE_VSS#M26 PCIE_VSS#M24 PCIE_VSS#M25 PCIE_VSS#M28 PCIE_VSS#P28 PCIE_VSS#N28 PCIE_VSS#R25 PCIE_VSS#R23 PCIE_VSS#R24 PCIE_VSS#R26 PCIE_VSS#R27 PCIE_VSS#R28 PCIE_VSS#T28 PCIE_VSS#T24 PCIE_VSS#U28 PCIE_VSS#V24 PCIE_VSS#V26 PCIE_VSS#V27 PCIE_VSS#V25 PCIE_VSS#V28 PCIE_VSS#Y28 PCIE_VSS#W23 PCIE_VSS#W28 PCIE_VSS#AA26 PCIE_VSS#AA27 PCIE_VSS#AA23 PCIE_VSS#AA24 PCIE_VSS#AA25 PCIE_VSS#AA28 PCIE_VSS#AB28 PCIE_VSS#AC28 PCIE_VSS#AD28 PCIE_VSS#AD26 PCIE_VSS#AD27 PCIE_VSS#AE28 PCIE_VSS#AF28 PCIE_VSS#AH29 U4 U8 W7 W8 Y4 AB8 AB7 AB1 AC4 AC12 AC14 AD16 AC16 AC18 AD18 AK2 AJ1 Dummy when use ''M24' MVDDQ= 1.8v/ 2.5v VDDR1 1.8V MEMVMODE_0 GND MEMVMODE_1 +VDDC_CT SB 0127 2.5V +VDDC_CT 2.8V +VDDC_CT GND +VDDC_CT VSS#R7 VSS#P4 VSS#M7 VSS#M8 VSS#L4 VSS#K1 VSS#K7 VSS#K8 VSS#R8 VSS#T1 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C R7 P4 M7 M8 L4 K1 K7 K8 R8 T1 VSS#AD12 VSS#AG5 VSS#AG9 VSS#AG11 AD12 AG5 AG9 AG11 VSS#F27 VSS#G9 VSS#G12 VSS#G16 VSS#G18 VSS#G21 VSS#G24 VSS#H27 VSS#H23 VSS#H21 VSS#H18 VSS#H16 VSS#H14 VSS#H12 VSS#H9 VSS#H8 VSS#H4 VSS#J23 VSS#J24 F27 G9 G12 G16 G18 G21 G24 H27 H23 H21 H18 H16 H14 H12 H9 H8 H4 J23 J24 A2 A10 A16 A22 A29 C1 C3 C28 C30 D27 D24 D21 D18 D15 D12 D10 D6 D4 VSS#A2 VSS#A10 VSS#A16 VSS#A22 VSS#A29 VSS#C1 VSS#C3 VSS#C28 VSS#C30 VSS#D27 VSS#D24 VSS#D21 VSS#D18 VSS#D15 VSS#D12 VSS#D10 VSS#D6 VSS#D4 SB 0127 Title ATI M26 MEM (3/3) Size A3 Document Number Date: Thursday, March 31, 2005 Rev -1 Bolsena Sheet 51 of 58 Dummy when use UMA (WHOLE PAGE) 1D8V_S0 SB 0201 SB 0201 MCL/DSF C65 SCD1U16V DQMA#2 QSA2 H12 H13 H12 H13 DM1 DQS1 HY5DS573222F-28 HY5DS573222F-28 (M24 HYNIX 64MB) 72.52832.F0U - (M26 HYNIX 128MB) 72.55732.B0U (M24 HYNIX 64MB) 72.52832.F0U - (M26 HYNIX 128MB) 72.55732.B0U of of U69D U71D G3 K3 J3 F3 J2 G2 F2 K2 DQ18 DQ23 DQ20 DQ16 DQ21 DQ19 DQ17 DQ22 H3 H2 DM2 DQS2 MDA37 MDA35 MDA34 MDA39 MDA33 MDA36 MDA38 MDA32 G3 K3 J3 F3 J2 G2 F2 K2 DQ18 DQ23 DQ20 DQ16 DQ21 DQ19 DQ17 DQ22 H3 H2 DM2 DQS2 M13 VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL MCL/DSF HY5DS573222F-28 VREF SC10U10V5ZY E5 E7 E8 E10 K6 K7 K8 K9 L5 L10 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS B4 B11 D4 D5 D6 D9 D10 D11 E6 E9 F5 F10 G5 G10 H5 H10 J5 J10 K5 K10 C SB 0201 1D8V_S0 N13 R520 1KR2F C689 SCD1U16V MDA6 MDA2 MDA0 MDA7 MDA1 MDA4 MDA5 MDA3 DQMA#6 QSA6 DM1 DQS1 F6 F7 F8 F9 G6 G7 G8 G9 H6 H7 H8 H9 J6 J7 J8 J9 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ C702 R64 1 HY5DS573222F-28 HY5DS573222F-28 (M24 HYNIX 64MB) 72.52832.F0U - (M26 HYNIX 128MB) 72.55732.B0U of (M24 HYNIX 64MB) 72.52832.F0U - (M26 HYNIX 128MB) 72.55732.B0U U69C of U71C MDA49 K13 MDA21 K13 MDA53 G13 DQ8 MDA18 G13 DQ8 MDA54 G12 DQ12 MDA17 G12 DQ12 MDA50 J13 DQ13 MDA22 J13 DQ13 MDA52 F13 DQ10 DQ10 MDA19 F13 MDA48 K12 DQ14 MDA23 K12 DQ14 MDA55 F12 DQ9 MDA16 F12 DQ9 MDA51 J12 DQ15 DQ11 MDA20 J12 DQ15 DQ11 CKE CLK CLK# 60D4R2F R49 2 51 CKEA 10R3 N12 VDDRA_CLK1+ M11 VDDRA_CLK1- M12 10R3 60D4R2F R66 R65 CLOSE TO MEM !! SC10U10V5ZY 2 SCD01U16V2KX SC330P50V2KX 1 DM0 DQS0 51 CLKA1 51 CLKA#1 C692 DQMA#0 QSA0 DQMA#4 QSA4 HY5DS573222F-28 HY5DS573222F-28 (M24 HYNIX 64MB) 72.52832.F0U - (M26 HYNIX 128MB) 72.55732.B0U (M24 HYNIX 64MB) 72.52832.F0U - (M26 HYNIX 128MB) 72.55732.B0U U71E of U69E of MDA26 MDA31 MDA30 MDA24 MDA27 MDA25 MDA29 MDA28 SB 0201 1D8V_S0 D12 D13 E13 C9 B10 B8 C13 B9 DQ26 DQ25 DQ24 DQ30 DQ28 DQ31 DQ27 DQ29 B12 B13 DM3 DQS3 MDA58 MDA63 MDA61 MDA56 MDA59 MDA57 MDA62 MDA60 D12 D13 E13 C9 B10 B8 C13 B9 DQ26 DQ25 DQ24 DQ30 DQ28 DQ31 DQ27 DQ29 B12 B13 DM3 DQS3 B VDDR_VREF2 (M24 HYNIX 64MB) 72.52832.F0U - (M26 HYNIX 128MB) 72.55732.B0U N13 B3 B2 DQMA#5 QSA5 BA0 BA1 NC#M10 MAA12 MAA13 D C688 SCD1U16V R519 1KR2F VREF DQ3 DQ1 DQ2 DQ0 DQ6 DQ5 DQ4 DQ7 C3 C5 C7 C8 C10 C12 E3 E12 F4 F11 G4 G11 J4 J11 K4 K11 E5 E7 E8 E10 K6 K7 K8 K9 L5 L10 1 1 SC330P50V2KX VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS DM0 DQS0 B5 C6 B6 B7 D2 D3 C2 E2 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ SB 0201 1D8V_S0 Layout trace 20 mil R547 1KR2F C708 SCD1U16V DQMA#3 QSA3 DQMA#7 QSA7 HY5DS573222F-28 NC#C4 NC#C11 NC#H4 NC#H11 NC#L12 NC#L13 NC#M3 NC#N3 M13 VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL C4 C11 H4 H11 L12 L13 M3 N3 F6 C132 F7 SCD1U16V F8 F9 G6 G7 G8 G9 H6 H7 H8 H9 J6 J7 J8 J9 B3 B2 N4 M5 M10 of U69B MDA45 MDA46 MDA43 MDA44 MDA42 MDA40 MDA47 MDA41 A0 A1 A2 A3 A4 A5 A6 A7 A8/AP A9 A10 A11 NC#L9 D7 D8 E4 E11 L4 L7 L8 L11 BC751_1 B B4 B11 D4 D5 D6 D9 D10 D11 E6 E9 F5 F10 G5 G10 H5 H10 J5 J10 K5 K10 C711 DQ3 DQ1 DQ2 DQ0 DQ6 DQ5 DQ4 DQ7 N5 N6 M6 N7 N8 M9 N9 N10 N11 M8 L6 M7 L9 NC#C4 NC#C11 NC#H4 NC#H11 NC#L12 NC#L13 NC#M3 NC#N3 60D4R2F R108 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ DQMA#1 QSA1 SB 0201 C703 of U71B B5 C6 B6 B7 D2 D3 C2 E2 MAA0 MAA1 MAA2 MAA3 MAA4 MAA5 MAA6 MAA7 MAA8 MAA9 MAA10 MAA11 VDD VDD VDD VDD VDD VDD VDD VDD C4 C11 H4 H11 L12 L13 M3 N3 CKE CLK CLK# 2 N12 VDDRA_CLK0+ M11 VDDRA_CLK0- M12 60D4R2F R88 BA0 BA1 NC#M10 51 CKEA 1 R107 R109 10R3 10R3 CLOSE TO MEM !! 51 CLKA0 51 CLKA#0 N4 M5 M10 C3 C5 C7 C8 C10 C12 E3 E12 F4 F11 G4 G11 J4 J11 K4 K11 C69 C71 SC330P50V2KX SCD01U16V2KX RAS# CAS# WE# CS# NC#M4 MAA12 MAA13 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ 1D8V_S0 SC10U10V5ZY C D7 D8 E4 E11 L4 L7 L8 L11 A0 A1 A2 A3 A4 A5 A6 A7 A8/AP A9 A10 A11 NC#L9 VDD VDD VDD VDD VDD VDD VDD VDD MAA0 N5 MAA1 N6 MAA2 M6 MAA3 N7 MAA4 N8 MAA5 M9 MAA6 N9 MAA7 N10 MAA8 N11 MAA9 M8 MAA10 L6 MAA11 M7 L9 C162 MDA12 MDA11 MDA9 MDA10 MDA13 MDA8 MDA15 MDA14 RAS# CAS# WE# CS# NC#M4 C701 M2 L2 L3 N2 M4 BC752_1 M2 L2 L3 N2 M4 C138 of U71A 51 RASA# 51 CASA# 51 WEA# 51 CSA#0 51 CSA#1 1 SC330P50V2KX C713 SC330P50V2KX C712 SC330P50V2KX 2 C163 SC330P50V2KX C131 SC330P50V2KX C66 SC330P50V2KX 1 1 D RASA# CASA# WEA# CSA#0 CSA#1 SC10U10V5ZY C133 SCD1U16V C72 SCD1U16V 1 51 MAA[13 0] C705 51 DQMA#[7 0] SCD01U16V2KX C690 SCD1U16V C704 SCD1U16V 1 C691 SCD1U16V 51 QSA[7 0] C134 of U69A 51 MDA[63 0] C41 SCD1U16V C67 SCD1U16V 2 C68 SCD1U16V 1 1 C70 SCD1U16V 2 All dampings in this page must near the VRAM C90 SCD1U16V 1D8V_S0 1 C707 SCD1U16V A R548 1KR2F Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C 2 A CLOSE TO MEM HY5DS573222F-28 HY5DS573222F-28 (M24 HYNIX 64MB) 72.52832.F0U - (M26 HYNIX 128MB) 72.55732.B0U (M24 HYNIX 64MB) 72.52832.F0U - (M26 HYNIX 128MB) 72.55732.B0U VDDR_VREF1 (M24 HYNIX 64MB) 72.52832.F0U - (M26 HYNIX 128MB) 72.55732.B0U Title ATI VRAM (1/2) Layout trace 20 mil Size A3 Document Number Rev Date: Thursday, March 31, 2005 -1 Bolsena Sheet 52 of 58 1D8V_S0 51 MDB[63 0] MCL/DSF VREF DM0 DQS0 BA0 BA1 NC#M10 51 CKEB 51 CLKB1 51 CLKB#1 2 R31 R32 10R3 10R3 N12 VDDRC_CLK1+M11 VDDRC_CLK1- M12 CKE CLK CLK# MDB14 MDB9 MDB11 MDB13 MDB10 MDB15 MDB12 MDB8 DQMB#1 QSB1 DQ8 DQ12 DQ13 DQ10 DQ14 DQ9 DQ15 DQ11 1 K13 G13 G12 J13 F13 K12 F12 J12 F6 VSS_THERMAL F7 VSS_THERMAL F8 VSS_THERMAL F9 VSS_THERMAL G6 VSS_THERMAL DQMB#7 H12 DM1 H12 DM1 G7 VSS_THERMAL QSB7 H13 DQS1 H13 DQS1 G8 VSS_THERMAL G9 VSS_THERMAL H6 VSS_THERMAL H7 VSS_THERMAL HY5DS573222F-28 HY5DS573222F-28 H8 VSS_THERMAL (M24 HYNIX 64MB) 72.52832.F0U - (M26 HYNIX 128MB) (M24 72.55732.B0U HYNIX 64MB) 72.52832.F0U - (M26 HYNIX 128MB) 72.55732.B0U of of U64D U65D H9 VSS_THERMAL J6 VSS_THERMAL MDB43 G3 DQ18 G3 DQ18 J7 VSS_THERMAL MDB47 K3 K3 DQ23 J8 VSS_THERMAL DQ23 MDB45 J3 J3 DQ20 J9 VSS_THERMAL MDB42 F3 DQ20 F3 DQ16 DQ16 MDB44 J2 DQ21 J2 DQ21 M13 MCL/DSF MDB40 G2 G2 DQ19 MDB41 F2 DQ19 F2 DQ17 MDB46 K2 DQ17 K2 DQ22 DQ22 H3 H2 DQMB#5 QSB5 DM2 DQS2 H3 H2 C23 B4 B11 D4 D5 D6 D9 D10 D11 E6 E9 F5 F10 G5 G10 H5 H10 J5 J10 K5 K10 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS E5 E7 E8 E10 K6 K7 K8 K9 L5 L10 VREF N13 C684 C679 C SB 0201 1D8V_S0 R510 1KR2F C682 HY5DS573222F-28 SCD1U16V (M24 HYNIX 64MB) 72.52832.F0U - (M26 HYNIX 128MB) 72.55732.B0U DM2 DQS2 DQMB#3 QSB3 MDB63 MDB59 MDB58 MDB60 MDB56 MDB62 MDB57 MDB61 DQ8 DQ12 DQ13 DQ10 DQ14 DQ9 DQ15 DQ11 SCD1U16V C675 SC10U10V5ZY K13 G13 G12 J13 F13 K12 F12 J12 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ D N4 M5 M10 2 B3 B2 MAB12 MAB13 SB 0201 DQMB#4 QSB4 DQ3 DQ1 DQ2 DQ0 DQ6 DQ5 DQ4 DQ7 CLOSE TO MEM !! 2 2 1 MDB28 MDB29 MDB31 MDB25 MDB26 MDB27 MDB24 MDB30 B HY5DS573222F-28 HY5DS573222F-28 (M24 HYNIX 64MB) 72.52832.F0U - (M26 HYNIX 128MB) 72.55732.B0U (M24 HYNIX 64MB) 72.52832.F0U - (M26 HYNIX 128MB) 72.55732.B0U U64E of U65E of DQMB#2 QSB2 D12 D13 E13 C9 B10 B8 C13 B9 DQ26 DQ25 DQ24 DQ30 DQ28 DQ31 DQ27 DQ29 B12 B13 DM3 DQS3 MDB53 MDB54 MDB52 MDB51 MDB50 MDB49 MDB55 MDB48 DQMB#6 QSB6 CLOSE TO MEM D12 D13 E13 C9 B10 B8 C13 B9 DQ26 DQ25 DQ24 DQ30 DQ28 DQ31 DQ27 DQ29 B12 B13 DM3 DQS3 C681 SCD1U16V R509 1KR2F MDB20 MDB23 MDB22 MDB16 MDB19 MDB17 MDB21 MDB18 VDDR_VREF4 E5 E7 E8 E10 K6 K7 K8 K9 L5 L10 C672 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS DM0 DQS0 B5 C6 B6 B7 D2 D3 C2 E2 C3 C5 C7 C8 C10 C12 E3 E12 F4 F11 G4 G11 J4 J11 K4 K11 Layout trace 20 mil 1D8V_S0 N13 SB 0201 HY5DS573222F-28 HY5DS573222F-28 (M24 HYNIX 64MB) 72.52832.F0U - (M26 HYNIX 128MB) 72.55732.B0U (M24 HYNIX 64MB) 72.52832.F0U - (M26 HYNIX 128MB) 72.55732.B0U R516 1KR2F C676 SCD1U16V HY5DS573222F-28 NC#C4 NC#C11 NC#H4 NC#H11 NC#L12 NC#L13 NC#M3 NC#N3 M13 VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL SB 0201 C4 C11 H4 H11 L12 L13 M3 N3 F6 F7 F8 F9 G6 G7 G8 G9 H6 H7 H8 H9 J6 J7 J8 J9 B4 B11 D4 D5 D6 D9 D10 D11 E6 E9 F5 F10 G5 G10 H5 H10 J5 J10 K5 K10 B3 B2 MDB32 MDB33 MDB34 MDB35 MDB36 MDB38 MDB37 MDB39 of VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ 1D8V_S0 1 C19 SCD1U16V VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ DQ3 DQ1 DQ2 DQ0 DQ6 DQ5 DQ4 DQ7 U65B D7 D8 E4 E11 L4 L7 L8 L11 C4 C11 H4 H11 L12 L13 M3 N3 R27 60D4R2F 60D4R2F C3 C5 C7 C8 C10 C12 E3 E12 F4 F11 G4 G11 J4 J11 K4 K11 B5 C6 B6 B7 D2 D3 C2 E2 of R33 R30 60D4R2F 60D4R2F HY5DS573222F-28 HY5DS573222F-28 (M24 HYNIX 64MB) 72.52832.F0U - (M26 HYNIX 128MB) (M24 72.55732.B0U HYNIX 64MB) 72.52832.F0U - (M26 HYNIX 128MB) 72.55732.B0U of of U64C U65C 1D8V_S0 2 R26 CKE CLK CLK# CLOSE TO MEM !! CKEB N12 VDDRC_CLK0+M11 VDDRC_CLK0- M12 110R3 10R3 BC753_1 B R28 R29 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ DQMB#0 QSB0 BA0 BA1 NC#M10 D7 D8 E4 E11 L4 L7 L8 L11 N4 M5 M10 MAB12 MAB13 VDD VDD VDD VDD VDD VDD VDD VDD SC10U10V5ZY A0 A1 A2 A3 A4 A5 A6 A7 A8/AP A9 A10 A11 NC#L9 RAS# CAS# WE# CS# NC#M4 N5 N6 M6 N7 N8 M9 N9 N10 N11 M8 L6 M7 L9 MDB7 MDB6 MDB5 MDB4 MDB1 MDB0 MDB2 MDB3 MAB0 MAB1 MAB2 MAB3 MAB4 MAB5 MAB6 MAB7 MAB8 MAB9 MAB10 MAB11 U64B A0 A1 A2 A3 A4 A5 A6 A7 A8/AP A9 A10 A11 NC#L9 BC754_1 M2 L2 L3 N2 M4 2 2 C RASB# CASB# WEB# CSB#0 CSB#1 C22 C673 SC330P50V2KX SCD01U16V2KX C50 SCD01U16V2KX of U64A 51 CLKB0 51 CLKB#0 1 1 1 C694 C683 C48 C20 C130 C21 C49 C678 SC330P50V2KX SC330P50V2KX SC330P50V2KX SC330P50V2KX SC330P50V2KX SC330P50V2KX SC330P50V2KX SC330P50V2KX 2 1 D N5 N6 M6 N7 N8 M9 N9 N10 N11 M8 L6 M7 L9 VDD VDD VDD VDD VDD VDD VDD VDD SC10U10V5ZY MAB0 MAB1 MAB2 MAB3 MAB4 MAB5 MAB6 MAB7 MAB8 MAB9 MAB10 MAB11 RAS# CAS# WE# CS# NC#M4 C671 SCD01U16V2KX M2 L2 L3 N2 M4 SC10U10V5ZY 51 RASB# 51 CASB# 51 WEB# 51 CSB#0 51 CSB#1 51 QSB[7 0] C18 SCD1U16V 2 C693 SCD1U16V C680 SCD1U16V 2 1 C16 SCD1U16V C674 SCD1U16V C44 SCD1U16V 2 C46 SCD1U16V 1 1 C17 SCD1U16V C45 SCD1U16V 2 1 C47 SCD1U16V 51 DQMB#[7 0] 1 1D8V_S0 SB 0201 of U65A 51 MAB[13 0] SB 0201 Dummy when use UMA (WHOLE PAGE) All dampings in this page must near the VRAM NC#C4 NC#C11 NC#H4 NC#H11 NC#L12 NC#L13 NC#M3 NC#N3 A VDDR_VREF3 A C677 SCD1U16V Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C R515 1KR2F Title 2 CLOSE TO MEM 1 (M24 HYNIX 64MB) 72.52832.F0U - (M26 HYNIX 128MB) 72.55732.B0U ATI VRAM (2/2) Layout trace 20 mil Size A3 Document Number Date: Thursday, March 31, 2005 Rev -1 Bolsena Sheet 53 of 58 D D SB 0201 C C SRN0-1-U 49 49 49 49 ATI_TXBCLK+ ATI_TXBCLKATI_TXBOUT2+ ATI_TXBOUT2- 49 49 49 49 ATI_TXBOUT1+ ATI_TXBOUT1ATI_TXBOUT0+ ATI_TXBOUT0- LCD_TXBCLK+ 13,17 LCD_TXBCLK- 13,17 LCD_TXBOUT2+ 13,17 LCD_TXBOUT2- 13,17 LCD_TXBOUT1+ LCD_TXBOUT1LCD_TXBOUT0+ LCD_TXBOUT0- LCD_TXACLK+ 13,17 LCD_TXACLK- 13,17 LCD_TXAOUT2+ 13,17 LCD_TXAOUT2- 13,17 LCD_TXAOUT1+ LCD_TXAOUT1LCD_TXAOUT0+ LCD_TXAOUT0- RN97 SRN0-1-U 13,17 13,17 13,17 13,17 RN96 SRN0-1-U 49 49 49 49 ATI_TXACLK+ ATI_TXACLKATI_TXAOUT2+ ATI_TXAOUT2- ATI_TXAOUT1+ ATI_TXAOUT1ATI_TXAOUT0+ ATI_TXAOUT0- RN92 SRN0-1-U 49 49 49 49 13,17 13,17 13,17 13,17 RN91 B R160 49 ATI_LCDVDD_ON B 0R2-0 LCD_VDD_ON 13,17 3D3V_S0 R521 2K2R2 3D3V_S0 U67 23,49 VGA_LOCAL_DP 3D3V_S0 DY SMBCLK SMBDATA ALERT# GND VGA_SMB_CLK 49 VGA_SMB_DAT 49 SB 0201 DY C697 SCD1U To M24 To M26 G781 DY R535 0R2-0 GPIO_AUXWIN 49 DY Q26 DY PDTC144EU 2 DY R536 10KR2 VGA_ALERT# 49 23,49 VGA_LOCAL_DN VCC DXP DXN THERM# 2 1 C695 SC2200P50V2KX DY A Dummy use ''M26' A Dummy when use UMA Wistron Corporation SB 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title VGA SELECTOR Size A3 Document Number Date: Thursday, March 31, 2005 Rev -1 Bolsena Sheet 54 of 58 A B C D E FAN5234 FOR VGA_Core VGA_CORE_S0 DCBATOUT Dummy when use 'UMA' (whole page) VGA_CORE_PWR VGA_CORE_S0 DCBATOUT_5234 GAP-CLOSE-PWR G63 2 GAP-CLOSE-PWR GAP-CLOSE-PWR G61 GAP-CLOSE-PWR GAP-CLOSE-PWR G8 GAP-CLOSE-PWR G7 2 G3 GAP-CLOSE-PWR G57 G2 GAP-CLOSE-PWR G58 GAP-CLOSE-PWR G60 GAP-CLOSE-PWR G59 G9 GAP-CLOSE-PWR GAP-CLOSE-PWR G54 G10 GAP-CLOSE-PWR GAP-CLOSE-PWR GAP-CLOSE-PWR G56 G62 2 GAP-CLOSE-PWR G55 DCBATOUT_5234 GAP-CLOSE-PWR G53 5V_S5 SC10U25V0KX GAP-CLOSE-PWR G5 GAP-CLOSE-PWR G1 GAP-CLOSE-PWR G4 G S S S SB 0127 2 SB 0127 FDS6612A SCD1U25V3KX TC22 ST330U2D5VDM-3 C706 SCD1U TC21 ST330U2D5VDM-3 D Q5 2N7002 PWM Mode: FPWM (High)=>Fixed PWM Mode FPWM (Low)=>Hysteretic Mode GPIO_PWRCNTL 49 R87 10KR2 2KR2F DUMMY-R3 G S R538 R58 5234_VSEN Rilim=(11.2/Iilim)*((100+Rsense)/Rdson) High(3.3V)=>Vo=1.0V Low(0V)=>Vo=1.2V KEMET V Size 330uF 2.5V ESR=9mohm, Iripple=3.7A NTD:9.0 KEMET B2 Size 220uF 2.5V ESR=35mohm Iripple=1.6A NTD:6.0 2 2 C61 SCD1U25V3KX SC2200P50V2KX C700 R57 10KR2 TP73 TPAD30 FAN5234MTCX R59 464R3F R537 698R2F C699 SCD01U16V2JX G S S S R523 40K2R2F SC 0308 C696 SCD22U16V3ZY 5V_S0 300KHz FDS6690A PGOOD IND-2D2UH-4 U15 5234_HDRV 5234_LDRV 14 10 VGA_CORE_PWR 2 HDRV LDRV SC 0303 L25 1 VSEN VOUT VIN VCC 1K2R2F R522 2 5234_ISEN 5234_SW 12 13 ISNS SW PGND AGND FPWM BOOT SS ILIM EN D D D D 11 5234_VIN 1 R60 0R0603-PAD 16 15 5234_SS 5234_ILIM 5234_EN 10KR2 DCBATOUT_5234 DY 1D2V or 1D15V Iomax=10 or 5.2A OCP>20A U68 R525 1 C87 R524 DUMMY-R2 SB 0131 5234_BOOT SSM5818SL PM_SLP_S3# C85 SCD1U 18,21,34,38,39,43,44,57 SC10U25V0KX U18 D D D D C60 SCD1U16V D9 5V_S0 GAP-CLOSE-PWR 1 1 2 C59 SC4D7U10V5ZY C84 G6 C86 2 Vout Setting: 0.9V/Rlow=(Vout-0.9V)/Rhigh M24/M26 POWER PLAY (GPIO_PWRCNTL) high (3.3V) = set lower core voltage (VDDC = 1.0V) low (0V) = set higher core voltage (VDDC = 1.2V) 3D3V_S0 1D5V_VGA_1_S0 GAP-CLOSE-PWR C755 SC10U25V6KX G64 2 GAP-CLOSE-PWR 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C R596 10KR2F-U Title DY VGA CORE 1D2V or 1D0V Size A3 (Power Team) A Wistron Corporation 1 APL5332KAC U74 C753 SCD1U NC#8 NC#7 GND NC#5 GND R597 8K66R2F VIN BS FB VOUT C756 SC10U10V5ZY C754 SC10U10V5ZY 2 1D5V_VGA_S0 G67 B C D Document Number Date: Thursday, March 31, 2005 Rev -1 Bolsena Sheet E 55 of 58 DY 1 2HOLE3 HOLE8 HOLE HOLE HOLE6 HOLE HOLE7 HOLE HOLE5 HOLE HOLE10 HOLE HOLE28 HOLE HOLE9 HOLE 1HOLE18 HOLE20 HOLE HOLE2 HOLE HOLE HOLE22 HOLE 1 1 1 1 3D3V_S5 DY 5V_AUX_S5 EC23 SCD1U16V 3D3V_LAN_S5 CHG_PWR-2 47 AD+ 5130_LL1 44,45 5130_LL2 44,45 2 EC21 SCD1U16V 2 EC20 SCD1U16V HOLE23 HOLE 1 1 DY EC19 SCD1U16V HOLE4 HOLE 1D2V_S0 HOLE1 HOLE 1D8V_S0 HOLE24 HOLE VGA_CORE_PWR HOLE13 HOLE 5130_LL3 44,45 MAX1544_LXM 41,42 DY 1 EC89 DY EC88 MAX1544_LXS 41,42 1 DY 1 2 2 1 1 2 1 2 DY EC87 DY D DY EC90 3D3V_S5 EC45 SCD1U16V 5VA_OP_S0 EC44 SCD1U16V EC43 SCD1U16V EC42 SCD1U16V EC41 SCD1U16V EC40 SCD1U16V EC39 SCD1U16V EC38 SCD1U16V 2D5V_S0 DOCK_AD+ DY 1 EC52 SCD1U16V EC53 SCD1U16V EC51 SCD1U16V EC50 SCD1U16V EC49 SCD1U16V 1 EC48 SCD1U16V 2 EC47 SCD1U16V EC46 SCD1U16V 1 C EC22 SCD1U EC62 SCD1U DY EC35 SCD1U 2 DCBATOUT 2 2 DY EC34 SCD1U DY EC33 SCD1U16V DCBATOUT 1 DY DCBATOUT EC37 SCD1U16V 1 2 2 1 DY EC86 EC82 SC1000P50V2KX DY SC1500P50V3KX 3D3V_LAN_S5 EC32 SCD1U16V DY SC1000P50V2KX DY EC85 SC1500P50V3KX DY DY SC 0310 3D3V_S0 EC84 SC1000P50V2KX C 3D3V_BT_S0 EC31 SCD1U16V EC83 EC30 SCD1U16V EC36 SCD1U16V 2D5V_S0 DY MAX1999_LX5 43 1D2V_PWR EC29 SCD1U16V MAX1999_LX3 43 DY SC1500P50V3KX EC28 SCD1U16V DY SC1000P50V2KX 2D5V_PWR DY SC1500P50V3KX 1D8V_PWR 1 2 1 2 1 2 DY EC27 SCD1U16V 2 DY SC 0310 1 1 EC74 SCD1U SC1000P50V2KX EC73 SCD1U EC81 SC1500P50V3KX EC72 SCD1U EC80 SC1000P50V2KX DY EC26 SCD1U16V EC71 SCD1U16V EC79 SC1500P50V3KX DY EC25 SCD1U16V EC70 SCD1U16V EC78 SC1000P50V2KX DY EC24 SCD1U16V EC69 SCD1U16V EC77 SC1500P50V3KX EC68 SCD1U16V 2D5V_S0 EC76 SC1000P50V2KX 2D5V_S3 EC75 SC1500P50V3KX D 1 CHG_PWR-3 47 FAN1_VCC FOR MDC HOLE12 DCBATOUT HOLE11 EC66 SCD1U 34.42E05.001 HOLE16 SC 0308 1 34.42E05.001 EC67 SCD1U SC 0309 GND16 GND17 GND1 GND2 13 14 TSLCX125 TSLCX125 34.40V16.001 DY DY 34.42E05.001 Dummy when no EZ4 34.40V16.001 GND12 U54F DY GND9 SPRING-1 SPRING-1 34.42E05.001 14 DY 13 A Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C 12 GND11 34.40V16.001 DY 34.40V16.001 34.40V16.001 HOLE19 11 3D3V_AUX_S5 34.40V16.001 GND10 1 34.40V16.001 34.49U24.001 GND8 DY 14 12 1 GNDPAD 34.42T14.001 U40D HOLE21 GND6 34.45T31.001 1 34.45T31.001 34.40V16.001 U40A GND3 34.40V16.001 GND7 FOR NORTH BRIDGE HOLE17 DY SPRING-1 SPRING-24 SPRING-24 SPRING-1 SPRING-1 SPRING-1 SPRING-1 DY DY GND4 1 GND5 3D3V_S5 SPRING-1 SPRING-1 SPRING-1 34.49U24.001 A 34.40V16.001 34.45T31.001 SPRING-24 SPRING-1 DY 34.40V16.001 GND18 3D3V_S5 B 34.42E05.001 SC 0301 GND15 SPRING-29 GND14 34.42E05.001 34.42E05.001 DY GND20 GND13 ZZ.NDPAD.XXX 34.39S07.001 34.40V16.001 SPRING-1 SPRING-23 34.39S07.001 1 34.39S07.001 SPRING-23 SPRING-23 34.39S07.001 SPRING-23 GND24 GNDPAD DY GND23 ZZ.NDPAD.XXX DY GND21 34.42E05.001 BT+ GREEN COLOR FOR INSTALL GND22 HOLE15 B GND19 HOLE14 SCD1U => VOLTAGE 25V IMPORTANT: SCD1U => VOLTAGE 25V SCD1U16V => VOLTAGE 16V DY 1 EC64 SCD1U EC65 SCD1U EC59 SCD1U EC58 SCD1U 1 EC57 SCD1U EC60 SCD1U 1 EC56 SCD1U EC55 SCD1U 1 EC54 SCD1U SC 0308 2 FOR VGA CHIP EC63 SCD1U16V TSLCX14MTC-L-U Title Size A3 EMI Document Number Rev -1 Bolsena Date: Thursday, March 31, 2005 Sheet 56 of 58 B C PPD[7 0] 126 15 EZ4_DVI_DDC_D 15,49 TMDS_EZ4_TXC+ 15,49 TMDS_EZ4_TXC34 EZIN_EM# 15 EZ4_DVI_DDC_C R498 1KR2 33 DOCK_LIN_R 33 DOCK_MIC_JKIN TV_COMP_DOCK TV_LUMA_DOCK 33 DOCK_LIN_L TV_CRMA_DOCK 33 SPKR_R_DOCK 33 DOCK_EXT_MIC CRT_R_DOCK 33 SPKR_L_DOCK CRT_G_DOCK CRT_B_DOCK 16 EZ4_HS 16 EZ4_CRT_DDC_D 16 EZ4_VS 12 PCIE_RXP0 12 PCIE_RXN0 5V_S0 16 EZ4_CRT_DDC_C SC 0309 R501 1KR2 SMBC_SB_EZ4 12 PCIE_TXP0 12 PCIE_TXN0 SMBD_SB_EZ4 34 EZ_PWROK SC 0309 34 PE_REQ1# CLK_PCIE_DOCK1 CLK_PCIE_DOCK1# 12 PCIE_RXN1 12 PCIE_RXP1 U3 LUSB1# 21 33 34 35 36 37 38 10 39 40 11 12 41 42 13 14 43 44 15 16 45 46 17 18 47 48 19 20 49 50 21 22 51 52 23 24 53 54 25 26 55 56 27 28 57 58 29 30 59 60 122 121 D_RTGP1 D_RTGP1 30 D_TGP2 30 D_RTGN1 30 D_TGN2 D_TGN2 30 49 DIS_COMP 49 DIS_LUMA 49 DIS_CRMA FOR LINK LED (GREEN) D_TGP3 30 D_TGN3 30 PSTROB# 58 PAUTOFD# 58 DOCK_JACK_IN PPD0 PERROR# DOCK_JACK_IN 33 13 UMA_LUMA 13 UMA_CRMA 13 UMA_COMP SUSON MAINON R6 TV_CRMA TV_LUMA TV_CRMA TV_COMP 0R0402-PAD R15 2 5 PCIRST_BUF# 15,18,26,28,29,31 CRT_G_1 CRT_B_1 CRT_R_1 U6 CRT_R_1 0R0402-PAD R7 DOCK_ON_1 30 R507 NC7SZ08-U CRT_G_SYS 16 NC7SB3157P6X-U CRT_B_DOCK B0 GND B1 CRT_B_SYS 16 NC7SB3157P6X-U CRT_R_DOCK B0 GND B1 CRT_R_SYS 16 Dummy when no EZ4 SRN0-1-U RN87 3D3V_S5 18,21,34,38,39,43,44,55 DTR1_BOUT1_5 RI1#_5 RTS1#_5 EZIN_EM# U40C MAINON TSLCX125 SUSON TSLCX125 Dummy when no EZ4 Dummy when no EZ4 RC14 1 EZIN_EM# U40B 21,34,44 PM_SLP_S5# SOUT1_5 10KR2 PM_SLP_S3# 3D3V_S5 CTS1#_5 SIN1_5 DSR1#_5 DCD1#_5 DOCK_ON_2# Q25 CHT2222A 21 RC15 Wistron Corporation 8 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title SRC100P50V-U SRC100P50V-U EASY PORT4 (1/2) Size A3 Dummy when no EZ4 A B Dummy when use EZ4 GND L Y L DOCK_CRT_ON# R508 10KR2 R500 1MR2 H DOCK CRT_G_DOCK B0 GND B1 14 B H TV NC7SB3157P6X-U A VCC S 5V_S0 EZ_PWROK Q24 CHT2222A DOCK H RN85 13 UMA_G 13 UMA_B 13 UMA_R CRT_G_1 CRT_B_1 CRT_R_1 L CRT SYSTEM 1 DY EZIN_EM# A VCC S SC 0308 U58 VCC A VCC S U8 CRT_B_1 SRN0-1-U ME : 20.80591.120 A Function CRT_R_1 CRT_G_1 CRT_B_1 DOCK_ON_2# LAN 5V_S0 CRT_G_1 SB 0127 1 U7 Dummy when use Discrete SYSTEM TV_CRMA_SYS 16 RN84 SRN0-1-U Dummy when use UMA D2 1KR2 BAT54-1 CLK_PCIE_DOCK2 CLK_PCIE_DOCK2# PCIE_TXP1 12 PCIE_TXN1 12 Function TV_CRMA_DOCK B0 GND B1 C4 SCD1U16V 49 DIS_R 49 DIS_G 49 DIS_B 20.80591.120 DOCK_IN NC7SB3157P6X-U RN86 FOX-CONN120-2-GP 3D3V_S5 TV_LUMA_SYS 16 Dummy when use EZ4 CRT SWITCH DOCK_AD+ R499 10KR2 TV_LUMA_DOCK B0 GND B1 DOCK_TV_ON# SRN0-1-U 3D3V_S5 NC7SB3157P6X-U TV_COMP TV_LUMA TV_CRMA SC 0308 DOCK_ON_2# A VCC S 125 TV_COMP_SYS 16 Dummy when no EZ4 Dummy when use Discrete PACK# 58 PS2_KDAT 34 PS2_KCLK 34 PBUSY 58 PPE 58 PS2_MDAT 34 PS2_MCLK 34 PSLCT 58 LUSB2# 21 3D3V_S0 ?10K PULL TOO SLOW - 0324 R5 10KR22 PSLCT SRN0-1-U DCD1#_5 37 PBUSY PPE A VCC S U5 SIN1_5 37 DSR1#_5 37 PPD5 PPD6 H TV_COMP_DOCK B0 GND B1 L A to B1 RN93 PSLCTIN# 58 SOUT1_5 37 RTS1#_5 37 PPD3 PPD4 U4 TV_LUMA Dummy when use UMA PINIT# 58 DTR1_BOUT1_5 37 CTS1#_5 37 PPD2 PSLCTIN# TV_COMP TV_LUMA TV_CRMA A VCC S S A to B0 SC 0309 PERROR# 58 SPDIF 32,33 RI1#_5 37 PPD1 PINIT# SRN0-1-U 10M_LED# 29,30 D_TGP3 D_TGN3 PSTROB# PAUTOFD# TV_COMP RN83 D_TGP2 D_RTGN1 PPD7 PACK# C9 SCD1U16V NC7SB3157P6X-U Function 14 15,49 TMDS_EZ4_TX0+ D_TTGP0 30 D_TTGN0 30 ACT_LED# 29,30 93 94 64 63 95 96 66 65 97 98 68 67 99 100 70 69 101 102 72 71 103 104 74 73 105 106 76 75 107 108 78 77 109 110 80 79 111 112 82 81 113 114 84 83 115 116 86 85 117 118 88 87 119 120 90 89 123 124 15,49 TMDS_EZ4_TX015 DVI_EZ4_HPD TV SWITCH 58 5V_S0 D_TTGP0 D_TTGN0 31 32 91 92 62 61 TMDS_EZ4_TX1TMDS_EZ4_TX1+ TMDS_EZ4_TX2+ TMDS_EZ4_TX2- E 15,49 15,49 15,49 15,49 D 10 EZ1 A C Document Number Rev Bolsena Date: Thursday, March 31, 2005 D -1 Sheet E 57 of 58 PRINT PORT PRN5V C685 SCD1U16V PACK# PBUSY PSLCT PPE SRN33 R511 33R2 PSTROB# PACK# 57 PBUSY 57 PSLCT 57 PPE 57 EZ4_PD1 ERROR#_5 EZ4_PD0 AUTOFD#_5 C669 SCD1U16V 10 PRINIT#_5 EZ4_PD2 SLCTIN#_5 EZ4_PD3 10 EZ4_PD4 EZ4_PD5 EZ4_PD6 EZ4_PD7 PSTROB# 57 RP6 RC11 SRC100P50V-U SRC100P50V-U SRP1K PE_5 SLCT_5 BUSY_5 PRNACK#_5 RN10 EZ4_PD4 EZ4_PD5 EZ4_PD7 EZ4_PD6 RC13 PPD4 PPD5 PPD7 PPD6 SRN33 SRP1K PSTROB# PPD6 PPD7 PPD5 PPD4 PPD1 PERROR# PPD0 PAUTOFD# 37 STROB#_5 CH751H-40-U RP5 SRN33 RN11 37 PRNACK#_5 37 BUSY_5 37 SLCT_5 37 PE_5 PSLCTIN# 57 EZ4_PD3 D30 PINIT# 57 EZ4_PD2 PINIT# PPD2 PSLCTIN# PPD3 37 PRINIT#_5 37 SLCTIN#_5 5 5V_S0 RN9 4 PPD3 PSLCTIN# PPD2 PINIT# PSLCT PPE PBUSY PACK# 57 PPD[7 0] 37 EZ4_PD[7 0] C660 SC100P50V2JN 37 ERROR#_5 PAUTOFD# PPD0 PPD1 PERROR# PAUTOFD# 57 PERROR# 57 SRN33 STROB#_5 R512 1KR2 RC10 RC12 1 Place near Dock1 EZ4_PD0 EZ4_PD1 37 AUTOFD#_5 RN8 SRC100P50V-U SRC100P50V-U For EMI Place near Dock1 Dummy when no EZ4 cap between moat (for UMA RGB signal) 1D2V_S0 1D8V_S0 C961 SCD1U16V 5V_S0 C962 C963 SCD1U16V SCD1U16V SB 0213 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title EASY PORT4 (2/2) Size A3 Document Number Rev -1 Bolsena Date: Thursday, March 31, 2005 Sheet 58 of 58 ... (AFTER SB) Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title CHANGE HISTORY Size A3 Document Number Bolsena Date: Thursday, March... FS2 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title CLKGEN_IDTCV137 Size A3 Document Number Rev A B C D -1 Bolsena Date: Thursday,... 1 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title CPU(1/4)_HyperTransport I/F Size A3 Document Number Rev A B C D -1 Bolsena Date: