A B C D Garda-5 Block Diagram Mobile CPU CLK GEN ICS951413 (RTM865T-300/CY28RS400) PCB STACKUP TOP 133/166MHz INPUTS OUTPUTS 5V_S5 DCBATOUT 3D3V_S5 TPS51124RGER 42 INPUTS OUTPUTS DCBATOUT 1D8V_S3 1D2V_S0 APL5312 120mA S TVOUT 14 ATI RC410ME 41 TPS51120 VCC SVIDEO/COMP S www.kythuatvitinh.com LVDS AGTL+ CPU I/F DDR2 x SINGAL DDR2 CHANNEL 533/667MHz 14"WXGA+ LCD 13 RGB CRT INTEGRATED GRAPHICS CRT PCIE x 1 X4 PCIE SB I/F AZALIA 6,7,8,9,10 PCIE x USB2.0 8Ports MIC In SATA II (4 PORTS) AZALIA HD AUDIO 1.0 PCI BUS AC97 2.3 INT.MIC ATA 66/100/133 OP AMP LPC I/F G1432Q 31 ACPI 1.2 PCMCIA I/F 1D2V_S0 TPS2211 26 1394 CONN 43 Support TypeII 26 APL5308 29 MS/MS Pro/xD/ MMC/SD/SDIO Mini-PCI LAN TXFM 24 MAX8725 29 INPUTS DCBATOUT RJ45 PATA SATA NS87381 35 USB FIR 35 PORT 22 21 MINI USB Blue-tooth 4.0A UP+5V 24 5V KBC ENE 3910 Touch Pad 34 33 INT KB 34 INPUTS BIOS LPC MX29LV800 DEBUG CONN 36 36 DCBATOUT 100mA Title Size A3 Date: 39,40 OUTPUTS VCC_CORE_S0 0~1.3V 48A Digitally signed by dd Wistron Corporation DN: cn=dd, ou=dd, 21F, 88, Sec.1,o=dd, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C email=dddd@yahoo.com, BLOCKc=US DIAGRAM Document Number Rev Date: 2009.11.29 17:23:13 Garda-5 -1 of Wednesday, April 26, 2006 46 +07'00' Sheet 22 HDD 21 18V CPU DC/DC SIO 15,16,17,18,19 CHG_PWR ISL6262 22 44 OUTPUTS 32 LPC BUS CDROM 1D8V_S5 MAXIM CHARGER Lab Ver :A11, 71.SB460.A0U Eng Ver :A12, 71.SB460.B0U 300mA 43 in Reltek10/100 RTL8100CL 23 MODEM MDC Card DDR_VREF_S3 DDR_VREF_S0 1D8V_S3 3D3V_S5 RICOH R5C832 1394 CardReader 802.11A/B/G PCI/PCI BDGE Line Out (SPDIF) 1D05V_S0 43 PCMCIA SLOT PWR SW 28,29 MAX4411 RJ11 New card32 INT RTC INT.SPKR 1D5V_NEW_ MINI_S0 43 APL5912 3A PWR SW TPS223132 CARDBUS ENE CB1410 25 30 31 27 1A TPS51100 1A ATI SB460 ALC883 31 APL5332 A-Link Express X4 Codec 31 43 BOTTOM 14 802.11A/B/G Ver.:A13, 71.RC410.D0U Line In 1D5V_CPU_S0 Mini Card*1 X1 PCIE GPP I/F 31 3D3V_S0 GND 3D3V_S0 LVDS/TVOUT/CRT 11,12 SYSTEM DC/DC SYSTEM DC/DC -1-0426 20 4, AGTL+ Project code: 91.4Q201.001 PCB P/N : 55.4Q201.XXX REVISION : 06206-SA (Hannstar, GCE) G792 Yonah 478 E A B USB Pair PCI ROUTING TABLE Device USB1 BT USB2 NEW C USB3 CCD MINIC1 NC PCI_CLK0 PCI_CLK1 PCI_CLK2 PCI_CLK3 PCI_CLK4 PCI_CLK5 PCI_CLK6 PCI_CLK7 C History IDSEL DEVICE REQ# / GNT# AD22 H REQ#1/ GNT#1 AD20 F : 1394 H : in REQ#3/ GNT#3 LAN(RTL8100CL) AD17 E REQ#2/ GNT#2 CARDBUS CB1410 AD16 G REQ#0 / GNT#0 MiniPCI R5C832 PCM IEEE1394 LAN MINI KBC FWH SIO SPDIFOUT IRQ(Default) USB UHCI AD29 USB 2.0 EHCI AD29 DMI-to-PCI AC97 Modem AC97 Audio AD30 A, B, C, D A REQ#1 / GNT#1 B A AD31 A B B PCI Express AD28 A, B, C, D Azalia Controller AD27 A Value Rating Tolerance (J: 5%, F: 1%, D: 0.5%, B: 0.1 %) 0402=> 1/16W, 25V 0603 => 1/16W, 75V 0805 => 1/10W, 100V Size 2=>0402, 3=>0603, 5=>0805, 6=>1206, 0=>1210 10KR3 10K Ohm If no letter, it means J: 5% 1/16W, 75V 0603 33D3R5 33.3 Ohm If no letter, it means J: 5% 1/10W, 100V 0805 1KR3F 1K Ohm F: 1% 1/16W, 75V 0603 The naming rule is value + R + size + tolerance For the value, it can be read by the number before R (R means resistor) For the tolerance, it can be read from the last letter For the rating, we don't show on the symbol name For the size, R2=>0402, R3=>0603, R5=>0805, CAPACITOR Symbol name Value Tolerance (J: +/-5, K: +/-10, M: +/-20, Z: +80/-20) E =========================================================== 2006/04/26 (-1 Modify) page 27, change R8/R226 to 100 ohm due to power/email to dark page 15, change C286/C287 from 18pf to 15pf due to frequence shift(from -6.7 to 4ppm) page 23, change C295/C294 from 15p to 12p due to frequence shift(from -23.3 to 7.9ppm) EMI Solution for USB/MDC a Change L23, L24, L31, L32 to "69.10084.071" b del R353,R354,R356,R360,R445,R446 c Change L1, L2 to "68.00331.011" Page 44, change C12/C14 to 78.10699.43L due to 78.10699.42L Obsoleted =========================================================== 2006/04/13 (-1 Modify) Page 31, R447/R448 33ohm Page 45, Add D4:83.P4SSM.0AM Page 44, Change C321 from 78.10492.4BL to 78.10224.2BL(1000P, 50V, K0603) Page 23, change R209 from 5.6K to 5.37K Page 24, change XF1 from 68.68161.30A to 68.01201.30A Page 46, Mini card stand-off(銅柱) need to be changed from 34.4P401.001 to 34.4A907.001 change 84.27002.L04 to 84.27002.F31 =========================================================== 2006/04/10 (-1 Modify) Page 8, add "LVDS_DIGON" solution from ATI PA note Page 31, Add R to GND and serial R for U60 pin13/15 =========================================================== 2006/04/03 (SB Modify) Page 40, Dummy C593 Page 44, Del C32 Page 41, DCBATOUT_51120 change to DCBATOUT (Del G4,G5,G6,G7,G8) Page 4/5, updae CPU symbol Page 15, Change X5 to same as X1 due to ME high limit issue, Cap the same as X1 but should fine-tune Page 39/41/42, change "GAP-CLOSE-PWR" to ohm PAD due to layout concern =========================================================== 2006/03/31 (SB Modify) Page 3, change R139 to bead and C211 to 2.2u for CRT Jitter Page 6, change R105 from 1.8K to 4.7K Page 8, change C165 to 2.2u for ATI recommend Page 8, SIV EDID_CLK/DAT issue, change RN53 to 4.7K Page 14, SIV RBG fail: Page 15, a PCIRST1#(1394) shoulder: Add 33 ohm @ SB b PLT_RST1# overshot : change R144 to 33ohm & R141 to 100P c Add 0ohm for RTC power for ATI recommend Page 40 , add 10U Cap Page 13/27, change Green LED4/LED5/LED1 to 83.00190.L70 (manual change yellow LED6/LED3/LED8/LED2 to 83.00190.S70) EMI request: a Page 13, USB_PP5,USB_PN5 add COMMON CHOKE b EC28,EC34,C208 add O.1μCap c CLK48_ICH( near CLK GEN.),SB_CLK33_FWH(near R177) add 20p Cap =========================================================== 2006/03/28 (SB Modify) Page 14, change Q15/Q14 to 2N7002 for SIV CRT SMBus bug Page 15, Change C248/C261/C264/C263/C252 from 78.10491.4FL to 78.10523.5F1, and C262 from 78.10693.41L to 78.10623.51L Page 8, Add "LCDVDD_ON" PL 100K Page 41, change U7 to AO4406(84.04406.A37) Page 33, KBC GPIO09 for 1394 Page 33, add 1u Cap for ENE ECRST# spec 2ms Page 31, add audio popo noise solution Page 25, change C520 to 1U for "GBRST#" Page 28, change "GBUS_GRST#_1" timing =========================================================== www.kythuatvitinh.com LPC Bridge IDE SATA SMBus RESISTOR Symbol name D Rating ( X5R / X7R < 80%, Y5V/Y5U/Z5U < 1/3 ) Size 2=>0402, 3=>0603, 5=>0805, 6=>1206, 0=>1210 SCD1U10V2MX-1 0.1uF M/X5R 10V 0402 SC10U6D3V5MX 10uF M/X5R 6.3V 0805 SC2D2U16V5ZY 2.2uF Z/Y5V 16V 0805 The naming rule is Capacitor type + value + rating + size + tolerance + material SCD1U10V2MX-1 SC=> SMT Ceremic, TC=> POS cap or SP cap D1U => 0.1uF 10V => the voltage rating is 10V 2=> 0402, 3=>0603, 5=>0805 M=>tolerance J, K, M, Z X=> X7R/X5R, Y=> Y5V -1 => symbol version, nonsense to EE characteristic Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title Reference Size A3 Document Number Rev Garda-5 Date: Wednesday, April 26, 2006 -1 Sheet of 46 B D Bead: 200ohm, 200mA Bead: 26ohm, 600mA X-14D31818M-31GP 82.30005.831 C199 X2 R140 GEN_XTAL_OUT_R CLK_IREF 475R2F-L1-GP 11,18,27,32 SMB_CLK 11,18,27,32 SMB_DATA R127 1MR2J-1-GP 32 27 18 SC27P50V2JN-2-GP FS_C CLKREQ_NEW# CLKREQ_MINI# CLK48_ICH R134 C594 SC20P50V2JN-1GP DY R132 OSC14M 1 SCD1U16V2ZY-2GP 2 C203 1 1 C201 At least 22u*1, 0.1u*7 37 10 11 53 54 52 50 48 X2 X1 IREF SCLK SDATA FS_C CLKREQA# CLKREQB# USB_48MHZ FS_B/REF1 FS_A/REF0 TEST_SEL/REF2 CK410#/PCICLK0 VTT_PWRGD#/PD CPU_STOP# VDDA 39 3D3V_CLKPLL_S0 VDD48 3D3V_48MPWR_S0 VDDATI 32 3D3V_CLKGEN_S0 VDDCPU 45 www.kythuatvitinh.com SC27P50V2JN-2-GP SMbus Table: Byte4 bit 4, CLKREQA# Byte2 bit 3, CLKREQB# "0": not controlled, "1": controlled PL: always output 39 15 CLK_EN# CPU_STP# CLK_MCH_BCLK CLK_MCH_BCLK# NB free-running: Byte5 bit5 =0 CLK_CPU_BCLK CLK_CPU_BCLK# R133 SRN33J-5-GP-U SRN33J-5-GP-U R137 CLK48 FS_B FS_A OSC14M_R SEL_CK410# CLK_EN# CPU_STP#_R 33R2J-2-GP 33R2J-2-GP 0R0402-PAD CPU_STP# CLK GEN Internal PH 120K 41 40 CPUCLKT2_ITP CPUCLKC2_ITP RN9CLK_MCH_BCLK_1 CLK_MCH_BCLK_1# 43 42 CPUCLKT1 CPUCLKC1 RN7CLK_CPU_BCLK_1 CLK_CPU_BCLK_1# 47 46 CPUCLKT0 CPUCLKC0 36 26 20 15 GNDSRC GNDSRC GNDSRC GNDSRC 49 GNDPCI 44 GNDCPU 31 GNDATI 38 GNDA CLKREQ_NEW# 1KR2J-1-GP R138 CLKREQ_MINI# 1KR2J-1-GP 4,9 18 FSC FSB FSA 0 0 1 0 1 0 1 1 0 0 CPU 100 133 166 200 266 333 400 RESV SRC 100 100 100 100 100 100 100 100 PCI 33 33 33 33 33 33 33 33 CPU_SEL0 SB_OSCIN 4,9 CPU_SEL1 35 CLK14_SIO CPU_SEL2 CK410# = 0, CK410 MODE CK410# = 1, CK409 MODE CLOCK FREQUENCY SELECT TABLE (MHz) C209 SB Modify HCB1608K-300T10GP 68.00214.111 C207 C208 SCD1U16V2ZY-2GP U29 GEN_XTAL_IN C200 C216 SCD1U16V2ZY-2GP Ioh = * Iref (2.32mA) Voh = 0.7V @ 50 ohm C212 SCD1U16V2ZY-2GP At least 22u*1, 0.1U*1 C210 C202 SC2D2U10V3ZY-1GP SCD1U16V2ZY-2GP At least 2.2u*1 C211 SC2D2U10V3ZY-1GP 3D3V_CLKGEN_S0 SC4D7U10V5ZY-3GP 50mA 3D3V_48MPWR_S0 0R3-0-U-GP 2 R377 3D3V_CLKPLL_S0 0R3-0-U-GP 50mA DY 3D3V_S0 R139 500mA SCD1U16V2ZY-2GP 3D3V_S0 R128 C483 SCD1U16V2ZY-2GP E SCD1U16V2ZY-2GP Bead: 200ohm, 200mA 3D3V_S0 C A REF 14.31 14.31 14.31 14.31 14.31 14.31 14.31 14.31 R129 R126 R131 R130 R136 2 2 FS_A 4K7R2J-2-GP 55 33R2J-2-GP FS_B 4K7R2J-2-GP GND GND VDDPCI 51 VDDREF 56 VDDSRC VDDSRC VDDSRC 35 21 14 SRCCLKC7 SRCCLKT7 13 12 SRCCLKC6 SRCCLKT6 17 16 SRCCLKC5 SRCCLKT5 19 18 SRCCLKC4 SRCCLKT4 23 22 CLK_PCIE_NEW_1# RN12 CLK_PCIE_NEW_1 SRCCLKC3 SRCCLKT3 25 24 CLK_PCIE_MINI1_1# RN19 CLK_PCIE_MINI1_1 SRCCLKC0 SRCCLKT0 33 34 CLK_PCIE_ICH_1# CLK_PCIE_ICH_1 ATIGCLKT1 ATIGCLKC1 ATIGCLKT0 ATIGCLKC0 NEW SRN33J-5-GP-U CLK_PCIE_NEW# 32 CLK_PCIE_NEW 32 MINIC SRN33J-5-GP-U CLK_PCIE_MINI1# 27 CLK_PCIE_MINI1 27 RN15 SRN33J-5-GP-U CLK_PCIE_ICH# 15 CLK_PCIE_ICH 15 27 28 CLK_NB_ALINK_1 RN22 CLK_NB_ALINK_1# SRN33J-5-GP-U CLK_NB_ALINK CLK_NB_ALINK# 30 29 CLK_NB_GFX_1 CLK_NB_GFX_1# SRN33J-5-GP-U CLK_NB_GFX CLK_NB_GFX# RN23 ICS951413CGLF 71.95143.A0W ICS951413 Ver C /CY28RS400 Ver.B /CV136 2nd source: 71.00865.A0W 33R2J-2-GP FS_C 4K7R2J-2-GP DY SEL_CK410# 33R2J-2-GP R135 CK410# CLK GEN Internal PL 120K RN18 CLK_PCIE_MINI1# CLK_PCIE_MINI1 SRN49D9F-GP MINIC RN21 CLK_NB_ALINK# CLK_NB_ALINK SRN49D9F-GP 4 For Yonah Cerlon-M For Yonah RN8 CLK_CPU_BCLK CLK_CPU_BCLK# SRN49D9F-GP RN16 CLK_PCIE_ICH CLK_PCIE_ICH# SRN49D9F-GP RN10 CLK_MCH_BCLK CLK_MCH_BCLK# SRN49D9F-GP 4 Wistron Corporation RN11 CLK_PCIE_NEW CLK_PCIE_NEW# SRN49D9F-GP NEW 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title RN24 CLK_NB_GFX CLK_NB_GFX# SRN49D9F-GP Clock Generator -ICS951413 Size A3 Document Number Rev Garda-5 Date: Wednesday, April 26, 2006 A B C D SB Sheet E of 46 A B C D E 1D05V_S0 SB460 contains 400ohm inernal pull-up on CPU sideband signals H_FERR# A20M# IGNNE# INIT# INTR/LIN0 NMI/LIN1 SMI# STPCLK# TP28 TPAD30 U53A H_ADSTB#0 H_REQ#[4 0] H_REQ#0 K3 H_REQ#1 H2 H_REQ#2 K2 H_REQ#3 J3 H_REQ#4 L5 H_ADS# H_BNR# H_BPRI# 6 H5 F21 E1 H_DEFER# H_DRDY# H_DBSY# BR0# F1 H_BREQ#0 IERR# INIT# D20 B3 LOCK# H4 RESET# RS[0]# RS[1]# RS[2]# TRDY# B1 F3 F4 G3 G2 HIT# HITM# G6 E4 R330 R329 R326 H_CPUSLP# R331 H_PWRGD H_DPSLP# H_INIT# 15 H_D#[63 0] H_LOCK# H_CPURST# H_RS#[2 0] 56R2J-4-GP 330R2J-3-GP H_BREQ#0 Place testpoint on H_IERR# with a GND 0.1" away H_IERR# H_RS#0 H_RS#1 H_RS#2 R78 56R2J-4-GP DEFER# DRDY# DBSY# H1 E2 G5 ADS# BNR# BPRI# REQ[0]# REQ[1]# REQ[2]# REQ[3]# REQ[4]# 200R2J-L1-GP 200R2J-L1-GP 200R2J-L1-GP U53B H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 E22 F24 E26 H22 F23 G25 E25 E23 K24 G24 J24 J23 H26 F26 K22 H25 H23 G22 J26 D[0]# D[1]# D[2]# D[3]# D[4]# D[5]# D[6]# D[7]# D[8]# D[9]# D[10]# D[11]# D[12]# D[13]# D[14]# D[15]# DSTBN[0]# DSTBP[0]# DINV[0]# N22 K25 P26 R23 L25 L22 L23 M23 P25 P22 P23 T24 R24 L26 T25 N24 M24 N25 M26 D[16]# D[17]# D[18]# D[19]# D[20]# D[21]# D[22]# D[23]# D[24]# D[25]# D[26]# D[27]# D[28]# D[29]# D[30]# D[31]# DSTBN[1]# DSTBP[1]# DINV[1]# D[32]# D[33]# D[34]# D[35]# D[36]# D[37]# D[38]# D[39]# D[40]# D[41]# D[42]# D[43]# D[44]# D[45]# D[46]# D[47]# DSTBN[2]# DSTBP[2]# DINV[2]# AA23 AB24 V24 V26 W25 U23 U25 U22 AB25 W22 Y23 AA26 Y26 Y22 AC26 AA24 W24 Y25 V23 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 D[48]# D[49]# D[50]# D[51]# D[52]# D[53]# D[54]# D[55]# D[56]# D[57]# D[58]# D[59]# D[60]# D[61]# D[62]# D[63]# DSTBN[3]# DSTBP[3]# DINV[3]# AC22 AC23 AB22 AA21 AB21 AC25 AD20 AE22 AF23 AD24 AE21 AD21 AE25 AF25 AF22 AF26 AD23 AE24 AC20 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 AA1 AA4 AB2 AA3 M4 N5 T2 V3 B2 C3 RSVD[01] RSVD[02] RSVD[03] RSVD[04] RSVD[05] RSVD[06] RSVD[07] RSVD[08] RSVD[09] RSVD[10] TPAD30 TPAD30 TPAD30 TPAD30 TPAD30 TPAD30 TPAD30 TPAD30 TP41 TP39 TP43 TP40 TP32 TP31 TP35 TP36 TPAD30 TP22 TPAD30 TP21 B25 CLK_CPU_BCLK CLK_CPU_BCLK# RSVD[12] T22 TP34 TPAD30 RSVD[13] RSVD[14] RSVD[15] RSVD[16] RSVD[17] RSVD[18] RSVD[19] RSVD[20] D2 F6 D3 C1 AF1 D22 C23 C24 TP26 TPAD30 TP27 TPAD30 H CLK RSVD[11] R76 TP52 TP25 TP24 TP23 TPAD30 TPAD30 TPAD30 TPAD30 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 CPU_PROCHOT# 39 PM_THRMTRIP# should connect to ICH7 and Calistoga without T-ing ( No stub) 1D05V_S0 R125 1KR2F-3-GP Layout Note: 0.5" max length R124 2KR2F-3-GP 6 H_DSTBN#1 H_DSTBP#1 H_DINV#1 CPU_GTLREF0 DY AD26 C197 SC1KP16V2KX-GP R80 DY 1KR2J-1-GP 2TEST1 C26 2TEST2 D25 51R2F-2-GP R83 BGA479-SKT6-GPU2 62.10079.001 DY 0R2J-2-GP 2nd source: 62.10053.401 3,9 3,9 B22 B23 C21 CPU_SEL0 CPU_SEL1 CPU_SEL2 GTLREF DATA GRP A22 A21 BCLK[0] BCLK[1] PM_THRMTRIP-I# 37 THERMTRIP# H_DSTBN#0 H_DSTBP#0 H_DINV#0 R77 56R2J-4-GP C7 XDP/ITP SIGNALS H_THERMDA 20 H_THERMDC 20 1D05V_S0 DATA GRP STPCLK# LINT0 LINT1 SMI# D21 A24 A25 C84 SC2200P50V2KX-2GP D5 C6 B4 A3 H_STPCLK# H_INTR H_NMI H_SMI# PROCHOT# THERMDA THERMDC H_THERMDC 15 15 15 15 TPAD30 TPAD30 TPAD30 TPAD30 TPAD30 TPAD30 TPAD30 TPAD30 TPAD30 TPAD30 TPAD30 TPAD30 A20M# FERR# IGNNE# TP47 TP49 TP50 TP48 TP46 TP51 TP44 TP37 TP42 TP38 TP45 TP20 AD4 AD3 AD1 AC4 AC2 AC1 AC5 AA6 AB3 AB5 AB6 C20 A6 A5 C4 XDP_BPM#0 XDP_BPM#1 XDP_BPM#2 XDP_BPM#3 XDP_BPM#4 XDP_BPM#5 XDP_TCK XDP_TDI XDP_TDO XDP_TMS XDP_TRST# XDP_DBRESET# H_THERMDA 6 DATA GRP 15 H_A20M# 15 H_FERR# 15 H_IGNNE# H_TRDY# H_HIT# H_HITM# BPM[0]# BPM[1]# BPM[2]# BPM[3]# PRDY# PREQ# TCK TDI TDO TMS TRST# DBR# THERM A[17]# A[18]# A[19]# A[20]# A[21]# A[22]# A[23]# A[24]# A[25]# A[26]# A[27]# A[28]# A[29]# A[30]# A[31]# ADSTB[1]# RESERVED H_ADSTB#1 Y2 U5 R3 W6 U4 Y5 U2 R4 T5 T3 W3 W5 Y4 W2 Y1 V4 DATA GRP www.kythuatvitinh.com H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 ADDR GROUP 1D05V_S0 A[3]# A[4]# A[5]# A[6]# A[7]# A[8]# A[9]# A[10]# A[11]# A[12]# A[13]# A[14]# A[15]# A[16]# ADSTB[0]# CONTROL J4 L4 M3 K5 M1 N2 J1 N3 P5 P2 L1 P4 P1 R1 L2 ADDR GROUP H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#[31 3] R327 COMP[0] COMP[1] COMP[2] COMP[3] R26 U26 U1 V1 DPRSTP# DPSLP# DPWR# PWRGOOD SLP# PSI# E5 B5 D24 D6 D7 AE6 MISC TEST1 TEST2 BSEL[0] BSEL[1] BSEL[2] H_DSTBN#3 H_DSTBP#3 H_DINV#3 COMP0 COMP1 COMP2 COMP3 R99 R102 R103 R104 1 1 2 2 BGA479-SKT6-GPU2 R112 H_CPURST# R325 1 DY DY 2 CPU on die PH 55 ohm 39D2R3F-2-GP R328 470R2J-2-GP 54D9R2F-L1-GP 220R2J-L2-GP R378 10KR2J-3-GP H_DPRSLP# Q8 C 3D3V_S0 XDP_DBRESET# 3D3V_S0 150R2F-1-GP 2 XDP_TDO R110 R107 XDP_TMS DY 150R2F-1-GP XDP_TCK R116 XDP_TRST# R115 2 R71 B E R79 CH3904PT-GP PM_DPRSLPVR 15,39 Wistron Corporation 470R2J-2-GP 27D4R2F-L1-GP 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C 680R3F-GP Title All place within 2" to CPU CPU (1 of 2) Size A3 Document Number Rev Garda-5 Date: Wednesday, April 26, 2006 A B Layout Note: Comp0, connect with Zo=27.4 ohm, make trace length shorter than 0.5" Comp1, connect with Zo=55 ohm, make trace length shorter than 0.5" 1D05V_S0 27D4R2F-L1-GP 54D9R2F-L1-GP 27D4R2F-L1-GP 54D9R2F-L1-GP H_DPRSLP# 39 H_DPSLP# 15 H_DPWR# H_PWRGD 15,37 H_CPUSLP# 18 PSI# 39 1D05V_S0 XDP_TDI H_DSTBN#2 H_DSTBP#2 H_DINV#2 C D SA Sheet E of 46 A B C D E VCC_CORE_S0 U53D VCC_CORE_S0 A4 A8 A11 A14 A16 A19 A23 A26 B6 B8 B11 B13 B16 B19 B21 B24 C5 C8 C11 C14 C16 C19 C2 C22 C25 D1 D4 D8 D11 D13 D16 D19 D23 D26 E3 E6 E8 E11 E14 E16 E19 E21 E24 F5 F8 F11 F13 F16 F19 F2 F22 F25 G4 G1 G23 G26 H3 H6 H21 H24 J2 J5 J22 J25 K1 K4 K23 K26 L3 L6 L21 L24 M2 M5 M22 M25 N1 N4 N23 N26 P3 U53C VCC[068] VCC[069] VCC[070] VCC[071] VCC[072] VCC[073] VCC[074] VCC[075] VCC[076] VCC[077] VCC[078] VCC[079] VCC[080] VCC[081] VCC[082] VCC[083] VCC[084] VCC[085] VCC[086] VCC[087] VCC[088] VCC[089] VCC[090] VCC[091] VCC[092] VCC[093] VCC[094] VCC[095] VCC[096] VCC[097] VCC[098] VCC[099] VCC[100] VCCP[01] VCCP[02] VCCP[03] VCCP[04] VCCP[05] VCCP[06] VCCP[07] VCCP[08] VCCP[09] VCCP[10] VCCP[11] VCCP[12] VCCP[13] VCCP[14] VCCP[15] VCCP[16] V6 G21 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21 VCCA B26 VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6] AD6 AF5 AE5 AF4 AE3 AF2 AE2 VCCSENSE AF7 VSSSENSE AE7 VSS[082] VSS[083] VSS[084] VSS[085] VSS[086] VSS[087] VSS[088] VSS[089] VSS[090] VSS[091] VSS[092] VSS[093] VSS[094] VSS[095] VSS[096] VSS[097] VSS[098] VSS[099] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] P6 P21 P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 AF3 AF6 AF8 AF11 AF13 AF16 AF19 AF21 AF24 www.kythuatvitinh.com C171 SCD1U10V2KX-4GP 1 2 1 DY C189 SC4D7U6D3V3KX-GP 1 C167 VCC_CORE_S0 1 2 C440 SC10U10V5KX-2GP C456 SC10U10V5KX-2GP C420 SC10U10V5KX-2GP SCD1U10V2KX-4GP C113 BGA479-SKT6-GPU2 SA Modify 1 Wistron Corporation C455 SC10U10V5KX-2GP SC10U10V5KX-2GP SC10U10V5KX-2GP SC10U10V5KX-2GP C441 C448 C423 1 C454 SC10U10V5KX-2GP C416 SC10U10V5KX-2GP SC10U10V5KX-2GP SC10U10V5KX-2GP SC10U10V5KX-2GP C421 1 C418 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title CPU (2 of 2) Size A3 Document Number Rev Garda-5 Date: Wednesday, April 26, 2006 A B C449 C112 SCD1U10V2KX-4GP VCC_CORE_S0 SCD1U10V2KX-4GP C115 Layout Note: Provide a test point (with no stub) to connect a differential probe between VCCSENSE and VSSSENSE at the location where the two 54.9ohm resistors terminate the 55 ohm transmission line VCCSENSE and VSSSENSE lines should be of equal length Layout Note: R121 100R2F-L1-GP-U C116 SC4D7U6D3V3KX-GP VSS_SENSE 39 C141 SCD1U10V2KX-4GP VCC_SENSE 39 C143 SCD1U10V2KX-4GP C159 SCD1U10V2KX-4GP C78 H_VID0 39SCD01U16V2KX-3GP H_VID1 39 VCC_CORE_S0 H_VID2 39 H_VID3 39 H_VID4 39 H_VID5 39 R122 H_VID6 39 100R2F-L1-GP-U H_VID[0 6] 39 1D05V_S0 HCB1608KF121T30-GP 68.00230.041 C77 SC4D7U6D3V3KX-GP SCD1U10V2KX-4GP BGA479-SKT6-GPU2 1D5V_CPU_S0 L4 1D5V_VCCA_S0 2 1D05V_S0 2 VCC[001] VCC[002] VCC[003] VCC[004] VCC[005] VCC[006] VCC[007] VCC[008] VCC[009] VCC[010] VCC[011] VCC[012] VCC[013] VCC[014] VCC[015] VCC[016] VCC[017] VCC[018] VCC[019] VCC[020] VCC[021] VCC[022] VCC[023] VCC[024] VCC[025] VCC[026] VCC[027] VCC[028] VCC[029] VCC[030] VCC[031] VCC[032] VCC[033] VCC[034] VCC[035] VCC[036] VCC[037] VCC[038] VCC[039] VCC[040] VCC[041] VCC[042] VCC[043] VCC[044] VCC[045] VCC[046] VCC[047] VCC[048] VCC[049] VCC[050] VCC[051] VCC[052] VCC[053] VCC[054] VCC[055] VCC[056] VCC[057] VCC[058] VCC[059] VCC[060] VCC[061] VCC[062] VCC[063] VCC[064] VCC[065] VCC[066] VCC[067] AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20 A7 A9 A10 A12 A13 A15 A17 A18 A20 B7 B9 B10 B12 B14 B15 B17 B18 B20 C9 C10 C12 C13 C15 C17 C18 D9 D10 D12 D14 D15 D17 D18 E7 E9 E10 E12 E13 E15 E17 E18 E20 F7 F9 F10 F12 F14 F15 F17 F18 F20 AA7 AA9 AA10 AA12 AA13 AA15 AA17 AA18 AA20 AB9 AC10 AB10 AB12 AB14 AB15 AB17 AB18 VSS[001] VSS[002] VSS[003] VSS[004] VSS[005] VSS[006] VSS[007] VSS[008] VSS[009] VSS[010] VSS[011] VSS[012] VSS[013] VSS[014] VSS[015] VSS[016] VSS[017] VSS[018] VSS[019] VSS[020] VSS[021] VSS[022] VSS[023] VSS[024] VSS[025] VSS[026] VSS[027] VSS[028] VSS[029] VSS[030] VSS[031] VSS[032] VSS[033] VSS[034] VSS[035] VSS[036] VSS[037] VSS[038] VSS[039] VSS[040] VSS[041] VSS[042] VSS[043] VSS[044] VSS[045] VSS[046] VSS[047] VSS[048] VSS[049] VSS[050] VSS[051] VSS[052] VSS[053] VSS[054] VSS[055] VSS[056] VSS[057] VSS[058] VSS[059] VSS[060] VSS[061] VSS[062] VSS[063] VSS[064] VSS[065] VSS[066] VSS[067] VSS[068] VSS[069] VSS[070] VSS[071] VSS[072] VSS[073] VSS[074] VSS[075] VSS[076] VSS[077] VSS[078] VSS[079] VSS[080] VSS[081] C D SA Sheet E of 46 C U51A H_A#[31 3] 4 H_REQ#[4 0] G28 H26 G27 G30 G29 G26 H28 J28 H25 K28 H29 J29 K24 K25 F29 G25 F26 F28 E29 H27 CPU_A3# CPU_A4# CPU_A5# CPU_A6# CPU_A7# CPU_A8# CPU_A9# CPU_A10# CPU_A11# CPU_A12# CPU_A13# CPU_A14# CPU_A15# CPU_A16# CPU_REQ0# CPU_REQ1# CPU_REQ2# CPU_REQ3# CPU_REQ4# CPU_ADSTB0# H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 M28 K29 K30 J26 L28 L29 M30 K27 M29 K26 N28 L26 N25 L25 N24 L27 CPU_A17# CPU_A18# CPU_A19# CPU_A20# CPU_A21# CPU_A22# CPU_A23# CPU_A24# CPU_A25# CPU_A26# CPU_A27# CPU_A28# CPU_A29# CPU_A30# CPU_A31# CPU_ADSTB1# E H_D#[63 0] CPU_D0# CPU_D1# CPU_D2# CPU_D3# CPU_D4# CPU_D5# CPU_D6# CPU_D7# CPU_D8# CPU_D9# CPU_D10# CPU_D11# CPU_D12# CPU_D13# CPU_D14# CPU_D15# CPU_DBI0# CPU_DSTB0N# CPU_DSTB0P# E28 D28 D29 C29 D30 C30 B29 C28 C26 B25 B27 C25 A27 C24 A24 B26 C27 A28 B28 H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 CPU_D16# CPU_D17# CPU_D18# CPU_D19# CPU_D20# CPU_D21# CPU_D22# CPU_D23# CPU_D24# CPU_D25# CPU_D26# CPU_D27# CPU_D28# CPU_D29# CPU_D30# CPU_D31# CPU_DBI1# CPU_DSTB1N# CPU_DSTB1P# C19 C23 C20 C22 B22 B23 C21 B24 E21 B21 B20 G19 F21 B19 E20 D21 A21 D22 E22 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_DINV#1 H_DSTBN#1 H_DSTBP#1 H_DINV#1 H_DSTBN#1 H_DSTBP#1 CPU_D32# CPU_D33# CPU_D34# CPU_D35# CPU_D36# CPU_D37# CPU_D38# CPU_D39# CPU_D40# CPU_D41# CPU_D42# CPU_D43# CPU_D44# CPU_D45# CPU_D46# CPU_D47# CPU_DBI2# CPU_DSTB2N# CPU_DSTB2P# C18 F19 E19 A18 D19 B18 C17 B17 E17 B16 C15 A15 B15 F16 G18 F18 C16 D18 E18 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_DINV#2 H_DSTBN#2 H_DSTBP#2 H_DINV#2 H_DSTBN#2 H_DSTBP#2 CPU_D48# CPU_D49# CPU_D50# CPU_D51# CPU_D52# CPU_D53# CPU_D54# CPU_D55# CPU_D56# CPU_D57# CPU_D58# CPU_D59# CPU_D60# CPU_D61# CPU_D62# CPU_D63# CPU_DBI3# CPU_DSTB3N# CPU_DSTB3P# E16 D16 C14 B14 E15 D15 C13 E14 F13 B13 A12 C12 E12 D13 D12 B12 E13 F15 G15 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 H_DINV#3 H_DSTBN#3 H_DSTBP#3 H_DINV#0 H_DSTBN#0 H_DSTBP#0 H_DINV#0 H_DSTBN#0 H_DSTBP#0 4 R89 220KR2J-L2-GP D8 15 K NB_RST# D9 K 18,33,35 PM_SUS_STAT# A CH751H-40PT-1GP 1D05V_S0 H_RS#[2 0] H_BREQ#0 H_CPURST# R85 0R0402-PAD TP30 A NB_RST# CH751H-40PT-1GP 4 8,37 NB_PWRGD D25 C11 TPAD30 E11 AH14 A3 E3 RESERVED1 SUS_STAT# SYSRESET# POWERGOOD R87 49D9R2F-GP NB_CPU_COMP_P B11 CPU_COMP_P R86 24D9R2F-L-GP NB_CPU_COMP_N D11 CPU_COMP_N NB_CPVDD H21 CPVDD H20 CPVSS H22 CPU_VREF THERMALDIODE_P THERMALDIODE_N TESTMODE R81 H_DINV#3 H_DSTBN#3 H_DSTBP#3 71.RC410.D0U P.L.:Normal Mode 2 SC1U6D3V2ZY-GP RC410ME-GP R105 4K7R2J-2-GP ATI Modify 1989_DXP3 DY TP29 TPAD30 C92 Wistron Corporation TP33 TPAD30 C104 1 100R2F-L1-GP-U dedicated VIA C4 SC220P50V2JN-3GP through a C111 SC1U6D3V2ZY-GP AH13 AJ13 50mA 1989_DXN3 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C C137 SC470P50V2KX-3GP Title RC410ME (1 of 5) Host I/F Size A3 Document Number Rev Garda-5 Date: Wednesday, April 26, 2006 A B immediately CPVSS need to connect to GND LAYOUT NOTE NB_GTLVREF R84 L5 BLM18BD152SN-GP 68.00143.081 49D9R2F-GP 1D05V_S0 ADDR GROUP RESERVED0 CPU_CPURST# 1D8V_S0 Critical Bead 200ohm 200mA DATA GROUP 2 Buffer Implemented:27K 1D8V_S0 Buffer not Implemented:220K CPU_ADS# CPU_BNR# CPU_BPRI# CPU_DEFER# CPU_DRDY# CPU_DBSY# CPU_DPWR# CPU_LOCK# CPU_TRDY# CPU_HITM# CPU_HIT# CPU_RS0# CPU_RS1# CPU_RS2# DATA GROUP 4 4 F25 F24 E23 E25 G24 F23 G22 E27 F22 E24 D26 H_RS#0 E26 H_RS#1 G23 H_RS#2 D23 H_ADS# H_BNR# H_BPRI# H_DEFER# H_DRDY# H_DBSY# H_DPWR# H_LOCK# H_TRDY# H_HITM# H_HIT# CONTROL H_ADSTB#1 4 AGTL+I/F DATA GROUP www.kythuatvitinh.com MISC PART OF H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 H_ADSTB#0 D DATA GROUP B ADDR GROUP A C D SB Sheet E of 46 A B C D E U51C 11,12 M_B_A[17 0] 11 M_B_DM[7 0] M_B_DM0 M_B_DM1 M_B_DM2 M_B_DM3 M_B_DM4 M_B_DM5 M_B_DM6 M_B_DM7 PART OF AK27 AJ27 AH26 AJ26 AH25 AJ25 AH24 AH23 AJ24 AJ23 AH27 AH22 AJ22 AF28 AJ21 AG27 AJ28 AH21 MEM_A0 MEM_A1 MEM_A2 MEM_A3 MEM_A4 MEM_A5 MEM_A6 MEM_A7 MEM_A8 MEM_A9 MEM_A10 MEM_A11 MEM_A12 MEM_A13 MEM_A14 MEM_A15 MEM_A16 MEM_A17 AJ17 AG15 AE20 AF25 Y27 AB28 R26 R28 MEM_DM0 MEM_DM1 MEM_DM2 MEM_DM3 MEM_DM4 MEM_DM5 MEM_DM6 MEM_DM7 AJ29 AG28 AH30 MEMB_RAS# MEMB_CAS# MEMB_WE# AJ18 AE14 AF22 AE25 W27 AB29 P25 R29 MEM_DQS0P MEM_DQS1P MEM_DQS2P MEM_DQS3P MEM_DQS4P MEM_DQS5P MEM_DQS6P MEM_DQS7P AH17 AF15 AE22 AF26 W26 AB30 R25 R30 MEM_DQS0N MEM_DQS1N MEM_DQS2N MEM_DQS3N MEM_DQS4N MEM_DQS5N MEM_DQS6N MEM_DQS7N AC26 AC25 AF16 AE16 V29 V30 AC24 AC23 AG17 AF17 W29 W28 MEM_CK0N MEM_CK0P MEM_CK1N MEM_CK1P MEM_CK2N MEM_CK2P MEM_CK3N MEM_CK3P MEM_CK4N MEM_CK4P MEM_CK5N MEM_CK5P AH20 AJ20 AE24 AE21 MEM_CKE0 MEM_CKE1 MEM_CKE2 MEM_CKE3 M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63 MEM_DQ0 MEM_DQ1 MEM_DQ2 MEM_DQ3 MEM_DQ4 MEM_DQ5 MEM_DQ6 MEM_DQ7 MEM_DQ8 MEM_DQ9 MEM_DQ10 MEM_DQ11 MEM_DQ12 MEM_DQ13 MEM_DQ14 MEM_DQ15 MEM_DQ16 MEM_DQ17 MEM_DQ18 MEM_DQ19 MEM_DQ20 MEM_DQ21 MEM_DQ22 MEM_DQ23 MEM_DQ24 MEM_DQ25 MEM_DQ26 MEM_DQ27 MEM_DQ28 MEM_DQ29 MEM_DQ30 MEM_DQ31 MEM_DQ32 MEM_DQ33 MEM_DQ34 MEM_DQ35 MEM_DQ36 MEM_DQ37 MEM_DQ38 MEM_DQ39 MEM_DQ40 MEM_DQ41 MEM_DQ42 MEM_DQ43 MEM_DQ44 MEM_DQ45 MEM_DQ46 MEM_DQ47 MEM_DQ48 MEM_DQ49 MEM_DQ50 MEM_DQ51 MEM_DQ52 MEM_DQ53 MEM_DQ54 MEM_DQ55 MEM_DQ56 MEM_DQ57 MEM_DQ58 MEM_DQ59 MEM_DQ60 MEM_DQ61 MEM_DQ62 MEM_DQ63 AJ16 AH16 AJ19 AH19 AH15 AK16 AH18 AK19 AF13 AF14 AE19 AF19 AE13 AG13 AF18 AE17 AF20 AF21 AG23 AF24 AG19 AG20 AG22 AF23 AD25 AG25 AE27 AD27 AE23 AD24 AE26 AD26 AA25 Y26 W24 U25 AA26 Y25 V26 W25 AC28 AC29 AA29 Y29 AD30 AD29 AA30 Y28 U27 T27 N26 M27 U26 T26 P27 P26 U29 T29 P29 N29 U28 T28 P28 N27 MEM_COMPN MEM_COMPP AE29 AJ15 MEM_COMPN MEM_COMPP MEM_CAP2 N30 MEM_CAP2 MEM_CAP1 AJ14 MEM_CAP1 M_B_DQ[63 0] 11 M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7 11 M_CLK_DDR#0 11 M_CLK_DDR0 11 M_CLK_DDR#1 11 M_CLK_DDR1 11 M_CLK_DDR#3 11 M_CLK_DDR3 11 M_CLK_DDR#4 11 M_CLK_DDR4 R336 61D9R2F-GP L=> 2.0V DDR H=> 1.8V DDRII R75 1KR2J-1-GP 1D8V_S3 RC410ME-GP 71.RC410.D0U 1 DY DY L3 HCB1608KF-181-GP 68.00214.051 R70 1KR2J-1-GP DY 2 C74 0R2J-2-GP Bead: 200ohm, 200mA Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C NB_MPVDD 1D8V_S0 DDR_VREF_S3 R68 2 C72 AB26 AA27 MPVDD MPVSS R69 1KR2J-1-GP DY AD28 MEM_VMODE MEM_VREF MEM_ODT0 MEM_ODT1 MEM_RSRV2 MEM_RSRV3 AB27 C413 AG30 AE28 AC30 Y30 MEM_VREF SCD47U10V3KX-3GP M_ODT0 M_ODT1 M_ODT2 M_ODT3 MEM_CS0# MEM_CS1# MEM_CS2# MEM_CS3# C127 11,12 11,12 11,12 11,12 AH29 AG29 AH28 AF29 C73 SCD1U10V2KX-4GP M_CS0# M_CS1# M_CS2# M_CS3# SC4D7U6D3V3KX-GP 11,12 11,12 11,12 11,12 M_CS0# M_CS1# M_CS2# M_CS3# R346 61D9R2F-GP SCD47U10V3KX-3GP M_CKE0 M_CKE1 M_CKE2 M_CKE3 SCD1U10V2KX-4GP 11,12 11,12 11,12 11,12 1 1D8V_S3 11 M_B_DQS#[7 0] M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7 11 M_B_DQS[7 0] M_B_RAS# M_B_CAS# M_B_WE# MEM_B I/F www.kythuatvitinh.com 11,12 11,12 11,12 M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15 M_B_A16 M_B_A17 C82 SC1U6D3V2ZY-GP Title RC410ME (2 of 5) Memory I/F Size A3 Document Number Rev Garda-5 Date: Wednesday, April 26, 2006 A B C D SA Sheet E of 46 A B C D E 3D3V_S0 5V_S0 RN68 SRN10KJ-5-GP NB_PWRGD level-shifted to 5V B 3D3V_S0 G S LCDVDD_ON R480 100KR2J-1-GP 2 13 1 D C185 U51D R492 C8 AVSSDI B8 AVDDQ 250mA H9 PLLVSS PLLVDD J7 TMDS_HPD DDC_DATA 100mALVDDR18A_2 LVDDR18A_1 H8 H7 B3 C3 DACVSYNC DACHSYNC LVSSR_1 LVSSR_2 LVSSR_3 G9 G8 G7 LVDDR18D C7 LVDS_DIGON LVDS_BLON LVDS_BLEN E2 G3 F2 TXCLK_UP TXCLK_UN TXCLK_LP TXCLK_LN F8 F7 F6 G6 B10 RSET 300mA RED GREEN BLUE CLK_MCH_BCLK CLK_MCH_BCLK# R358 10KR2J-3-GP TVCLKIN TPAD30 TP71 SB_OSCIN_1 C466 DUMMY-C2 13 EDID_CLK EDID_CLK 13 EDID_DAT EDID_DAT DY G1 OSCIN J1 K1 CPU_CLKP CPU_CLKN G2 TVCLKIN F1 OSCOUT D2 I2C_CLK C1 I2C_DATA CLK GEN SVID CRT F10 E10 D10 R359 DUMMY-R2 1D8V_S0_LVDDR18A C175 SCD1U10V2KX-4GP 715R3-GP NB_REST R90 150R2F-1-GP DY R120 0R3-0-U-GP 9,14 DAC_VSYNC 9,14 DAC_HSYNC R93 1 R91 150R2F-1-GP OSC14M 1D8V_S0_LPVDD 1D8V_S0 C168 SC1U6D3V2ZY-GP J8 LPVSS SCD1U10V2KX-4GP C169 LPVDD 20mA J2 H3 R96 0R3-0-U-GP C162 SCD1U10V2KX-4GP C194 SC1U6D3V2ZY-GP 1D8V_S0 LVDS_DIGON BL_ON LVDS_BLEN 33 TP69 TPAD30 TXBCLK+ TXBCLKTXACLK+ TXACLK- 13 13 13 13 C174 SC1U6D3V2ZY-GP 3D3V_S0 R92 150R2F-1-GP 14 RED 14 GREEN 14 BLUE H10 C D9 Y F9 COMP E9 DACSCL DACSDA B2 C2 STRP_DATA D1 R97 TV 1150R2F-1-GP R101 TV 1150R2F-1-GP R100 TV 1150R2F-1-GP TV_CRMA 14 TV_LUMA R118 14 4K7R2J-2-GP TV_COMP 14 GMCH_DDCCLK 14 GMCH_DDCDATA 14 STRP_DATA R357 4K7R2J-2-GP 3D3V_S0 71.RC410.D0U R119 4K7R2J-2-GP GMCH_DDCCLK High, E2PROM STRAPING Low, Memory Channel STRAPING 3D3V_S0 3D3V_S0 STRP_DATA:Debug strap DEFAULT:0 RC410ME-GP 1 2 4K7R2J-2-GP DDC_DATA EDID_CLK EDID_DAT Wistron Corporation "DACSCL" This strap select the CPU I/O voltage level 0: mobile CPU Interface(1.4V or below) 1: reserved(Desktop) RN53 SRN4K7J-8-GP 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Q12 B E SIV Modify C R362 1 R123 SB_PWRGD# 37 Title RC410ME (3 of 5) Vedio I/F 2KR2F-3-GP CH3904PT-GP Size A3 Document Number Rev Garda-5 Date: Wednesday, April 26, 2006 A B TMDS_HPD DDC_DATA AVSSQ 1D8V_S0 TPAD30 TP70 TPAD30 TP72 B9 13 13 13 13 13 13 SCD1U10V2KX-4GP 1D8V_S0_PLLVDD 100mA TXAOUT0TXAOUT0+ TXAOUT1TXAOUT1+ TXAOUT2TXAOUT2+ C142 1D8V_S0_AVDDQ E5 F5 D5 C5 E6 D6 E7 E8 2 C193 C164 TXOUT_L0N TXOUT_L0P TXOUT_L1N TXOUT_L1P TXOUT_L2N TXOUT_L2P TXOUT_L3N TXOUT_L3P AVDDDI SB Modify AVSSN D8 13 13 13 13 13 13 C10 TXBOUT0TXBOUT0+ TXBOUT1TXBOUT1+ TXBOUT2TXBOUT2+ AVDD B4 A4 B5 C6 B6 A6 B7 A7 C9 TXOUT_U0N TXOUT_U0P TXOUT_U1N TXOUT_U1P TXOUT_U2N TXOUT_U2P TXOUT_U3N TXOUT_U3P VDDR3_1 VDDR3_2 G5 G4 DY 0R2J-2-GP ATI Modify C170 SC1U6D3V2ZY-GP PART OF 100mA 1 2 C165 C467 Q31 LVDS_DIGON FDN337N-1-GP 3D3V_S0_AVDD_S SCD1U10V2KX-4GP C166 SC1U6D3V2ZY-GP SC2D2U10V3ZY-1GP R98 0R3-0-U-GP SC1U6D3V2ZY-GP SC2D2U10V3ZY-1GP L27 HCB1608KF-181-GP 68.00214.051 1 2 Bead: 200ohm, 200mA 1D8V_S0 Bead: 200ohm, 200mA CH3904PT-GP www.kythuatvitinh.com 1D8V_S0 1D8V_S0 NB_PWRGD_5V 3D3V_S0_VDDR3 SCD1U10V2KX-4GP C188 C156 SC2D2U10V3ZY-1GP SC1U6D3V2ZY-GP ATI Modify C Q30 0R3-0-U-GP R95 0R3-0-U-GP Bead: 26ohm, 600mA E 6,37 NB_PWRGD Bead: R117 200ohm, 200mA 3D3V_S0 C D -1 Sheet E of 46 A B C D E NB Strap pins All pull-up and pull-down resistors are 4.7kohm U51B DY BMREQ# R363 4K7R2J-2-GP R361 4K7R2J-2-GP 3D3V_S0 BMREQ# pulled down if CPU doesn't support BSEL2 3D3V_S0 1D05V_S0 GFX_RX0P GFX_RX0N GFX_RX1P GFX_RX1N GFX_RX2P GFX_RX2N GFX_RX3P GFX_RX3N GFX_RX4P GFX_RX4N GFX_RX5P GFX_RX5N GFX_RX6P GFX_RX6N GFX_RX7P GFX_RX7N GFX_RX8P GFX_RX8N GFX_RX9P GFX_RX9N GFX_RX10P GFX_RX10N GFX_RX11P GFX_RX11N GFX_RX12P GFX_RX12N GFX_RX13P GFX_RX13N GFX_RX14P GFX_RX14N GFX_RX15P GFX_RX15N PART OF GFX_TX0P GFX_TX0N GFX_TX1P GFX_TX1N GFX_TX2P GFX_TX2N GFX_TX3P GFX_TX3N GFX_TX4P GFX_TX4N GFX_TX5P GFX_TX5N GFX_TX6P GFX_TX6N GFX_TX7P GFX_TX7N GFX_TX8P GFX_TX8N GFX_TX9P GFX_TX9N GFX_TX10P GFX_TX10N GFX_TX11P GFX_TX11N GFX_TX12P GFX_TX12N GFX_TX13P GFX_TX13N GFX_TX14P GFX_TX14N GFX_TX15P GFX_TX15N N1 N2 P2 R2 R1 T1 T2 U2 V2 V1 W1 W2 Y2 AA2 AA1 AB1 AB2 AC2 AD2 AD1 AE1 AE2 AF2 AG2 AG1 AH1 AH2 AJ2 AJ3 AJ4 AK4 AJ5 3,4 CH3904PT-GP 3D3V_S0 2 1D05V_S0 R106 4K7R2J-2-GP DY 8,14 DAC_VSYNC R108 C 4K7R2J-2-GP 32 32 PCIE_RXP0 PCIE_RXN0 AF8 AG8 AG6 AG7 GPP_RX0P GPP_RX0N GPP_RX1P GPP_RX1N GPP_TX0P GPP_TX0N GPP_TX1P GPP_TX1N AJ8 PCIE_LAN_TXP0_1 C460 AJ9 PCIE_LAN_TXN0_1 C459 AE6 AF6 SCD1U10V2KX-4GP PCIE_TXP0 SCD1U10V2KX-4GP PCIE_TXN0 32 32 27 27 PCIE_RXP2 PCIE_RXN2 AK7 AJ7 AG4 AH4 GPP_RX2P GPP_RX2N GPP_RX3P GPP_RX3N GPP_TX2P GPP_TX2N GPP_TX3P GPP_TX3N AJ6 PCIE_MC_TXP_2_1 C462 AK6 PCIE_MC_TXN_2_1 C461 AE4 AF4 SCD1U10V2KX-4GP SCD1U10V2KX-4GP 27 27 DY B 1 R114 4K7R2J-2-GP E CPU_SEL0 Q10 3,4 15 15 15 15 CH3904PT-GP PCIE_RX0P_SB PCIE_RX0N_SB PCIE_RX1P_SB PCIE_RX1N_SB CLK_NB_ALINK CLK_NB_ALINK# CLK_NB_GFX CLK_NB_GFX# Select the FSB SPEED VSYNC 15 BMREQ# SB_RX0P SB_RX0N SB_RX1P SB_RX1N SB_TX0P SB_TX0N SB_TX1P SB_TX1N AJ10 AJ11 AK9 AK10 K2 L2 SB_CLKP SB_CLKN PCE_TXSET AK13 PCE_TXSET PCE_ISET AJ12 PCE_ISET M2 M1 GFX_CLKP GFX_CLKN PCE_PCAL AH12 PCE_PCAL PCE_NCAL AG12 PCE_NCAL H2 BMREQ# Freq 0 100MHZ 0 133MHZ 1 166MHZ 0 100MHZ 1 100MHZ 1 1 1 1 2 2 C451 C450 C457 C453 PCIE_TX0P_SB PCIE_TX0N_SB PCIE_TX1P_SB PCIE_TX1N_SB 15 15 15 15 HSYNC PCIE_TX0P_NB SCD1U10V2KX-4GP PCIE_TX0N_NB SCD1U10V2KX-4GP PCIE_TX1P_NB SCD1U10V2KX-4GP PCIE_TX1N_NB SCD1U10V2KX-4GP AG9 AG10 AE9 AF10 RC410ME-GP 71.RC410.D0U R88 82D5R2F-1-GP R347 8K25R2F-1-GP R94 R349 150R2F-1-GP 10KR2F-2-GP BMREQ# PCIE_TXP2 PCIE_TXN2 1D2V_S0 Adjust PCI-E Amp R->Small then Amp->Large 1 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title RC410ME (4 of 5) PCI-E & Strap Size A3 Document Number Rev Garda-5 Date: Wednesday, April 26, 2006 A CPU_SEL1 E Q11 C 2 4K7R2J-2-GP 1 R111 B 1 8,14 DAC_HSYNC R109 4K7R2J-2-GP 2 www.kythuatvitinh.com R113 4K7R2J-2-GP J5 J4 K4 L4 L6 L5 M5 M4 N4 P4 P6 P5 R5 R4 T4 T3 U6 U5 V5 V4 W4 W3 Y6 Y5 AA5 AA4 AB4 AB3 AC6 AC5 AD5 AD4 B C D SA Sheet E of 46 A B C D E U51F C98 SCD1U10V2KX-4GP SCD1U10V2KX-4GP C95 C96 DY 2.25A C182 C183 C178 C152 Bead: 50ohm, 3A At least 100u*1(ESR:INT_PIRQE# GNT:PCI_GNT1# REQ:PCI_REQ1# MINIP MINIP C204 SC4D7U10V5ZY-3GP 15,19,23,25,28 PCI_AD[0 31] 126 PCISLT124-5-GP 18 19 21 18,20,33,37,43 PM_SLP_S3# 62.10043.221 2nd source: 62.10032.061 3.3VIN 3.3VOUT 1.5VIN 1.5VOUT AUXIN AUXOUT 12 11 17 15 3D3V_S0 3D3V_NEW_S0 1D5V_NEW_MINI_S0 1D5V_NEW_S0 3D3V_S5 3D3V_NEW_LAN_S5 GND NC#16 NC#14 NC#13 NC#5 NC#4 STBY# RCLKEN NEW OC# THERMAL_PAD 16 14 13 TPS2231RGP-GP 74.02231.073 3D3V_S0 3D3V_NEW_S0 1D5V_NEW_S0 3D3V_NEW_LAN_S5 C543 2 Wistron Corporation 1 2 NEW C259 Place them Near to Connector D SCD1U16V2ZY-2GP C NEW C539 SCD1U16V2ZY-2GP B NEW C538 SC1U6D3V2ZY-GP Place them Near to Chip A NEW C268 SCD1U16V2ZY-2GP C472 SCD1U16V2ZY-2GP NEW DY SC1U6D3V2ZY-GP 1 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title Size A3 MINI-PCI/NEW Card Document Number Rev Garda5 Date: Wednesday, April 26, 2006 SB Sheet E 32 of 46 B C KCOL[1 16] 34 KROW[1 8] 34 3D3V_AUX_S5 LAD0 LAD1 LAD2 LAD3 18 LFRAME# LCLK SERIRQ SCL1 SDA1 SCL2 SDA2 2N7002DW-7F-GP SMBC_G792 KBC_SCL2 KBC_SDA2 KBC_SDA2 GPIO29 GPIO28 GPIO27 GPIO26 GPIO25 GPIO24 GPIO23 GPIO22 GPIO21 GPIO20 GPIO19 GPIO18 GPIO17 GPIO16 GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO09 GPIO08 GPIO07 GPIO06 GPIO05 GPIO04 GPIO03 GPIO02 GPIO01 GPIO00 155 149 148 119 118 109 108 107 106 105 86 85 75 70 69 63 62 55 54 48 22 21 20 12 11 GPIO0F GPIO0E GPIO0D GPIO0C GPIO0B GPIO0A 41 28 27 25 24 23 GPIO1F GPIO1E GPIO1D GPIO1C GPIO1B GPIO1A 98 97 94 93 92 91 GPIOI2D GPIO2F GPIO2E GPIO2C GPIO2B GPIO2A 168 175 171 165 162 156 KBC_MATRIX1# 34 KBC_MATRIX0# 34 CCD_ON 13 BT_BTN# 13 AD_OFF A20 E51TXD E51RXD E51CS# TP17 BATA_SCL BATA_SDA KBC_SCL2 KBC_SDA2 163 164 169 170 160 158 KROW1 KROW2 KROW3 KROW4 KROW5 KROW6 KROW7 KROW8 71 72 73 74 77 78 79 80 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 KSO16 KSO17 KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 161 U48 20 U17 KB Matrix LPC RN41 SRN10KJ-5-GP TPAD28 KBC_SCL2 SMBC_G792 SMBD_G792 SMBD_G792 20 3D3V_AUX_S5 3D3V_AUX_S5 R36 100KR2J-1-GP 45 TP19 TPAD28 TP16 15,19,35,36 LPC_LFRAME# 15,19 SB_CLK33_KBC 15,25,28,32,35 INT_SERIRQ 15 14 13 10 RN43 SRN10KJ-5-GP C40 SC18P50V2JN-1-GP LPC_LAD0 LPC_LAD1 LPC_LAD2 LPC_LAD3 82.10026.021 KBC_XI non 1394 15,35,36 LPC_LAD[0 3] VCCBAT 16 34 45 123 136 157 166 95 VCC VCC VCC VCC VCC VCC VCC VCCA SCD1U16V2ZY-2GP C386 X1 4RESO-32D768KHZ-GP XCLKO XCLKI KCOL1 KCOL2 KCOL3 KCOL4 KCOL5 KCOL6 KCOL7 KCOL8 KCOL9 KCOL10 KCOL11 KCOL12 KCOL13 KCOL14 KCOL15 KCOL16 C388 49 50 51 52 53 56 57 58 59 60 61 64 65 66 67 68 153 154 SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP 3D3V_AUX_S5 C36 SC22P50V2JN-4GP 5V_S0 L20 3D3V_KBC_AUX_S5 BLM11P600S SCD1U16V2ZY-2GP 68.00082.011 C375 C370 C379 E 5V_S0 KBC_XO 3D3V_AUX_S5 1 SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP C382 C43 2 C387 SCD1U16V2ZY-2GP 1 SCD1U16V2ZY-2GP D A R481 10KR2J-3-GP TP15 5V_S0 SRN47J-4-GP 2 34 34 PS/2 DA0 DA1 DA2 DA3 DA4 DA5 DA6 DA7 GPWU0 GPWU1 GPWU2 GPWU3 GPWU4 GPWU5 GPWU6 GPWU7 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 81 82 83 84 87 88 89 90 71.03910.C0G 99 100 101 102 42 47 174 EXT_FWH# 36 R307 1KR2J-1-GP 26 29 30 44 76 172 176 PWM7 PWM6 PWM5 PWM4 PWM3 PWM2 PWM1 PWM0 A5 100KR2J-1-GP EBUTTON# 27 BATA_IN# 44,45 1KR2J-1-GP SA Rework KBRCIN# KA20GATE R37 1KR2J-1-GP SRN1KJ-7-GP ECSMI#_KBC 18 RF_ON/OFF# 27,32 PM_CLKRUN# 15,23,25,28,32,35 BLON_OUT 13 NUM_LED# 13 BLUETOOTH_EN 22 DC_BATFULL# 13 BT_LED# 13 WLAN_TEST_LED 27 EMAIL_LED# 27 CHRGER_LED# 13 3D3V_S5 D23 CH751H-40PT-1GP VCC3VSB CRT_IN# 14 AMP_SHUTDOWN_KBC 31 PLT_RST1# 15,21,27,32,35,36 BL_ON PSW_CLR# 34 45 45 A5 for EMWB==>High=Enable,Low=Disable GPIO05 for Clock test mode==>High=test Mode,Low=32KHz clock in normal running(Recommended) GPIO06 for DPLL test mode==>High=Test Mode,Low=Normal operation(Recommended) K D22 CH751H-40PT-1GP 3D3V_AUX_S5 A SB Modify RN44 SB Modify CHG_4D35V# E KBC_MATRIX1# KBC_MATRIX0# DY B R285 10KR2J-3-GP Q21 CH3906PT-GP PURE_HW_SHUTDOWN# 20,37 DY SRN10KJ-5-GP Wistron Corporation PLANARID2 34 PLANARID1 34 PLANARID0 34 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title KBC KB3910 22 Size A3 USB_EN# Document Number Rev C D SB Garda-5 Date: Wednesday, April 26, 2006 B R478100KR2J-1-GP R47910KR2J-3-GP BL_ON ECSCI#_KBC 18 TP18 BATA_SCL BATA_SDA 3D3V_S5 R289 10KR2J-3-GP R28 1KR2J-1-GP C591 C366 A1 for the internal pull-up resistors on XIOCS[F:0] pins==>High=enable,Low=Disable A4 for DMRP==>High=Disable,Low=Enable A 3D3V_AUX_S5 C TP13 TP12 TP7 18 PM_PWRBTN# 18 RSMRST#_KBC 32,37 S5_EN 44 CHG_V_PWM 13 BRIGHTNESS 44 CHG_I_PWM 18,20,32,37,43 PM_SLP_S3# 27 EC_PWRBTN# 44 AC_IN# 34 LID_CLOSE# 44 3D3V_AUX_S5 C381 SC1U6D3V2ZY-GP SRN8K2J-3-GP SC10U6D3V5MX-3GP 1 TP5 TP14 SC1U10V2KX-GP R27 10KR2J-3-GP R294 100KR2J-1-GP DY KB3910SF-2-GP TP8 EC_RST# 1KR2J-1-GP TP4 S5_EN 3S R26 3S2P_I KBC_BEEP RSMRST#_KBC 30 ECSWI# AD_OFF 18 18 DY R29 PSW_CLR# 18 RN2 2 WIRELESS_BTN# 13 KBCRST# RN42 RN3 3D3V_AUX_S5 PSDAT3 PSCLK3 PSDAT2 PSCLK2 PSDAT1 PSCLK1 AMP_MUTE_KBC 31 PROGRAM# 27 117 116 115 114 111 110 1394 TDATA TCLK CAP_LED# 13 PWRLED# 13 TP6 RICOH_DETECT R482 10KR2J-3-GP 1394 Detect Pin H:non 1394 L:has 1394 K R32 10KR2J-3-GP PM_SUS_STAT# 6,18,35 TP9 A A1 KB3910 RICOH_DETECT SB Modify TP10 DUMMY-R2 R33 X-bus ROM CHG_4S1P R30 DY 0R2J-2-GP A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 STDBY_LED# 13 GBUS_GRST# 28 INTERNET# 27 MAIL# 27 PM_SLP_S5# 18,42,43 GND GND GND GND GND GND 124 125 126 127 128 131 132 133 143 142 135 134 130 129 121 120 113 112 104 103 17 35 46 122 137 167 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 AGND BATGND 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 96 159 D0 D1 D2 D3 D4 D5 D6 D7 A[0 19] 3D3V_AUX_S5 R308 138 139 140 141 144 145 146 147 ECRST# ECSCI# 36 KBC_D0 KBC_D1 KBC_D2 KBC_D3 KBC_D4 KBC_D5 KBC_D6 KBC_D7 43 40 39 38 37 36 33 32 KBC_D[0 7] RD# WR# MEMCS# IOCS# 19 31 TP11 36 150 151 173 152 www.kythuatvitinh.com 36 KBCBIOS_RD# 36 KBCBIOS_WE# 36 KBCBIOS_CS# KBCBIOS_RD# KBCBIOS_WE# KBCBIOS_CS# Sheet E 33 of 46 Internal KeyBoard Connector 33 KROW[1 8] G70 33 KCOL[1 16] GAP-OPEN KB1 ON SW6 33 PSW_CLR# PSW_CLR# 33 KBC_MATRIX0# 33 KBC_MATRIX1# DY NC#26 C01 C02 C03 R01 R02 R03 C04 R04 R05 R06 R07 R08 R09 C05 R10 C06 C07 R11 R12 C08 R13 R14 R15 R16 NC#25 NC#27 SW-DIP-4-2-U2-GP Keyboard matrix ( from vendor ) US Eur Jap Ohter MATRIXID0# 1 MATRIXID1# 1 0 26 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 27 KROW1 KROW2 KROW3 KCOL1 KCOL2 KCOL3 KROW4 KCOL4 KCOL5 KCOL6 KCOL7 KCOL8 KCOL9 KROW5 KCOL10 KROW6 KROW7 KCOL11 KCOL12 KROW8 www.kythuatvitinh.com KCOL13 KCOL14 KCOL15 KCOL16 ACES-CON25-GP COVER SWITCH 3D3V_AUX_S5 PSW_CLR# Low Active - ON NC - ON KBC_MATRIX1 - ON KBC_MATRIX2 - ON 20.K0197.025 2nd source: 20.K0198.025 25 K/B R7 100KR2J-1-GP LID_CLOSE# 33 2 RN49 33 33 SRN33J-5-GP-U TDATA TCLK TP_DATA TP_CLK SCROLL KEY EC62 TPAD1 TP_SCROLL_LEFT PLANARID2 PLANARID1 PLANARID0 2 R298 100KR2J-1-GP DY PLANARID2 PLANARID1 PLANARID0 SW-TACT-59-GP-U1 R301 100KR2J-1-GP Planar ID(2,1,0) SA: 0,0,0 SB: 0,0,1 SC: 0,1,0 R296 100KR2J-1-GP SD: 0,1,1 ACES-CON12-GP 20.K0174.012 2nd source: 20.K0185.012 ERC3 SRC100P50V-2-GP DY R299 100KR2J-1-GP 12 T/P R297 100KR2J-1-GP 62.40009.431 33 33 33 DY 62.40009.431 DY TP_SCROLL_DOWN SCRL4 SW-TACT-59-GP-U1 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title KEYBOARD/TOUCHPAD 62.40009.431 62.40009.431 SW-TACT-59-GP-U1 R300 100KR2J-1-GP SW-TACT-59-GP-U1 DY DY 62.40009.431 3D3V_AUX_S5 SW-TACT-59-GP-U1 TP_RIGHT RIGHT1 EC65 SC100P50V2JN-3GP TP_SCROLL_RIGHT SCRL3 SC100P50V2JN-3GP 62.40009.431 TP_SCROLL_LEFT SCRL2 1 EC66 2 SW-TACT-59-GP-U1 TP_LEFT 13 DY DY LEFT1 14 12 11 10 TP_SCROLL_RIGHT TP_SCROLL_UP TP_SCROLL_DOWN TP_LEFT TP_RIGHT EC63 SC100P50V2JN-3GP SC100P50V2JN-3GP TP_SCROLL_UP SCRL1 EC69 SCD1U10V2KX-4GP EC70 RN47 SRN10KJ-5-GP SCD1U10V2KX-4GP 62.40010.161 SW-TE-ML-V-T-GP TOUCH PAD 5V_S0 5V_S0 C7 SC1KP16V2KX-GP 1 100R2F-L1-GP-U 2 1 R6 NP1 2 NP2 CVR1 Size A3 Document Number Rev Garda-5 Date: Wednesday, April 26, 2006 SA Sheet 34 of 46 D D LPC_LAD0 LPC_LAD1 LPC_LAD2 LPC_LAD3 LPC_LAD[0 3] 15,33,36 LPC_LDRQ0# 15 PLT_RST1# 15,21,27,32,33,36 www.kythuatvitinh.com INT_SERIRQ 15,25,28,32,33 LPC_LFRAME# 15,19,33,36 3D3V_S0 1 43 25 C445 C458 PCLK_SIO_RC CLK14_SIO_RC DUMMY-C2 DUMMY-C2 VSS VSS VSS 42 33 37 39 41 18 26 29 31 2 NC#42 NC#33 NC#37 NC#39 NC#41 NC#4 NC#18 NC#26 NC#29 NC#31 23 34 PC87381-VBH-GP B IRRX1 IRSL0 IRTX B IRRX1 IRRX2_IRSL0/GPIO17 IRTX 71.87381.A0G 3D3V_S0 R350 VISHAY FIR/CIR Module C306 SCD1U16V2ZY-2GP IRTX IRRX1 IRSL0 LPCPD# R351 10KR2J-3-GP DUMMY-R2 PM_SUS_STAT# 6,18,33 Layout Guide: (1) FIR_3D3V : 30 mils, (2) C583, C581 close to U32 VCC2/IRED_ANODE IRED_CATHODE TXD RXD SD SIO VCC1 MODE GND FIR-TFDU6102-GP G49 PM_CLKRUN# 15,23,25,28,32,33 SIO U41 SIO C305 SIO SCD1U16V2ZY-2GP Place C581 ,C583 near Pin1 and Pin6 C304 SIO SC10U10V5ZY-1GP 3D3V_S0 A Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C 56.15001.051 Title IR_GND SIO 87381 / FIR GAP-CLOSE Size A3 IR_GND Document Number Rev SA Garda-5 Date: Wednesday, April 26, 2006 C R352 DUMMY-R2 DUMMY-R2 SIO PC87381 SIO A R348 CLKIN LCLK 16 27 28 30 LDRQ#/XOR_OUT LRESET# SERIRQ LFRAME# CTS1# DCD1# DSR1# RI1# SIN1 VCORF DTR1#_BOUT1/BADDR RTS1#/TRIS# SOUT1/TEST# SIO Connecting a 10 K external pull-down resistor makes the base address sample low, setting the Index-Data pair at 2Eh-2Fh 32 36 38 40 44 45 46 VCORF 10 BADRR_STRAP 47 48 R355 10KR2J-3-GP LAD0 LAD1 LAD2 LAD3 24 35 VDD VDD VDD U54 1 SIO SB_CLK33_SIO 15,19 C463 SCD1U16V2ZY-2GP SIO GPIO00 GPIO01 GPIO02 GPIO03 GPIO04 GPIO20 GPIO21/LPCPD# CLKRUN#/GPIO22 GPIO23 RESERVED/GPO24 C158 11 12 13 14 15 17 21 19 22 20 1 2 SC1U6D3V2ZY-GP SIO SCD1U16V2ZY-2GP C452 SIO C SCD1U16V2ZY-2GP CLK14_SIO C190 Sheet 35 of 46 A B C D E GOLDEN FINGER FOR DEBUG BOARD 1D05V_S0 LPC_LAD[0 3] 3D3V_S0 15,33,35 5V_S0 5V_S0 U37 PLT_RST1# LPC_LFRAME# 15,21,27,32,33,35 PLT_RST1# 15,19,33,35 LPC_LFRAME# RN63 SRN10KJ-5-GP SB_CLK33_FWH 15,19 SB_CLK33_FWH FWH_INIT# R428 100R2J-2-GP LPC_LAD3 LPC_LAD2 LPC_LAD1 LPC_LAD0 EXT_FWH# B DY A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 PLT_RST1# LPC_LFRAME# SB_CLK33_FWH FWH_INIT# LPC_LAD3 LPC_LAD2 LPC_LAD1 LPC_LAD0 EXT_FWH# FWH_INIT# C Q28 CH3904PT-GP PCLKFWH www.kythuatvitinh.com E 15 SB_FWH_INIT# DY 33 EXT_FWH# C533 SC10P50V2JN-4GP 3D3V_S0 3D3V_S0 FOX-GF30 ZZ.GF030.XXX 3 Boot Device must have ID[3:0] = 0000 Has internal pull-down resistors All may be left floated FPET7 Elec P3-46 3D3V_AUX_S5 U49 33 KBCBIOS_CS# 33 KBCBIOS_RD# 33 KBCBIOS_WE# A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 26 28 11 47 12 CE# OE# WE# BYTE# RESET# Q15/A-1 Q14 Q13 Q12 Q11 Q10 Q9 Q8 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 45 43 41 39 36 34 32 30 44 42 40 38 35 33 31 29 RY/BY# 15 NC#14 NC#13 NC#10 NC#9 14 13 10 GND GND 46 27 A0 KBC_D7 KBC_D6 KBC_D5 KBC_D4 KBC_D3 KBC_D2 KBC_D1 KBC_D0 KBC_D[0 7] 33 TOP VIEW A15 (B1) A14 (B2) A[0 19] VCC 16 17 48 18 19 20 21 22 23 24 25 33 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 37 A2 (B14) A1 (B15) MX29LV800CBTC-GP 72.29800.0F9 (BOTTOM VIEW) 1 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title BIOS ROM Size A3 Document Number Rev Garda-5 Date: Wednesday, April 26, 2006 A B C D SA Sheet E 36 of 46 1D05V_S0 3D3V_S5 3D3V_S5 3D3V_AUX_S5 10 H_PWRGD C 2S5_EN_3 1KR2J-1-GP D7 Q7 CHT2222APT-GP A 1D8V_S5 S5_EN_2 1 R320 10KR2J-3-GP S5_EN 32,33 R366 TPS51120_EN1_5 D TPS51120_EN1_5 41 C348 SC4700P50V2KX-1GP SHUTDOWN_S5 1 G T(soft)=1.736ms 1D2V_EN 42 TSAHCT125PW-GP R267 1MR2J-1-GP Q19 2N7002PT-U 84.27002.F31 S SB_PWRGD 18 TSLCX14MTCX-1-GP 3D3V_S5 R364 330R2J-3-GP SB_PWRGD# TSLCX08MTCX-GP G 14 TPS51120_EN2_3D3 41 C353 SC4700P50V2KX-1GP S TSLCX14MTCX-1-GP C470 DUMMY-C3 NB_PWRGD TPS51120_EN2_3D3 Q20 2N7002PT-U 84.27002.F31 U27A 14 U28A SB_PWRGD IS 180MS AFTER NB_PWRGD D T(soft)=1.736ms 3D3V_S5 C469 SC1U10V2KX-GP TSLCX14MTCX-1-GP NB_PWRGD_N 11 12 C8 U27B 14 270KR2F-GP U1D 13 14 C SCD1U10V2KX-4GP E Q2 CHT2222APT-GP 3D3V_S5 U27C C398 SCD1U10V2KX-4GP 2 1KR2J-1-GP 5V_S0 R9 100KR2J-1-GP B 470KR2F-GP R10 14 20,33 www.kythuatvitinh.com 1D8V_S0 PURE_HW_SHUTDOWN# CH751H-40PT-1GP 3D3V_S0 R13 NB_PWRGD K E B SHUTDOWN_S5 R322 1D2V_S0 should not exceed 1D8V_S0 by more than 0.6V 3D3V_S5 DY C390 SCD1U10V2KX-4GP R365 100KR2J-1-GP 20 G792_PWROK CHT2222APT-GP Q6 B C 4,15 R314 10KR2J-3-GP 73.07408.02B R323 100KR2J-1-GP TSLCX08MTCX-GP TSLCX08MTCX-GP NB_PWRGD 6,8 E PM_THRMTRIP-I# VTT_VRM_PG 11 12 13 VGATE_PWRGD U28D 14 14 PM_SLP_S3# 18,39 VGATE_PWRGD R310 56R2J-4-GP U28C Aux Power S Q3 2N7002PT-U 84.27002.F31 G 18,20,32,33,43 PM_SLP_S3# S U12 S S S G D D D D AO4422-1-GP 1D8V_S0 1D8V_S3 U55 S S S G D D D D IRF7805ZPBF-GP 84.07805.A37 SCD01U16V2KX-3GP DY2 U47 100mA OUTPUT INPUT SENSE FEEDBACK SHUTDOWN VO TAP GND ERROR# OUTPUT 74.02951.F31 LP2951CDR2G-GP 2 3D3V_S5 A 1 K D6 MMGZ5242BPT-GP 3D3V_S0 SA Modify 2 G D 1 Q4 2N7002PT-U 84.27002.F31 R22 169KR2F-1-GP DCBATOUT C373 C378 C380 200KR3F-GP D R21 100KR2J-1-GP SCD1U25V3KX-GP G 330KR2F-L-GP 3D3V_AUX_S5 SC2D2U6D3V5KX-1GP RUN_PWR_CTLR C34 R23 47KR2J-2-GP R286 SA Rework AO4422-1-GP 84.04422.B37 84.00610.C31 R24 D D D D D S Z_12V 10KR2J-3-GP R25 SCD1U25V3KX-GP U11 S S S G C367 SC1U50V5ZY-1-GP R284 100KR2F-L1-GP DY Q5 TP0610K-T1-GP DCBATOUT C33 SCD1U16V2ZY-2GP Run Power 5V_S5 5V_S0 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title RUN and AUX POWER Size A3 Document Number Rev Garda-5 Date: Wednesday, April 26, 2006 SA Sheet 37 of 46 A B C D TPS51124 1D8V/1D05V CPU_CORE Intersil ISL6262 VID Setting H_VID0 H_VID1 VID2(I / 1.05V) H_VID3 VCC 1D8V (O) 6262_PWRGOOD CLK_EN# DCBATOUT_TPS51124 1D05V(O) Output Power VID6(I / 1.05V) TPS51124_EN1 VCC_CORE_PWR(O) Input Signal VCC_CORE_S0(Imax=48A) PM_DPRSLPVR 3D3V_S5 VSS_SENSE INPUT OUT 1D5V_CPU_S0 EN2 PSI# (I / 3.3V) PGD_IN (I / 3.3V) PGOOD1 CPUCORE_ON DPRSTP# (I / 3.3V) APL5312 Output Signal CPUCORE_ON DPRSLPVR (I / 3.3V) 1D5V_S0 PGOOD2 1D5V_NEW _MINI_S0 3D3V_S5 INPUT 3D3V_S0 APL5332 Input Signal 1D05V_S0 VCC(I) CHGON#/OFF VCC(I) BT_TH Output Signal ICTL BATT PKPRES ACOK 1D2V_S3 INPUT AC_IN OUT 1D05V_S0 APL5912-KAC-GP AD+ Input Signal DDR_VREF_S0 Output Power ACIN BT+ VOUT (O) TPS51120 5V/3D3V TPS51120_EN2_3D3 BT+SENSE VCC(I) Input Power TPS51120_EN1_5 RTN(I / Vcore) CHARGER MAX8725 5V_S0 OUT VSEN(I / Vcore) Input Power DCBATOUT_6262 1D5V_S0 Voltage Sense VCC_SENSE 1D8V_S5 1D05V_S0 (7A) EN1 TPS51124_EN2 OUT www.kythuatvitinh.com CPUCORE_ON INPUT Input Signal VID5(I / 1.05V) H_VID6 3D3V_S5 1D8V_S0 (7A) APL5308-18DC-GP VIN VID4(I / 1.05V) H_VID5 H_DPRSTP# CLK_EN#(O) 1D8V_S5 Output Power VID3(I / 1.05V) H_VID4 PSI# PGOOD(OD / 3.3V) VID1(I / 1.05V) H_VID2 Input Power 5V_S5 Output Signal VID0(I / 1.05V) E 5V_S5 INPUT OUT DDR_VREF_S0 DCBATOUT VOUT (O) TPS51100DGQR-GP Output Signal PGOOD1(OD / 5V) CPUCORE_ON PGOOD2(OD / 5V) CPUCORE_ON 3D3V_AUX_S5 DCBATOUT INPUT OUT 3D3V_AUX_S5 EN1 Output Power 5V(O) 5V_DC_S5 (6A) AD_OFF Input Power 3D3V(O) 3D3V_DC_S5 (5A) Input Signal (I) Input Power DCBATOUT_TPS51120 LP2951ACM Adapter EN2 AD_JK VIN 5V_AUX_S5 VCC(I) Output Signal (O) AD_IN Output Power VCC(O) AD+ Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C VCC(I) Title Power Block Diagram Size A3 Document Number Rev Garda-5 Date: Wednesday, April 26, 2006 A B C D SA Sheet E 38 of 46 DCBATOUT 3D3V_S0 R321 10R2J-2-GP R61 10R2J-2-GP R40 1K91R3F-GP 2 0R0402-PAD 49 D GND PGOOD 3V3 VIN VCC 21 GND_T 6262_UGATE1 35 UGATE1 36 6262_BOOT1 BOOT1 R64 R41 0R0402-PAD 6262_PSI# 2 6262_PHASE1 40 www.kythuatvitinh.com 6262_AGND R341 2NTC-470K-1-GP C48 SCD01U16V2KX-3GP 6262_AGND 470K /0402 size Place close to phase chocke If NTC=330Kohm, R10=8.66K H_VID0 R65 H_VID1 R63 H_VID2 R62 H_VID[0 6] H_VID3 R59 H_VID4 R58 H_VID5 R53 H_VID6 R52 41,42,43 CPUCORE_ON R49 4,15 PM_DPRSLPVR 6262_NTC R48 H_DPRSLP# R46 CLK_EN# R45 1 1 1 1 1 C50 6262_SOFT7 SCD015U25V3KX-GP 6262_VID0 0R0402-PAD 0R0402-PAD 0R0402-PAD 0R0402-PAD 0R0402-PAD 0R0402-PAD 0R0402-PAD 0R0402-PAD 0R0402-PAD 0R0402-PAD 0R0402-PAD 37 5V_S5 DY NTC R312 VID0 C69 38 VID1 UGATE2 6262_VID2 39 VID2 BOOT2 6262_VID3 40 VID3 6262_VID4 41 VID4 27 6262_VID5 42 VID5 6262_VID6 43 VID6 6262_CORE_ON 44 VR_ON PHASE2 28 LGATE2 30 6262_DPRSTP# 46 DPRSTP# 6262_CLKEN# 47 CLK_EN# 6262_VDIFF SC470P50V2KX-3GP 13 1R2J-GP 6262_ISENN1 40 SC4D7U6D3V3KX-GP 6262_UGATE2 C 40 0R3-0-U-GP C71 SCD22U25V3ZY-GP 6262_PHASE2 40 6262_LGATE2 3K65R3F-GP R74 40 6262_VSUM DPRSLPVR R73 C68 SCD22U10V3KX-2GP C49 25 SC1000P50V3JN-GP DY 6262_AGND OCSET 6262_OCSET VSUM 19 6262_VSUM 10KR2F-2-GP 6262_ISENP2 40 6262_ISENN2 40 R66 0R2J-2-GP R72 1R2J-GP OCP>=50A R304 10KR2F-2-GP VDIFF B SA Modify R305 4K42R2F-GP 6262_AGND 2 Place close to phase chocke 17 DFB DROOP R342 NTC-10K-9-GP SA Modify 18 6262_VO R44 1KR2F-3-GP U19 6262_DFB C392 6262_DROOP R51 11KR2F-L-GP C399 SCD22U10V3KX-2GP 6262_AGND C395 SCD01U50V3KX-4GP 6262_VSEN SCD01U16V2KX-3GP SCD01U16V2KX-3GP C396 When test without cpu, R183 & R184 change to ohms If VCC_SENSE and VSS_SENSE pins have pulled resistors to VCC_CORE_S0 ==> Remove R183/R184 6262_RTN 0R2J-2-GP PH R316 VCC_SENSE 2 0R2J-2-GP 16 74.06262.073 PL A VW VSEN 6262_VW SC47P50V3JN-GP 14 RTN C46 R319 ISL6262CRZ-T-GPU VO Switching Frequency=300KHz VSS_SENSE COMP C57 6262_COMP10 C58 R50 2K61R3F-GP 2C52 SC220P50V2KX-3GP FB 15 11 C45 SCD033U16V3KX-GP 61K9R2F-GP 6262_FB R306 FB2 SCD068U16V3KX-GP 6262_FB212 2KR2F-3-GP DY SCD22U10V3KX-2GP R43 1 B 1 R339 23 6262_ISEN2 ISEN2 45 40 29 PGND2 6262_DPRSLP SCD22U10V3KX-2GP 6262_ISENP1 DY 26 6262_BOOT2 R67 21K82R2F-1-GP 1K4R2F-1-GP C51 31 PVCC C409 5V_S0 0R2J-2-GP R333 0R0402-PAD R334 SOFT NC R313 VR_TT# 6262_VID1 6262_VSUM R337 3K65R3F-GP R338 10KR2F-2-GP R335 0R2J-2-GP 24 6262_ISEN1 ISEN1 4K02R3F-GP RBIAS 40 R340 33 CPU_PROCHOT# PGND1 6262_RBIAS 147KR2F-GP LGATE1 PGD_IN 1 R311 6262_AGND 6262_PGD_IN 2 0R0402-PAD 6262_LGATE1 1 R318 32 CPUCORE_ON C C70 SCD22U25V3ZY-GP 34 PHASE1 PSI# 40 0R3-0-U-GP 6262_AGND PSI# VGATE_PWRGD 18,37 SC1U10V3KX-3GP R42 22 C64 C61 SCD01U50V3KX-4GP 48 D 20 6262_AGND 2 PGOOD Power good open-drain output Will be pulled up externally by a 680 resistor to VCCP or 1.9k to 3.3V 1 R324 0R2J-2-GP DY 5V_S0 5V_S5 R47 2K55R3F-GP G43 Load Line C55 6262_VO A GAP-CLOSE-PWR 6262_AGND Wistron Corporation SC180P-GP 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C 6262_AGND Title CPU Vcore Power_1 Size A3 Document Number Rev Garda-5 Date: Wednesday, April 26, 2006 SA Sheet 39 of 46 DCBATOUT SB Modify D EC33 SCD1U25V3ZY-1GP SC10U25V6KX-1GP 2 C79 1 C81 SC10U25V6KX-1GP D D D D U23 IRF7807ZPBF-GP C163 SC10U25V6KX-1GP DY C593 SC10U25V6KX-1GP D S S S G Panasonic ETQP4LR36WFC 10*11.5*4mm 0.34uH / 24A DCR=1.1mohm 39 39 TC8 C76 DYSCD1U25V3ZY-1GP 2 TC5 SE330U2VDM-L-GP S S S G S S S G 6262_ISENN1 6262_ISENP1 TC9 SE330U2VDM-L-GP G74 GAP-CLOSE-PWR G75 GAP-CLOSE-PWR U22 2 IRF7831TRPBF-GP IRF7831TRPBF-GP D D D D U21 Id=30A Qg=8~11nC, Rdson=14.4~18mohm AG3-SB TC4 L-D36UH-1-GP 1 6262_LGATE1 SE330U2VDM-L-GP 6262_PHASE1 39 39 L21 SE330U2VDM-L-GP 6262_UGATE1 D D D D C Iomax=44A OCP>=88A VCC_CORE_S0 www.kythuatvitinh.com 39 C KEMET 330uF / 3V / V size ESR=9mohm / Iripple=3.7A S S S G DY SC10U25V6KX-1GP C173 L-D36UH-1-GP 2 G77 GAP-CLOSE-PWR G76 GAP-CLOSE-PWR U26 S S S G S S S G IRF7831TRPBF-GP U25 Id=46A Qg=15~21nC, Rdson=6.9~8.6mohm D D D D D D D D IRF7831TRPBF-GP AG3-SB TC7 TC6 SE330U2VDM-L-GP 6262_LGATE2 39 L22 6262_PHASE2 SE330U2VDM-L-GP 6262_UGATE2 39 B 39 C157 SCD1U25V3ZY-1GP Panasonic ETQP4LR36WFC 10*11.5*4mm 0.34uH / 24A DCR=1.1mohm 2 C186 SC10U25V6KX-1GP B C80 SC10U25V6KX-1GP D D D D U24 IRF7807ZPBF-GP DCBATOUT A A 39 6262_ISENP2 Wistron Corporation 39 6262_ISENN2 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title CPU Vcore Power_2/2 Size A3 Document Number Rev Garda-5 Date: Wednesday, April 26, 2006 SB Sheet 40 of 46 A B C D E DCBATOUT G10 S S S G 5V Iomax=6A OCP>12A GAP-CLOSE-PWR G13 5V_PWR GAP-CLOSE-PWR G15 2 TC1 ST220U6D3VDM-15GP GAP-CLOSE-PWR G16 NEC 220uF ,V size ESR=25mohm Iripple=2.2A DY 1 DY 1 C350 SCD1U50V3ZY-GP R244 30KR2F-GP C339 SC33P50V2JN-3GP Iomax=11A Qg=9.8nC, Rdson=19.6~24mohm 51120_VFB1 5V_S5 GAP-CLOSE-PWR G14 GAP-CLOSE-PWR G12 GS 10*10*4 4D7uH 5V_PWR DCR=25mohm, Isat=6A S S S G SB Modify 51120_V5FILT 51120_VBST1 0R3-0-U-GP 51120_VBST1_11 R259 SCD1U50V3ZY-GP 51120_DRVL1 GAP-CLOSE-PWR G17 R243 7K5R3F-GP 51120_COMP1 0R0402-PAD 51120_AGND 51120_DRVH2 51120_LL2 51120_VREF2 C342 SC33P50V2JN-3GP 51120_DRVL2 51120_VFB2 DY COMP N/A N/A CURRENT MODE D-Cap MODE TONSEL 380k/CH1 590k/CH2 290k/CH1 440k/CH2 220k/CH1 330k/CH2 180k/CH1 280k/CH2 DY R236 22KR2J-GP 51120_AGND ADJ VFB2 N/A not use ADJ EN1,EN2 Switcher OFF not use Swithchr ON Switcher ON EN3,EN5 not use LDO ON 51120_COMP2 not use 51120_AGND C335 SC390P50V3JN-GP DY DY R235 22KR2J-GP DY C333 SC1KP16V2KX-GP For TPS51120, Vout=5V If you use If you use If you use Vout=3.3V If you use If you use If you use a 6.8uH inductor, the minimum ESR is 70m ohm a 4.7uH inductor, the minimum ESR is 48m ohm a 3.3uH inductor, the minimum ESR is 34m ohm a 4.7uH inductor, the minimum ESR is 51m ohm a 3.3uH inductor, the minimum ESR is 36m ohm a 2.5uH inductor, the minimum ESR is 27m ohm N/A 51120_AGND VFB1 B Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title TPS51120_3D3V_5V Size A3 VREG3 on Document Number Date: Wednesday, April 26, 2006 51120_AGND A GAP-CLOSE-PWR DY C331 SC1KP16V2KX-GP 5V Fixed Output 3.3V Fixed Output LDO OFF G1 Vout=1V*(R1+R2)/R2 2 PWM DY PWM C337 SC390P50V3JN-GP AUTOSKIP AUTOSKIP /FAULTS OFF GAP-CLOSE-PWR NEC 220uF ,V size ESR=25mohm Iripple=2.2A R248 13K3R2F-L1-GP SKIPSEL V5FILT FLOAT DY GAP-CLOSE-PWR G25 R247 TC2 30K9R3F-GP ST220U6D3VDM-15GP DY 51120_COMP1 VREF2 GAP-CLOSE-PWR G24 2 Iomax=11A Qg=9.8nC, Rdson=19.6~24mohm 51120_AGND GND GAP-CLOSE-PWR G23 3D3V Iomax=6A OCP>12A IND-3D3UH-55-GP U9 AO4422-1-GP R246 0R0402-PAD GAP-CLOSE-PWR G22 3D3V_PWR L16 S S S G 15KR2F-GP 51120_CS2 R264 20KR2F-L-GP EC17 SCD1U25V3ZY-1GP 51120_TONSEL R249 0R0402-PAD SC10U25V6KX-1GP Iomax=11A AO4422-1-GP Qg=9.8nC, Rdson=20~25mohm 51120_AGND 51120_CS1 74.51120.073 U2 3D3V_S5 GAP-CLOSE-PWR G21 D D D D R266 51120_DRVH1 51120_DRVH2 C22 51120_V5FILT COMP2 COMP1 V5FILT VIN 20 22 28 13 VBST1 VBST2 24 17 33 51120_AGND 27 14 S S S G C336 SC1000P50V3JN-GP TPS51120RHBR-GPU1 DRVH1 DRVH2 C21 VREF2 51120_DRVL1 51120_DRVL2 3D3V_PWR 25 16 GAP-CLOSE-PWR G20 DCBATOUT 39,42,43 51120_VREF2 DRVL1 DRVL2 0R0402-PAD CPUCORE_ON 0R0402-PAD VO1 VO2 51120_PGOOD1 R250 51120_PGOOD2 R11 SC10U25V6KX-1GP 30 11 5V_PWR 3D3V_PWR PGOOD1 PGOOD2 GAP-CLOSE-PWR G19 VFB2 VFB1 51120_LL2 51120_LL1 15 26 2 0R0402-PAD51120_VFB2 0R0402-PAD51120_VFB1 R12 100KR2J-1-GP LL2 LL1 G18 R240 R237 U45 SKIPSEL TONSEL 51120_V5FILT 3D3V_S0 51120_SKIPSEL 32 31 EN1 EN2 EN3 EN5 CS1 CS2 29 12 10 23 18 19 21 0R0402-PAD51120_EN1 0R0402-PAD51120_EN2 TP2 TPAD28 TP1 TPAD28 1 R251 R256 R238 GAP-CLOSE-PWR DY D D D D 37 TPS51120_EN1_5 37 TPS51120_EN2_3D3 0R0402-PAD C351 R239 51120_COMP2 VREG3 VREG5 C352 SC10U10V5ZY-1GP G3 GAP-OPEN-PWR 51120_VREG3 PGND1 PGND2 GND GND SC10U10V5ZY-1GP 51120_VREG5 GAP-OPEN-PWR 1 EC12 SCD1U25V3ZY-1GP IND-4D7UH-84-GP U7 AO4406-1-GP GAP-CLOSE-PWR G11 www.kythuatvitinh.com G2 51120_AGND DCBATOUT 51120_VBST2 0R3-0-U-GP C346 51120_LL1 L17 51120_DRVH1 51120_LL1 D D D D 3D3V_AUX_S5 C349 SC1U10V3KX-3GP C347 51120_LL2 251120_VBST2_1 R260 SCD1U50V3ZY-GP TP3 TPAD30 R265 51120_VREG5 5D1R3F-GP SC10U25V6KX-1GP U6 AO4422-1-GP C13 SC10U25V6KX-1GP D D D D Iomax=11A Qg=9.8nC, Rdson=20~25mohm 51120_V5FILT C15 1 C D Rev SB Garda-5 Sheet E 41 of 46 DCBATOUT DCBATOUT_51124 G26 DCBATOUT_51124 S S S G GAP-CLOSE-PWR G35 1D8V Iomax=8A OCP>16A 1D8V_PWR GAP-CLOSE-PWR G36 2 Voutsetting=1.801V IND-3D3UH-55-GP GAP-CLOSE-PWR G37 TC3 GAP-CLOSE-PWR G38 1 R274 42K2R3F-GP SC33P50V3JN-GP U15 FDS6690DS-GP D D D D GAP-CLOSE-PWR G32 GAP-CLOSE-PWR G31 1D8V_S3 GAP-CLOSE-PWR G34 L19 51124_DRVH1 51124_LL1 GAP-CLOSE-PWR G33 1D8V_PWR C385 GAP-CLOSE-PWR G30 2 D D D D U13 FDS6612A-1-GP GAP-CLOSE-PWR G29 DY C37 SC10U25V6KX-1GP C38 SC10U25V6KX-1GP GAP-CLOSE-PWR G28 SC10U25V6KX-1GP 1 G27 Already PH at Page41 51124_DRVH2 0R3-0-U-GP C371 51124_VBST2 51124_VFB2 51124_DRVL2 SCD1U50V3ZY-GP Vout=0.75V*(R1+R2)/R2 GND TONSEL 230k/CH1 283k/CH2 OPEN 283k/CH1 346k/CH2 1 R272 51124_GND GAP-CLOSE-PWR 1 TC11 DY C364 SCD1U50V3ZY-GP Panasonic 220uF ESR=15mohm Iripple=2.7A V5FILT 346k/CH1 423k/CH2 R275 DY C362 SE220U2VDM-8GP GAP-CLOSE-PWR G65 2 SCD1U50V3ZY-GP 51124_LL2_1 IND-2D2UH-44-GP 75KR3F-GP R287 GAP-CLOSE-PWR G64 Voutsetting=1.203V SC33P50V3JN-GP 51124_GND 51124_LL2 GAP-CLOSE-PWR G63 1D2V_PWR 2 GAP-CLOSE-PWR 1D2V Iomax=6.5A OCP>13A 2 51124_GND 51124_VBST1 GAP-CLOSE-PWR G62 SCD1U50V3ZY-GP L18 51124_DRVL1 U16 AO4422-1-GP DY C39 51124_GND 51124_DRVL2 GAP-CLOSE-PWR G61 45K3R2F-L-GP 2C372 1D2V_S0 74.51124.073 C383 S S S G 0R3-0-U-GP C384 U14 AO4422-1-GP 51124_GND DY SC10U25V6KX-1GP 10KR2J-3-GP R277 0R2J-2-GP PGND1 PGND2 GND GND 18 13 25 51124_DRVH1 51124_DRVH2 G56 51124_LL1_1 GAP-CLOSE-PWR G60 DCBATOUT_51124 SC10U25V6KX-1GP 21 10 51124_V5FILT DY DRVH1 DRVH2 51124_LL2 R290 18KR2F-GP 2 51124_PGD1 51124_PGD2 24 R276 51124_TONSEL D D D D G57 GAP-CLOSE-PWR G58 GAP-CLOSE-PWR G59 R292 18KR2F-GP DRVL1 DRVL2 TRIP1 TRIP2 51124_TRIP1 51124_TRIP2 51124_GND R288 VBST1 VBST2 LL1 LL2 51124_GND GAP-CLOSE-PWR Panasonic 220uF ESR=15mohm Iripple=2.7A 1D2V_PWRGD 43 20 11 TPS51124RGER-GPU1 SA Modify 51124_LL1 EN1 EN2 GAP-CLOSE-PWR G40 1D2V_PWR TONSEL 17 14 51124_GND 51124_LL1 51124_LL2 23 0R0402-PAD GAP-CLOSE-PWR G39 51124_GND S S S G SCD01U16V2KX-3GP DY C368 V5FILT V5IN R279 C363 SCD1U50V3ZY-GP 39,41,43 D D D D DY SCD01U16V2KX-3GP C369 51124_EN1_1 51124_EN2_1 0R0402-PAD 0R0402-PAD 1 R283 R282 15 16 19 12 51124_V5FILT 0R0402-PAD CPUCORE_ON 51124_GND 18,33,43 PM_SLP_S5# 37 1D2V_EN VO1 VO2 VFB1 VFB2 U46 22 C376 SC1U6D3V2ZY-GP 1D2V_PWR 1D8V_PWR 51124_VFB2 51124_VFB1 R280 PGOOD1 PGOOD2 R291 3D3R3J-L-GP C35 SC4D7U10V5ZY-3GP R281 100KR2J-1-GP R271 5V_S5 30K1R3F-GP 51124_DRVL1 3D3V_S0 DY 51124_VFB1 S S S G GAP-CLOSE-PWR SE220U2D5VDM-3GP www.kythuatvitinh.com C361 DY Wistron Corporation Vtrip(mV)=Rtrip(Kohm)*10(uA) Iocp=(Vtrip/Rdson)+((1/(2*L*f))*((Vin-Vout)*Vout)/Vin)) 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title TPS51124_1D8V_1D2V Size A3 Document Number Date: Wednesday, April 26, 2006 Rev SA Garda-5 Sheet 42 of 46 A B C D E 1D05V_S0 Iomax=3A 1D2V_S0 0D9V Iomax=1A C394 SC4D7U10V5ZY-3GP OCP>6A R309 0R0402-PAD 42 1D2V_PWRGD POK EN VOUT VOUT FB 1D05V_PWR G67 1 U52 GAP-CLOSE-PWR 1D05V_S0 DDR_VREF_S3 GAP-CLOSE-PWR 10 18,33,42 PM_SLP_S5# G71 GAP-CLOSE-PWR VIN VDDQSNS S5 VLDOIN GND VTT S3 PGND VTTREF VTTSNS G72 GAP-CLOSE-PWR G73 GAP-CLOSE-PWR C437 SC10U10V5ZY-1GP C438 SC10U10V5ZY-1GP DY 74.51100.079 TPS51100DGQR-GP 11 GND NEC 100uF, 4V, B2 Size ESR=70mohm C443 C446 GAP-CLOSE-PWR TC12 ST100U4VBM-11-GP G69 18,20,32,33,37 PM_SLP_S3# Vo=0.8*(1+(R1/R2)) GAP-CLOSE-PWR SC10U10V5ZY-1GP R315 3K16R3F-1-GP G68 SCD1U16V2ZY-2GP 1 APL5912-KAC-GP 74.05912.A71 SOP-8 R317 C393 1KR2F-3-GP GND 1 DY SC330P50V3JN-GP SCD1U16V2ZY-2GP C444 SC1U6D3V2ZY-GP C439 SC10U10V5ZY-1GP www.kythuatvitinh.com C389 G66 Vo(cal.)=1.053V VIN VIN DDR_VREF_S0 1 Already PH at Page41 39,41,42 CPUCORE_ON VCNTL U50 1D8V_S3 0D9V_PWR 2 C397 SC1U6D3V2ZY-GP 1 C391 SC1U10V2KX-GP 5V_S5 5V_S5 2nd source: 74.02997.079 1D8V_S5 Iomax=300mA For New Card/MINI Card solution 3D3V_S5 1D8V_S5 G44 NEW ST100U4VBM-11-GP G48 APL5312-15BITRL-GP 74.05312.A3F GAP-CLOSE-PWR GAP-CLOSE-PWR GAP-CLOSE-PWR NEW Rh/Rl=(Vout/0.8)-1 R200 1K5R3F-GP 1 G45 TC10 C536 SC2D2U10V3ZY-1GP C62 NEW VIN VOUT GND SHDN# BP R196 1K33R3F-GP C541 SC1U10V2KX-GP 1 APL5308-18AC-GP 74.05308.G31 1D5V_CPU_S0 1D5V_NEW_MINI_S0 Vo(cal.)=1.5093V 74.05332.B31 NEW 1D5V_PWR VIN BS FB VOUT OCP>450mA U20 OCP>2A APL5332KAC-TRLGP GND NC#8 NC#7 GND NC#5 C265 SC10U10V5ZY-1GP SCD01U50V3KX-4GP NEW U35 C63 SC2D2U10V3ZY-1GP 1 1D5V Iomax=1A VIN VOUT GND 1D5V Iomax=120mA 3D3V_S0 20060217PM U59 3D3V_S0 C75 SC4D7U6D3V5KX-3GP Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title 1D5V/0D9V/1D05V/1D8V Size A3 Document Number Date: Wednesday, April 26, 2006 A B C D Rev SA Garda-5 Sheet E 43 of 46 BT+ DCBATOUT R257 D01R2512F-4-GP D DCBATOUT Near MAX1909 Pin SC10U35V0ZY-GP MAX1909_LDO 8725_CSSP C24 SCD1U50V3ZY-GP LDO :5.40V (< 5mA) CCV CCI CCS 8 BT+ B GAP-CLOSE G138 should close BTY CONN Pin7 V_REF :4.2235V (=2.8V = Cell C334 V( MODE ) = 1.8V = Cell MAX8725_ACIN R230 CHG_V_PWM CSSP 2 MAX8725_ICTL MAX8725_MODE R241 100KR2J-1-GP SC1U10V3ZY-6GP 2 CHG_I_PWM When V(ICTL)VCELL=VBAT/CELL =VREF+(VVCTL-1.8) /9.52 =4.1998V C338 SCD1U50V3ZY-GP C341 SCD1U50V3ZY-GP EC10 D D D D G52 GAP-CLOSE 8725_CSSN 2 CH521S-30-GP-U SCD1U50V3ZY-GP SCD1U50V3ZY-GP D17 AD+ C343 SC1U50V5ZY-1-GP ACOK is 17.8V G51 GAP-CLOSE Close to MAX8725 pin 24 R258 13K3R2F-L1-GP 1 AC_IN Threshold 2.089V Max AC_IN > 2.089V > AC DETECT 2 SCD01U50V3KX-4GP MAX8725_ACIN C330 U3 S S S G SC10U35V0ZY-GP AO4433-GP D 1 AD+_TO_SYS S S S G R262 100KR2F-L1-GP D D D D SCD1U50V3ZY-GP U43 AD+ R263 47KR2J-2-GP MAX1909_LDO ISOURCE_MAX = (0.075/R950)*(VCLS/VREF) AC_IN# A 33 Current limit setting Adapter=65W, Total_Power=58W(58W/20V=2.9A) D Wistron Corporation Q18 2N7002PT-U 84.27002.F31 MAX8725_ACOK 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title G A R253 100KR2J-1-GP CHARGER MAX8725 S Size Document Number Custom Rev Date: Wednesday, April 26, 2006 -1 Garda-5 Sheet 44 of 46 ADAPTER IN CIRCUIT AD+ DCIN1 -1 Modify 1 R1 C313 200KR3F-GP AD+_G U42 S S S G D D D D D AO4433-GP A D4 SCD1U50V3ZY-GP SCD1U50V3ZY-GP MH1 EC47 SCD47U50V5ZY EC2 EC1 SCD1U50V3ZY-GP K P4SSMJ24PT-GP AD+_JK D DC-JACK115-GP 22.10037.C51 R231 100KR2J-1-GP Q16 R2 C C B R1 90W: 22.10037.C61 E www.kythuatvitinh.com 33 PDTA144EU-1GPU Q1 CHT2222APT-GP B AD_OFF C E connect to KBC MAIN BATTERY CONNECTOR DY D19 BAV99PT-GP-U 3 D20 BAV99PT-GP-U D21 BAV99PT-GP-U 83.00099.K11 2 DY 3D3V_AUX_S5 BAT1 R269 100KR2F-L1-GP RN40 BATA_CLK_1 3BATA_DAT_1 33 BATA_SCL 33 BATA_SDA 33,44 BATA_IN# SRN33J-5-GP-U DY SYN-CON7-15-GP 20.80352.007 C29 2 B SCD1U50V3ZY-GP 2 DY C27 SCD1U50V3ZY-GP DY EC52 SC100P50V2JN-3GP EC20 2 DY SC100P50V2JN-3GP EC19 SC100P50V2JN-3GP BT+ B A A Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title AD/BATT CONN Size A3 Document Number Date: Wednesday, April 26, 2006 C KBC_3D3V_AUX Rev -1 Garda-5 Sheet 45 of 46 A B C D E EMI CAP U1C 10 14 5V_S0 DCBATOUT AD+ SCD1U25V3ZY-1GP EC53 EC77 EC74 BT+ SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP 1 EC76 SCD1U25V3ZY-1GP DY 5V_S5 SCD1U16V2ZY-2GP EC38 EC48 SCD1U25V3ZY-1GP DY SCD1U25V3ZY-1GP 1 2 DY EC9 EC21 K1 DY DY DY DY DY 1D8V_S3 H26 1D2V_S0 SPRING-9-GP SPRING-9-GP DY DY K3 K4 2 2 DY DY DY EC6 DY SCD1U16V2ZY-2GP DY EC7 2 EC18 SCD1U16V2ZY-2GP DY SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP EC26 SCD1U16V2ZY-2GP DY EC28 SCD1U16V2ZY-2GP DY EC58 SCD1U16V2ZY-2GP DY EC71 SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP DY EC56 1 DY SCD1U16V2ZY-2GP DY EC41 EC40 2 EC32 SCD1U16V2ZY-2GP DY SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP DY EC30 SCD1U16V2ZY-2GP DY EC35 SCD1U16V2ZY-2GP DY EC39 SCD1U16V2ZY-2GP DY EC60 SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP EC73 DY 1D2V_PWR DDR_VREF_S0 34.49U23.001 DY SA Rework DY EC55 EC37 EC57 SCD1U16V2ZY-2GP 34.39S07.002 EC68 34.4A907.001 DY SCD1U16V2ZY-2GP SPRING-23-GP EC31 1 SCD1U16V2ZY-2GP K2 H23 UNDER HDD MINIC MINIC DY 2 DY FOR MINIC DY VCC_CORE_S0 EC75 34.4A906.001 DY 34.4A902.001 SCD1U16V2ZY-2GP 34.4A905.001 DY 34.4A903.001 H6 SCD1U16V2ZY-2GP H2 EC29 H17 1 H27 1 34.4A904.001 H22 H14 H33 EC36 MDC H32 H10 DY 3D3V_S0 SCD1U16V2ZY-2GP IO Bracket FOR Daughter BD UMA DY 34.40U07.001 34.4A908.001 BOTTOM SIDE: 2 2 DY 1 SPRING-U3 H16 H15 www.kythuatvitinh.com H11 SCD1U16V2ZY-2GP EC24 SCD1U16V2ZY-2GP EC25 SCD1U16V2ZY-2GP EC64 SCD1U16V2ZY-2GP EC54 SCD1U16V2ZY-2GP EC34 SCD1U16V2ZY-2GP EC45 SCD1U16V2ZY-2GP EC5 1 CPU Thermal Module TOP SIDE: DY EC22 5V_USB5_S5 SCD1U16V2ZY-2GP 5V_S0 EC16 SCD1U25V3ZY-1GP DY SCD1U25V3ZY-1GP EC27 DY SCD1U25V3ZY-1GP DY EC23 2 EC49 SCD1U25V3ZY-1GP DY SCD1U25V3ZY-1GP EC72 DY SCD1U25V3ZY-1GP DY EC8 2 EC61 SCD1U25V3ZY-1GP DY SCD1U25V3ZY-1GP EC59 TSAHCT125PW-GP SCD1U25V3ZY-1GP DY H12 HOLE H13 HOLE H18 HOLE H19 HOLE 1 H9 HOLE H8 HOLE H7 HOLE H5 HOLE H21 HOLE H4 HOLE H20 HOLE H3 HOLE 1 H1 HOLE -1 Modify H24 HOLE H25 HOLE H28 HOLE H29 HOLE H30 HOLE H31 HOLE 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C 1 1 1 1 Wistron Corporation Title SPRING & BOSS Size A3 Document Number Rev Garda-5 Date: Wednesday, April 26, 2006 A B C D -1 Sheet E 46 of 46 ... 10 44 11 45 12 46 13 47 14 48 15 49 16 50 17 51 18 52 19 53 20 54 21 55 22 56 23 57 24 58 25 59 26 60 27 61 28 62 29 63 30 64 31 65 32 66 33 67 34 68 NP2 25 25 CBB_D[0 15] CBB_A[0 25] E 3D3V_S0... PCI_GNT#3 15, 23, 25, 32 PCI_FRAME# 15, 23, 25, 32 PCI_IRDY# 15, 23, 25, 32 PCI_TRDY# 15, 23, 25, 32 PCI_DEVSEL# 15, 23, 25, 32 PCI_STOP# 15, 23, 25, 32 PCI_PERR# 15, 23, 25, 32 PCI_SERR# GBUS_GRST#_1 SB 15, 23, 25, 32 PCIRST1#... CPU_DSTB3P# E16 D16 C14 B14 E 15 D 15 C13 E14 F13 B13 A12 C12 E12 D13 D12 B12 E13 F 15 G 15 H_D#48 H_D#49 H_D #50 H_D #51 H_D #52 H_D #53 H_D #54 H_D #55 H_D #56 H_D #57 H_D #58 H_D #59 H_D#60 H_D#61 H_D#62 H_D#63