Tài liệu Computer Organization pdf

System Components At the global and processor levels of computer design, we are concerned about four component “primitives” – CPUs » ALUs » Control units – Memories – I/O devices – Interconnection structures EE 4504 Computer Organization Knowledge of these components and their operation (interaction) offers insight into system bottlenecks, alternate pathways, magnitude of system failures, and opportunities for performance enhancement Section The Computer System and its Interconnection Structures EE 4504 Section EE 4504 Section 2 von Neumann’s Architecture von Neumann is credited with developing the idea of controlling the operation of hardware through the manipulation of control signals Characteristics – Both data and instructions (control sequences) are stored in a single read-write memory » Can not tell the difference between data and instructions by examining a memory location – Memory contents are addressable by location without regard for the type of data contained there – Execution occurs in a sequential fashion by reading consecutive instructions from memory – First machines (e.g., ENIAC) had to be physically rewired to change the computation being performed – von Neumann used the memory of the computer to store the sequence of the control signal manipulations required to perform a task software programming – the von Neumann architecture has been the basis for virtually all computer designs since the first generation Instruction codes Instruction Interpreter (control unit) Data in Results out Arithmetic logic unit EE 4504 Section EE 4504 Section Interrupts Instruction execution follows a set cycle The mechanism by which other system modules may interrupt the normal processing of the CPU These devices are 1-10 orders of magnitude slower than the CPU – Determine the address of the next instruction – Fetch that instruction from memory – Decode the instruction to determine what is to be performed – Calculate the addresses of needed operands and fetch the operands – Perform the operation on the operands – Store the results – Check for and service pending interrupts – CPU can waste vast amounts of processing cycles waiting for these slow devices to perform their tasks Interrupts let the CPU execute its normal instruction sequence and pause to service the external devices only when they signal (the interrupts) that they are ready for the CPU’s attention The processor and the O/S are responsible for recognizing an interrupt, suspending the user program, servicing the interrupt, and then resuming the user program Figure 3.12 State diagram for the instruction cycle EE 4504 Section EE 4504 Section Interrupts are processed in an interrupt cycle within the overall instruction cycle – At the end of an instruction cycle (operand storage step), check to see if any interrupts are pending – If there aren’t any, proceed with the next instruction – If there are » Suspend execution of the program and save its “state” » Jump to the interrupt service routine and resume the “normal” instruction cycle » When the ISR is completed, restore the state of the program and resume its operation Figure 3.8 Transfer of control via interrupts EE 4504 Section EE 4504 Section Multiple interrupts – A typical system can support several to several dozen interrupts – How should the system respond if more than interrupt occurs at the same time? » Systems prioritize the various interrupts » At the start of the interrupt cycle, the highest priority pending interrupt will be serviced » Remaining interrupt requests will be serviced in turn – What if an interrupt occurs while an ISR is being executed (a result of a previous interrupt) » Ignore the second interrupt (by disabling interrupts) until the ISR completes e.g., MC68HC11 microcontroller » Recognize and service the interrupt only if it has a higher priority than the one currently being serviced e.g., 8085 EE 4504 Section Figure 3.13 Transfer of control with multiple interrupts EE 4504 Section 10 Interconnection Structures Bus Interconnection The collection of paths that connect the system modules together form the interconnection structure Computer systems contain a number of buses that provide pathways between components – Shared transmission media connecting or more devices together – Broadcast, 1-to-all operation – Must insure only device places information onto a bus at any given time Typical buses consist of 50-100 lines Figure 3.15 Computer modules and their interconnection requirements EE 4504 Section 11 – Address information (address bus) » Specifies source/destination of data transfer » Width determines the capacity of the system – Data information (data bus) » Width is key in determining overall performance – Control information controls access to and use of the address and data bus – Miscellaneous power, ground, clock EE 4504 Section 12 Bus performance limited by – Data propagation delay through the bus -longer buses (to support more devices) require longer delays – Aggregate demand for access to the bus from all devices connected to the bus To avoid bottlenecks, multiple buses are used in most systems – Hierarchical – High-speed limited access buses close to the processor – Slower-speed general access buses farther away from the processor Figure 3.18 Hierarchical bus configurations EE 4504 Section 13 EE 4504 Section 14 Bus arbitration Bus timing – Process of insuring only devices places information onto the bus at a time – Master - slave mechanism » Master is given control of the bus and can place information onto it » Slave receives the information from the master – Two methods » Centralized Central bus controller mediates all device requests for the bus » Decentralized No centralized controller All devices contain logic to control access to the bus EE 4504 Section – Synchronous » Occurrence of events on the bus is determined by the clock » All events start at the beginning of a clock cycle » Example: PCI bus – Asynchronous » The occurrence of one event follows and depends onthe occurrence of a previous event » More flexible than synchronous bus but more complicated as well » Accomodates wider range of device speeds » Example: Futurebus+ 15 EE 4504 Section 16 PC Buses ISA (Industrial Standard Architecture) – First open system bus architecture for PCs (meaning IBM-type machines) – 8-bit and 16-bit ISA buses CPU Memory Bus drivers and glue logic ISA Bus Keyboard Bus slots Figure 3.19 Bus timing operations EE 4504 Section 17 EE 4504 Section 18 – 8-bit bus » First used in the PC-XT » 62 pins » 4.77 MHz clock » 20 address lines Mword memory » data lines » interrupt lines, DMA channels – 16-bit bus » 8-bit bus was very limiting » 16-bit bus introduced with the PC-AT and the 80286 » Augmented the existing 8-bit bus’ 62-pin connector with a 36-pin connector » 8.33 MHz clock » Total of 24 address lines 16 MB address space » 16 data lines » more interrupt lines and more DMA channels EE 4504 Section Micro Channel Architecture – Introduction of ‘386 and then ‘486 processors put a strain on the performance of the ISA bus » Slow to pass 32-bit data words in bus operations – IBM wanted to put ISA to rest and introduced the MCA in their PS/2 series of machines (late 80s) – Offered many improvements over the ISA » Higher speed » Bus arbitration » Automatic configuration – 16 and 32-bit implementations – Proprietary architecture that never caught on with users » Limited peripheral support » Large installed base of ISA equipment and low-cost replacements 19 EE 4504 Section 20 10 EISA (Extended-ISA) VESA Video Local Bus – Introduced in ‘88-89 to provide enhancements to the ISA bus – 16/32-bit data – 24/32-bit address – 8.33 MHz – Backward compatible with ISA equipment – Roughly twice the data throughput of ISA – More interrupts and DMA channels – Never really caught on viewed as a bus for “high-end” machines – Video Electronics Standards Assoc – Give video and graphics peripherals quick access to main memory – Implemented in conjunction with ISA or EISA for support of other peripherals (2 sets of connectors on motherboard) – 32/64-bit data, 24/32-bit address – Speed related to speed of the processor VL Bus slots CPU Memory Bus drivers and glue logic ISA Bus Keyboard EE 4504 Section 21 EE 4504 Section Bus slots 22 11 PCI – Peripheral Component Interface bus – Introduced in late ‘92 by Intel and a consortium of manufacturers » Effectively killed off the VL bus – Uses a 33 MHz clock, independent from that of the processor – 64-bit data and address lines (multiplexed) – Supports up to 16 slots (vs for the VL bus) – Systems also include ISA slots for compatibility – Synchronous bus, centralized bus arbitration Figure 3.21 Example PCI Configurations EE 4504 Section 23 EE 4504 Section 24 12 Summary Futurebus+ System architecture – High-performance asynchronous bus – Introduced in the late 80s – Architecture, processor, and technology independent – Support: » Parallel and arbitration protocols » Fault tolerant and high-reliability systems » Cache-based memory – Has the potential to supplant other buses because of its flexibility » Can support data bus widths of up to 256 bits – Flexibility comes at a higher implementation cost than the PCI bus so would appeal to a different target user EE 4504 Section – von Neumann structure – Instruction execution cycle Interrupts – Brief overview! – Purpose and implementation – Multiple interrupts Bus interconnections – Need for them – Survey of common buses – See Bigelow, Stephen,“Understanding PC Buses,” Circuit Cellar Ink, The Computer Applications Journal, No 50, September 1994, pp 44-51 25 EE 4504 Section 26 13 ... the computer to store the sequence of the control signal manipulations required to perform a task software programming – the von Neumann architecture has been the basis for virtually all computer. .. collection of paths that connect the system modules together form the interconnection structure Computer systems contain a number of buses that provide pathways between components – Shared transmission... places information onto a bus at any given time Typical buses consist of 50-100 lines Figure 3.15 Computer modules and their interconnection requirements EE 4504 Section 11 – Address information